Elastic membrane for semiconductor wafer polishing apparatus

FIG. 1 is a bottom plan view of an elastic membrane for semiconductor wafer polishing apparatus showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front elevation view thereof;

FIG. 4 is an enlarged perspective view of a portion taken along section 4 in FIG. 2 ;

FIG. 5 is a cross sectional view taken along line 5 - 5 in FIG. 2 ; and,

FIG. 6 is an enlarged portion view taken along line 6 - 6 in FIG. 5 .

The broken lines shown in the drawings represent portions of the elastic membrane for semiconductor wafer polishing apparatus that form no part of the claimed design. The dashed-dot-dashed lines represent the boundary lines of the claimed design.

All surfaces not shown form no part of the claimed design.