Electrodes of semiconductor memory devices having corners of acute angles

The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices and methods of forming the same.

Semiconductor memory devices can be generally split into volatile memory devices and non-volatile memory (NVM) devices. Resistive random-access memory (RRAM) devices are a type of non-volatile memory (NVM) device.

An RRAM device uses a switching layer arranged between two electrodes. The switching layer may exhibit different resistance states, such as a high-resistance state and a low-resistance state. The RRAM device may operate by switching between those resistance states to represent one or more bits of information.

The switching layer is normally insulating and exhibits a high-resistance state. The resistance states of the RRAM device may be changed to a low-resistance state by applying a suitable potential difference between the electrodes to form conductive filaments in the switching layer. However, the conductive filaments are often randomly formed across many locations within the switching layer, thereby subjecting the RRAM device to poor electrical performance with undesirable device-to-device variability and cycle-to-cycle variability.

To achieve the foregoing and other aspects of the present disclosure, semiconductor memory devices and methods of forming the same are presented.

According to an aspect of the present disclosure, a memory device is provided. The memory device includes a dielectric layer having a top surface, a first electrode having a bottom surface, a switching layer, and a second electrode. The bottom surface of the first electrode is arranged below the top surface of the dielectric layer. The first electrode includes a first corner having a first acute angle and a second corner having a second acute angle arranged above the top surface of the dielectric layer. The switching layer is arranged over the first electrode. The second electrode is arranged over the switching layer, and at least the first corner of the first electrode extends into the second electrode.

According to another aspect of the present disclosure, a memory device is provided. The memory device includes a first dielectric layer having a top surface, a first bottom electrode having a bottom surface, a second bottom electrode, a switching layer, and a first top electrode. The bottom surface of the first top electrode is arranged below the top surface of the first dielectric layer. The second bottom electrode is arranged immediately adjacent to and substantially parallel to the first bottom electrode. The first bottom electrode and the second bottom electrode each includes a first corner having a first acute angle and a second corner having a second acute angle arranged above the top surface of the dielectric layer. The first corner of the second bottom electrode is arranged proximate to the first corner of the first bottom electrode. The switching layer is arranged over the first bottom electrode and the second bottom electrode. The first top electrode is arranged over the switching layer and the first corner of the first bottom electrode and the first corner of the second bottom electrode extend into the first top electrode.

According to yet another aspect of the present disclosure, a method of forming a memory device is provided. The method includes forming a first electrode including a first corner having a first acute angle, a second corner having a second acute angle, and a bottom surface arranged below a top surface of a dielectric layer. A switching layer is formed over the first electrode. A second electrode is formed over the switching layer, and at least the first corner of the first electrode extends into the second electrode.

The embodiments of the present disclosure will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawings:

FIG. 1 A is a perspective view of a memory device and FIG. 1 B is a cross-sectional view of the memory device (taken across a line A-A′), according to an embodiment of the disclosure.

FIGS. 1 C through 1 E are cross-sectional views illustrating exemplary embodiments of the memory device in FIG. 1 B .

FIG. 2 A is a top-down view of a memory device and FIG. 2 B is a cross-sectional view of the memory device (taken along a line B-B′), according to another embodiment of the disclosure.

FIG. 3 is a top-down view of a memory device, according to yet another embodiment of the disclosure.

FIGS. 4 A to 4 D are cross-sectional views that illustrate a method of forming electrodes of a memory device, according to an embodiment of the disclosure.

FIG. 5 is a cross-sectional view of a memory device, according to an alternative embodiment of the disclosure.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the device.

Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the device. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.

The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices and methods of forming the same.

Various embodiments of the present disclosure are now described in detail with accompanying drawings. It is noted that like and corresponding elements are referred to by the use of the same reference numerals. The embodiments disclosed herein are exemplary, and not intended to be exhaustive or limiting to the disclosure.

FIG. 1 A is a perspective view of a memory device 100 and FIG. 1 B is a cross-sectional view of the memory device 100 (taken across a line A-A′), according to an embodiment of the disclosure. FIGS. 1 C through 1 E are cross-sectional views illustrating exemplary cross-sectional embodiments of the memory device 100 . The memory device 100 may be arranged in a memory cell region of a semiconductor device (not shown) and the memory device 100 may be part of a plurality of memory devices arranged in an array configuration of rows and columns in the memory cell region.

The memory device 100 may include a plurality of electrodes 102 and a plurality of electrodes 104 arranged over the plurality of electrodes 102 . The plurality of electrodes 102 may be arranged substantially parallel to each other, and the plurality of electrodes 104 may be arranged substantially parallel to each other. The plurality of electrodes 104 may be arranged substantially perpendicular to a lengthwise direction of the plurality of electrodes 102 . As used herein, the term “lengthwise direction” is a direction along which a feature, such as the electrode 102 , extends the most. In an embodiment of the disclosure, the electrodes 102 may be referred to as bottom electrodes, and the electrodes 104 may be referred to as top electrodes.

Each electrode 102 may be electrically coupled to at least one electrode 104 . As used herein, when an element is referred to as being “connected” or “coupled” to another element, the element can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

The electrode 102 and the electrode 104 may include a conductive material, for example, a semiconductor material, a metallic material, or combinations thereof. The semiconductor material may include, for example, monocrystalline silicon, polycrystalline silicon, germanium, or combinations thereof. The metallic material may include, for example, copper, aluminum, tungsten, cobalt, nickel, hafnium, gold, silver, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. In an embodiment of the disclosure, the electrode 102 may include the same conductive material as the electrode 104 . In another embodiment of the disclosure, the electrode 102 may include a different conductive material than the electrode 104 .

The plurality of electrodes 102 may be partially arranged in a dielectric layer 106 . For example, the dielectric layer 106 may have a top surface 106 T and each electrode 102 may have a lower portion arranged in the dielectric layer 106 and an upper portion extending above the top surface 106 T of the dielectric layer 106 , as illustrated in FIG. 1 B . The dielectric layer 106 may serve to electrically isolate each electrode 102 from adjacent conductive features, such as an adjacent electrode 102 . The dielectric layer 106 may include an electrically insulative material, for example, silicon oxide, carbon-doped silicon oxide, tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or amorphous silicon.

In an embodiment of the disclosure, the plurality of electrodes 102 may be configured as conductive line structures and may function as word lines of the memory device 100 . The plurality of electrodes 104 may also be configured as conductive line structures and may function as bit lines of the memory device 100 . The memory device 100 may be arranged in a crossbar array configuration, for example, a plurality of bit lines and a plurality of word lines arranged in multiple rows and columns. Even though the memory device 100 is illustrated to include four bit lines BL 1 through BL 4 arranged in a column configuration and three word lines WL 1 through WL 3 arranged in a row configuration, the memory device 100 may take on other array configurations without departing from the spirit and scope of the present disclosure.

The memory device 100 may include a plurality of memory cells and each memory cell may be arranged at an intersection of a word line and a bit line. For example, as illustrated in FIG. 1 B , the memory device 100 may include a memory cell MC 1 and a memory cell MC 2 arranged along a common word line WL 1 . In another example, the memory cell MC 1 may be arranged at the intersection of the bit line BL 2 and the word line WL 1 , and the memory cell MC 2 may be arranged at the intersection of the bit line BL 3 and the word line WL 1 . Each memory cell MC 1 /MC 2 may correspond to a one-bit memory cell.

The electrode 102 may include a bottom surface 102 B, a side surface 102 S 1 , a side surface 102 S 2 , and a top surface 102 T arranged above the bottom surface 102 B. The bottom surface 102 B of the electrode 102 may be substantially parallel to the top surface 106 T of the dielectric layer 106 and may be arranged at a level lower than the top surface 106 T. The side surface 102 S 1 and the side surface 102 S 2 may extend parallel to the lengthwise direction of the electrode 102 . The side surface 102 S 1 may adjoin one end of the bottom surface 102 B and one end of the top surface 102 T, and the side surface 102 S 2 may adjoin the opposite ends of the bottom surface 102 B and the top surface 102 T. The side surface 102 S 1 may be substantially parallel to the side surface 102 S 2 , as illustrated in FIGS. 1 A and 1 B . Alternatively, the side surface 102 S 1 and the side surface 102 S 2 may be tapered from the bottom surface 102 B to the top surface 102 T such that the width dimension between the side surface 102 S 1 and the side surface 102 S 2 decreases with increasing distance from the bottom surface 102 B, as illustrated in FIG. 1 C .

The top surface 102 T of the electrode 102 may have a concave surface profile, i.e., the top surface 102 T may extend inwardly towards the bottom surface 102 B of the electrode 102 . The top surface 102 T may include at least a top surface portion 102 T 1 and a top surface portion 102 T 2 . The top surface portion 102 T 1 and the top surface portion 102 T 2 may taper inwardly towards the bottom surface 102 B of the electrode 102 . For example, the top surface portion 102 T 1 may adjoin the side surface 102 S 1 to converge to a corner 102 C 1 having an acute angle, i.e., an angle of less than 90 degrees, and the top surface portion 102 T 2 may adjoin the side surface 102 S 2 to converge to a corner 102 C 2 having an acute angle. The acute angle of the corner 102 C 1 may be substantially similar to the acute angle of the corner 102 C 2 .

In another example, the top surface 102 T may extend to a maximum depth d 1 below the corner 102 C 1 (or the corner 102 C 2 ), the maximum depth d 1 is where the top surface 102 T and the bottom surface 102 B of the electrode 102 are vertically closest to each other. The electrode 102 may have a thickness t 1 that corresponds to the height of the side surface 102 S 1 (or the side surface 102 S 2 ), and a thickness t 2 that corresponds to the distance between the bottom surface 102 B and the top surface 102 T at the maximum depth d 1 .

The corner 102 C 1 of the electrode 102 may extend along the side surface 102 S 1 and the corner 102 C 2 may extend along the side surface 102 S 2 in the lengthwise direction of the electrode 102 , as illustrated in FIG. 1 A . The corner 102 C 1 and the corner 102 C 2 may be substantially pointed, for example, the top surface portion 102 T 1 and the side surface 102 S 1 acquiring an inverted “V-shaped” profile, or substantially rounded, for example, the top surface portion 102 T 1 and the side surface 102 S 1 acquiring an inverted “U-shaped” profile.

As mentioned above, the electrode 102 may be partially arranged in the dielectric layer 106 . Specifically, at least the corner 102 C 1 and the corner 102 C 2 of the electrode 102 may be arranged above the dielectric layer 106 , i.e., the corner 102 C 1 and the corner 102 C 2 may be spaced apart from the top surface 106 T of the dielectric layer. For example, the entire top surface 102 T of the electrode 102 may be arranged above and spaced apart from the dielectric layer 106 , as illustrated in FIG. 1 B . Alternatively, a portion of the top surface 102 T of the electrode 102 may be arranged at a level lower than the top surface 106 T of the dielectric layer 106 , as illustrated in FIG. 1 E .

The top surface 102 T of the electrode 102 may include various top surface profiles. In an embodiment of the disclosure, the top surface portion 102 T 1 and the top surface portion 102 T 2 may each have a substantially flat surface profile, for example, the cross-sectional view of the electrode 102 as shown in FIG. 1 B illustrates the top surface portion 102 T 1 and the top surface portion 102 T 2 as each having a substantially straight line. In another example, the top surface portion 102 T 1 and the top surface portion 102 T 2 may taper inwardly towards the bottom surface 102 B of the electrode 102 with a substantially similar constant gradient of an absolute value. The top surface portion 102 T 1 and the top surface portion 102 T 2 may converge to form a “V-shaped” groove.

In another embodiment of the disclosure, the top surface portion 102 T 1 and the top surface portion 102 T 2 may each have a convex surface profile, as illustrated in FIG. 1 D . For example, the top surface portion 102 T 1 may taper inwardly towards the bottom surface 102 B of the electrode 102 with a gentler gradient proximate to the corner 102 C 1 and a steeper gradient proximate to the top surface 106 T of the dielectric layer 106 . Similarly, the top surface portion 102 T 2 may include a gentler gradient proximate to the corner 102 C 2 and a steeper gradient proximate to the top surface 106 T of the dielectric layer 106 .

FIG. 1 E illustrates yet another top surface profile of the electrode 102 , according to an embodiment of the disclosure. The top surface 102 T of the electrode 102 may further include a top surface portion 102 T 3 arranged between and adjoining the top surface portion 102 T 1 and the top surface portion 102 T 2 . For example, the top surface portion 102 T 3 may converge with the top surface portion 102 T 1 and the top surface portion 102 T 2 to form two laterally opposite corners each having an angle of at least 90 degrees; the corners may be substantially sharp or substantially rounded. The top surface portions 102 T 1 , 102 T 2 , and 102 T 3 may form a “U-shaped” groove. The top surface portion 102 T 3 may be arranged at a maximum depth D 2 below the corner 102 C 1 or the corner 102 C 2 to form a “U-shaped” groove.

The top surface portion 102 T 3 may have a substantially flat surface profile and may be arranged substantially parallel to the bottom surface 102 B of the electrode 102 . As illustrated, the top surface portion 102 T 3 may be arranged at a level lower than the top surface 106 T of the dielectric layer 106 . Alternatively, the top surface portion 102 T 3 may be arranged above and spaced apart from the top surface 106 T the dielectric layer 106 .

Even though the top surface portion 102 T 1 and the top surface portion 102 T 2 of the electrode 102 in FIG. 1 E are illustrated to have substantially flat surface profiles, the top surface portion 102 T 1 and the top surface portion 102 T 2 may each have a convex surface profile, similar to the top surface portion 102 T 1 and the top surface portion 102 T 2 illustrated in FIG. 1 D .

The memory device 100 may further include a switching layer 108 arranged between the electrode 102 and the electrode 104 . The switching layer 108 may be conformal to the top surface 102 T of the electrode 102 , i.e., the switching layer 108 may have a substantially equal thickness and has a portion that follows the surface profile of the portion of the electrode 102 that extends above the top surface 106 T of the dielectric layer 106 . For example, the switching layer 108 may at least overlay the corner 102 C 1 and the corner 102 C 2 of the electrode 102 , i.e., a portion of the switching layer 108 may overlay a portion of the side surface 102 S 1 , a portion of the side surface 102 S 2 , a portion of the top surface portion 102 T 1 and a portion of the top surface portion 102 T 2 . In another example, the switching layer 108 may also include a corner 108 C 1 having an acute angle and a corner 108 C 2 having an acute angle. The corner 108 C 1 and the corner 108 C 2 of the switching layer 108 may be proximate to the corner 102 C 1 and the corner 102 C 2 of the electrode 102 , respectively.

The switching layer 108 may include a resistive dielectric material, for example, silicon oxide, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, tungsten oxide, zirconium oxide, gadolinium oxide, magnesium oxide, or combinations thereof. In an embodiment of the disclosure, the switching layer 108 may have a thickness ranging from about 2 nm to about 10 nm.

The electrode 102 may be partially arranged in the electrode 104 . For example, at least the corner 102 C 1 and the corner 102 C 2 of the electrode 102 may be arranged in the electrode 104 . The corner 102 C 1 and the corner 102 C 2 of the electrode 102 may extend into and terminate within the electrode 104 , i.e., the corner 102 C 1 and the corner 102 C 2 may not extend through the electrode 104 and a portion of the electrode 104 may be arranged over the corner 102 C 1 and the corner 102 C 2 of the electrode 102 . In another example, the electrode 104 may include a bottom surface 104 B, and the bottom surface 104 B of the electrode 104 may be arranged at a level lower than the corner 102 C 1 and the corner 102 C 2 of the electrode 102 . The electrode 104 may further include a top 104 T and the top surface 104 T of the electrode 104 may have a substantially flat surface profile.

The memory device 100 may include a filament-type resistive random-access memory (RRAM) device such as, but is not limited to, an oxide random-access memory (OxRAM) device or a conductive bridge random-access memory (CBRAM) device. The switching layer 108 may exhibit different resistance states, such as a high-resistance state and a low-resistance state, and the memory device 100 may operate by switching between those resistance states of the switching layer 108 . The low-resistance state and the high-resistance state of the switching layer 108 may be used to represent one or more bits of information.

To program the memory device 100 , a suitable potential difference may be applied between the electrode 102 and the electrode 104 to cause a dielectric breakdown of the switching layer 108 . Conductive paths in a form of conductive filaments may be formed in the switching layer 108 . The conductive filaments may be formed by diffusion or drift of electrical charges, for example, ions or electrons, from the electrode 104 or the electrode 102 induced by the potential difference to the other electrode. The conductive filaments may provide electrical coupling between the electrode 102 and electrode 104 , and the switching layer 108 may be conductive and may exhibit a low-resistance state; the low-resistance state is representative of an “on” or “1” state.

To erase the memory device 100 , a suitable potential difference may be applied between the electrode 102 and the electrode 104 to break the conductive filaments in the switching layer 108 , reverting the switching layer 108 to the insulative high-resistance state; the high-resistance state is representative of an “off” or “0” state.

The corner 102 C 1 and the corner 102 C 2 of the electrode 102 may advantageously improve the electrical performance of the memory device 100 . Electric fields generated at corners or tapered regions of conductive structures may be relatively stronger than that of non-corner regions, i.e., a stronger localization of electric fields may be generated around the corner 102 C 1 and the corner 102 C 2 of the electrode 102 . Therefore, during a program operation, the relatively stronger electric fields generated around the corner 102 C 1 and the corner 102 C 2 of the electrode 102 may substantially confine the formation of the conductive filaments to a region in the switching layer 108 that is proximate to the corner 102 C 1 and the corner 102 C 2 .

The ability to confine the formation of the conductive filaments is advantageous to minimize the variability of locations where the conductive filaments may be formed. The conductive filaments may not randomly form within the switching layer 108 . Such filament confinement may reduce the stochasticity of the conductive filaments, which in turn reduces the resistance variability of the switching layer 108 in the high-resistance state. Controlled distribution of the conductive filaments may enhance the electrical performance of the memory device 100 , such as providing low device-to-device variability and cycle-to-cycle variability. Accordingly, the memory device 100 may achieve stable switching between the resistance states of the switching layer 108 during the program operations and the erase operations and may also reduce the overall power consumption of the memory device 100 .

FIG. 2 A is a top-down view of a memory device 200 and FIG. 2 B is a cross-sectional view of the memory device 200 (taken along a line B-B′), according to another embodiment of the disclosure. The memory device 200 may be similar to the memory device 100 in FIGS. 1 A and 1 B , and thus common features are labeled with the same reference numerals and need not be discussed.

The memory device 200 may include a plurality of electrodes 204 arranged above the plurality of electrodes 102 . The plurality of electrodes 204 may be arranged in a regular array configuration of multiple rows and columns. For example, each electrode 204 may be substantially aligned in a row configuration with an adjacent electrode 204 and in a column configuration with another adjacent electrode 204 . Each electrode 204 may be electrically coupled to a conductive line that may function as a word line of the memory device 200 .

The plurality of electrodes 204 may be arranged in a dielectric layer 206 and the dielectric layer 206 may serve to electrically isolate the plurality of electrodes 204 from each other. The dielectric layer 206 may be arranged over a portion of the top surface 102 T of the electrode 102 . The dielectric layer 206 may include an electrically insulative material, for example, silicon oxide, carbon-doped silicon oxide, tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or amorphous silicon and may not necessarily include the same electrically insulative material as the dielectric layer 106 .

Each electrode 204 may be at least partially arranged over at least one electrode 102 . For example, the electrode 204 may partially overlay two electrodes 102 , i.e., the corner 102 C 2 of the electrode 102 and the corner 102 C 1 of an immediately adjacent electrode 102 . In another example, the electrode 204 may include a side surface 204 S 1 that terminates over the top surface portion 102 T 2 of the electrode 102 and a laterally opposite side surface 204 S 2 that terminates over the top surface portion 102 T 2 of the adjacent electrode 102 .

The electrode 204 may form a memory cell MC 3 with the electrode 102 and a memory cell MC 4 with the adjacent electrode 102 . The memory device 200 may include a higher density of memory cells than the memory device 100 in FIG. 1 A .

FIG. 3 is a top-down view of a memory device 300 , illustrating an alternative arrangement of a plurality of electrodes 304 , according to yet another embodiment of the disclosure. The memory device 300 may be similar to the memory device 200 in FIG. 2 A , and thus common features are labeled with the same reference numerals and need not be discussed.

The plurality of electrodes 304 may be arranged over the plurality of electrodes 102 . The plurality of electrodes 304 may be arranged in a staggered array configuration. For example, each electrode 304 may be offset from an immediately adjacent electrode 304 . Similar to the memory device 200 , each electrode 304 may be at least partially arranged over at least one electrode 102 and may be electrically coupled to a conductive line that may function as a word line of the memory device 300 .

FIGS. 4 A to 4 D are cross-sectional views that illustrate a method of forming a plurality of electrodes 102 of a memory device 400 , according to an embodiment of the disclosure. The memory device 400 may be similar to the memory device 100 in FIG. 1 B , and thus common features are labeled with the same reference numerals. Certain structures may be fabricated, for example, using known processes and techniques, and specifically disclosed processes and methods may be used to achieve individual aspects of the present disclosure.

As used herein, “deposition techniques” refer to the process of applying a material over another material (or a substrate). Exemplary techniques for deposition include, but are not limited to, spin-on coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), or electro-plating.

Additionally, “patterning techniques” include deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described pattern, structure, or opening 420 . Exemplary examples of techniques for patterning include, but are not limited to, wet etch lithographic processes, dry etch lithographic processes, or direct patterning processes.

As illustrated in FIG. 4 A , a dielectric layer 106 having a top surface 106 T may be provided. Openings 402 may be formed in the dielectric layer 106 using a patterning technique. The openings 402 may have a width that substantially corresponds to the width of the electrodes 102 that will be subsequently formed. Even though the openings 402 are illustrated to terminate within the dielectric layer 106 , this may not be necessarily so, and the openings 402 may extend through the dielectric layer 106 . The dielectric layer 106 may include an electrically insulative material, for example, silicon oxide, carbon-doped silicon oxide, tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or amorphous silicon.

FIG. 4 B illustrates the memory device 400 after depositing a layer of conductive material 404 in the openings 402 , according to an embodiment of the disclosure. The conductive material 404 may be deposited using a deposition technique to overfill the openings 402 such that the conductive material 404 may overlay the top surface 106 T of the dielectric layer 106 . The conductive material 404 may include a semiconductor material, a metallic material, or combinations thereof.

Due to the presence of the openings 402 in the dielectric layer 106 , the conductive material 404 may not achieve a substantially flat surface profile. For example, the conductive material 404 may acquire a top surface 404 U including a top surface portion 404 T 1 having a substantially flat surface profile and a top surface portion 404 TU 2 having a concave surface profile. The top surface portion 404 T 1 may be arranged above the top surface 106 T of the dielectric layer 106 and the top surface 404 T 2 may be arranged above the openings 402 of the dielectric layer 106 .

The top surface portion 404 T 2 may extend inwardly to a maximum depth d 3 from the top surface portion 404 T 1 ; the maximum depth d 3 is where the top surface portion 404 T 2 and a plane P 1 that is substantially coplanar with the top surface 106 T of the dielectric layer 106 are vertically closest to each other. For example, the conductive material 404 may have a thickness t 3 that corresponds to a distance between the top surface portion 404 T 1 and the plane P 1 , and a thickness t 4 that corresponds to a distance between a plane P 2 substantially coplanar with the maximum depth d 3 of the top surface portion 404 T 2 and the plane P 2 ; the thickness t 4 is thinner than the t 3 thickness.

In an embodiment of the disclosure, a liner may be deposited in the openings 402 before the deposition of the conductive material 404 , although not shown in FIG. 4 B . The liner may include an adhesion liner and/or a barrier liner. The liner may include metal silicides or metal nitrides. The metal silicides may include, for example, titanium silicide or nickel silicide. The metal nitrides may include, for example, titanium nitride or tantalum nitride.

FIG. 4 C illustrates the memory device 400 after forming the plurality of electrodes 102 , according to an embodiment of the disclosure. A portion of the conductive material 404 may be removed until the top surface 106 T of the dielectric layer 106 is exposed, leaving a portion of the conductive material 404 in the openings 402 of the dielectric layer 106 to form the electrodes 102 .

The removal of the conductive material 404 may be performed using a directional material removal technique, such as an anisotropic etching process. Due to the substantially constant material removal rate of the material removal technique, the electrodes 102 may acquire a concave top surface 102 T having at least a top surface portion 102 T 1 and a top surface portion 102 T 2 . The concave top surface 102 T may form a corner 102 C 1 and a corner 102 C 2 having acute angles with side surfaces 102 S 1 and 102 S 2 of the electrode 102 .

FIG. 4 D illustrates the memory device 400 after recessing the dielectric layer 106 , according to an embodiment of the disclosure. The dielectric layer 106 may be recessed to a depth below the corner 102 C 1 and the corner 102 C 2 of the electrode 102 to form the recessed dielectric layer 106 ′; the portion of the dielectric layer 106 removed is demarcated by a dotted line. The dielectric layer 106 may be recessed to a depth D 4 as illustrated, for example, the top surface 106 T′ of the recessed dielectric layer 106 ′ may be arranged below and spaced apart from the top surface 102 T of the electrode 102 , though not necessarily so, as long as the corner 102 C 1 and the corner 102 C 2 of the electrode 102 extend above and spaced apart from the top surface 106 T′ of the recessed dielectric layer 106 ′.

The memory device 400 may undergo further processing steps, such as depositing a resistive dielectric material over the electrodes 102 to form a switching layer and depositing and patterning a conductive material over the switching layer to form the electrodes 104 as illustrated in FIG. 1 A, 2 A , or 3 .

FIG. 5 is a cross-sectional view of a memory device 500 , according to an alternative embodiment of the disclosure. The memory device 500 may be similar to the memory device 100 in FIG. 1 B , and thus common features are labeled with the same reference numerals and need not be discussed.

The plurality of electrodes 102 may be arranged in a substrate 510 of the memory device 500 . The substrate 510 may have a top substrate surface 510 T. The substrate 510 may include various configurations, such as a bulk semiconductor material or a composite material, for example, a semiconductor-on-insulator (SOI) substrate having a single crystalline semiconductor material, a buried insulator layer under the single crystalline semiconductor material, and a carrier substrate under the buried insulator layer. The semiconductor substrate may include any suitable semiconductor material, such as silicon, silicon germanium, silicon carbon, other II-VI or III-V semiconductor compounds, and the like.

A plurality of substrate openings (not shown) may be arranged in the substrate 510 , within which each electrode 102 and the dielectric layer 106 may be arranged therein. The plurality of substrate openings may be formed by a patterning technique, and the plurality of substrate openings may not extend through the substrate 510 . In an embodiment where the substrate 510 includes a composite material, the plurality of substrate openings may be formed in the single crystalline semiconductor material. The corner 102 C 1 and the corner 102 C 2 of the electrode 102 may or may not extend above the substrate opening. For example, as illustrated in FIG. 5 , the corner 102 C 1 and the corner 102 C 2 of the electrode 102 may be arranged below the top substrate surface 510 T. Alternatively, the corner 102 C 1 and the corner 102 C 2 of the electrode 102 may be arranged above the top substrate surface 510 T, even though this embodiment is not illustrated in the accompanying drawings.

A spacer liner 512 may be arranged in the plurality of substrate openings. The spacer liner 512 may be formed by a conformal deposition technique, for example, an ALD process or a conformal CVD process. The spacer liner 512 may be fully arranged within the substrate opening, according to an embodiment of the disclosure. In an alternative embodiment of the disclosure, a portion of the spacer liner 512 may be fully arranged within the substrate opening and another portion of the spacer liner 512 may be arranged over the upper surface 510 U of the substrate. The spacer liner 512 may include an electrically insulative material, for example, silicon nitride or silicon oxide-silicon nitride-silicon oxide (ONO).

The dielectric layer 106 may partially fill the substrate opening. For example, the dielectric layer 106 may be arranged such that a lower portion of the electrode 102 may be arranged therein, and an upper portion of the electrode 102 may extend over the top surface 106 T of the dielectric layer 106 . Accordingly, the top surface 106 T of the dielectric layer 106 may be arranged below the top substrate surface 510 T. The dielectric layer 106 may be preferably formed by a conformal deposition technique, such that a dielectric opening (not shown) may be inherently formed, within which the electrode 102 may be arranged therein. In the embodiment where the dielectric layer 106 is formed by a non-conformal deposition technique, the dielectric opening may be subsequently formed by a patterning technique.

The switching layer 108 may be arranged over the electrode 102 . A portion of the switching layer 108 may be fully arranged in the substrate opening and another portion of the switching layer 108 may be arranged over the top surface 510 U of the substrate 510 . The switching layer 108 may be conformal and a portion of the switching layer 108 may at least follow the surface profile of the electrode 102 that extends above the top surface 106 T of the dielectric layer 106 in the substrate opening. The switching layer 108 may be further arranged over the top surface 102 T of the electrode 102 , the top surface 106 T of the dielectric layer 106 , a portion of the spacer liner 512 , and the top substrate surface 510 T. The spacer liner 512 may be formed by a conformal deposition technique.

The electrode 104 may be at least partially arranged over one electrode 102 such that at least the corner 102 C 1 or the corner 102 C 2 of the electrode 102 may be arranged in the electrode 104 . The electrode 104 may be formed by a deposition technique.

The terms “top”, “bottom”, “over”, “under”, and the like in the description and the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the devices described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Additionally, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.

Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in an embodiment” herein do not necessarily all refer to the same embodiment.

In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of materials, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about”.

Furthermore, approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “approximately”, “about,”, “substantially” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value. In other instances, the approximating language may correspond to within normal tolerances of the semiconductor industry. For example, “substantially coplanar” means substantially in a same plane within normal tolerances of the semiconductor industry, and “substantially perpendicular” means at an angle of 90 degrees plus or minus a normal tolerance of the semiconductor industry.

While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that a number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the device in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.