Passivation structure for metal pattern

This application is a non-provisional application of claims priority to U.S. Provisional Patent Application Ser. No. 63/230,207, filed Aug. 6, 2021, the disclosure of which is hereby incorporated by reference in its entirety.

The semiconductor integrated circuit (IC) industry has experienced rapid growth, with each generation utilizing smaller and more complex circuits. However, such advances increase the complexity of processing and manufacturing and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased.

With such decreasing geometry size in ICs, physical stress due to temperature changes may be critical.

Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 A is a diagram of a layout of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 1 B is a cross-section of the semiconductor device of FIG. 1 A along line AA′, in accordance with some embodiments of the present disclosure.

FIG. 2 A is a diagram of a layout of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 2 B is a cross-section of the semiconductor device of FIG. 2 A along line BB′, in accordance with some embodiments of the present disclosure.

FIG. 3 is a cross-section of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 4 is a cross-section of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIGS. 5 to 9 illustrate various stages of manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 10 is a flowchart illustrating a method of manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 11 is a cross-section of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 12 is a cross-section of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 13 is a cross-section of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIG. 14 is a cross-section of a semiconductor device, in accordance with some embodiments of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, although terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another. Terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

Metal pads, such as soldering pads or wire bonding pads, have been used for various IC applications. In order to function properly, a metal pad should have sufficient size and strength to withstand physical stress from such actions as soldering or wire bonding. However, the ever-decreasing geometry size of ICs has further dictated a reduction in the size of metal pads, and often conventional metal pads and passivation layers may suffer from problems such as peeling or cracking in layers surrounding the metal pads.

The present disclosure provides a novel semiconductor including a via and a passivation of improved design to provide support for a metal pad.

FIG. 1 A is a diagram of a layout of a semiconductor device 100 , in accordance with some embodiments of the present disclosure. In FIG. 1 A , the x-axis may be horizontal, the y-axis may be vertical, and the z-axis may be orthogonal to the plane of the figure.

The semiconductor device 100 includes pads 110 and 120 and vias 111 , 112 , 121 , and 122 . The pads 110 and 120 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof. The vias 111 , 112 , 121 , and 122 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof. In some embodiments, the pad 110 and vias 111 and 112 may be formed in a single process (e.g., a deposition process). The pad 120 and vias 121 and 122 may be formed in a single process (e.g., a deposition process).

In FIG. 1 A , the pad 110 may connect with the vias 111 and 112 . The pad 120 may connect with the vias 121 and 122 . The vias 111 and 112 may be formed at a level lower than that of pad 110 . The vias 121 and 122 may be formed at a level lower than that of pad 120 .

The semiconductor device 100 of the present disclosure may be manufactured under processes of different nanometer scale. For example, the semiconductor device 100 may be manufactured under a 28 nm process. In some embodiments, the width W 1 of the pad 110 may be from 3.5 μm to 6 μm. The width W 1 of the pad 120 may be from 3.5 μm to 6 μm. The pads 110 and 120 may be spaced apart by the spacing S 1 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 1 may not exceed 5 μm.

In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the width W 2 of the via 111 may be from 1 μm to 1.7 μm. In an embodiment, the width W 2 may be 1.7 μm. The width W 2 of the via 112 may be from 1 μm to 1.7 μm. In an embodiment, the width W 2 may be 1.7 μm. The width W 2 of the via 121 may be from 1 μm to 1.7 μm. In an embodiment, the width W 2 may be 1.7 μm. The width W 2 of the via 122 may be from 1 μm to 1.7 μm. In an embodiment, the width W 2 may be 1.7 μm.

In some embodiments, the semiconductor device 100 may be manufactured under processes of different nanometer scale. In some embodiments, the ratio of W 2 to W 1 may be from 0.16 to 0.48. When the ratio of the width of the vias to the width of the pads (e.g., W 2 /W 1 ) is from 0.16 to 0.48, passivation cracking between the two pads (e.g., pads 110 and 120 ) may be effectively avoided. The reasons why passivation cracking between the two pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the length L 1 of the pad 110 may be from 10 μm to 2000 μm. The length L 1 of the pad 120 may be from 10 μm to 2000 μm. When lengths of pads 110 and 120 are substantially identical and pads 110 and 120 parallel, the parallel run length (PRL) of pads 110 and 120 may be from 10 μm to 2000 μm.

In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the length L 2 of the via 111 may be from 5 μm to 30 μm. In an embodiment, the length L 2 may be 7.2 μm. The length L 2 of the via 112 may be from 5 μm to 30 μm. In an embodiment, the length L 2 may be 7.2 μm. The length L 2 of the via 121 may be from 5 μm to 30 μm. In an embodiment, the length L 2 may be 7.2 μm. The length L 2 of the via 122 may be from 5 μm to 30 μm. In an embodiment, the length L 2 may be 7.2 μm.

In some embodiments, the ratio of W 2 to L 2 does not exceed 0.34. When the ratio of the width of the vias to the length of the vias (e.g., W 2 /L 2 ) does not exceed 0.34, passivation cracking between the two pads (e.g., pads 110 and 120 ) may be effectively avoided. The reasons why passivation cracking between the two pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

In FIG. 1 A , the distance D 1 may be measured from the left side of the via 111 (or via 112 ) to the left side of the pad 110 along the width (e.g., the width W 1 or W 2 ). The distance D 1 along the width may be measured from the boundary of the via 111 (or via 112 ) to the boundary of the pad 110 on the same side (e.g., the left side). When the via 111 (or via 112 ) is located at the center of the pad 110 along the width, the distance between the right side of the via 111 (or via 112 ) and the right side of the pad 110 may be substantially identical to the distance D 1 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the distance D 1 may be from 0.9 μm (e.g., W 1 =3.5 μm, W 2 =1.7 μm) to 2.5 μm (e.g., W 1 =6 μm, W 2 =1 μm). In some embodiments, the ratio of D 1 to W 2 may be from 0.52 (e.g., D 1 =0.9 μm, W 2 =1.7 μm) to 2.5 (e.g., D 1 =2.5 μm, W 2 =1 μm). In some embodiments, the ratio of D 1 to W 1 may be from 0.25 (e.g., D 1 =0.9 μm, W 1 =3.5 μm) to 0.42 (e.g., D 1 =2.5 μm, W 1 =6 μm).

The distance D 2 may be measured from the right side of the via 121 (or via 122 ) to the right side of the pad 120 along the width (e.g., the width W 1 or W 2 ). The distance D 2 along the width may be measured from the boundary of the via 121 (or via 122 ) to the boundary of the pad 120 on the same side (e.g., the right side). When the via 121 (or via 122 ) is located at the center of the pad 120 along the width, the distance between the left side of the via 121 (or via 122 ) and the left side of the pad 120 may be substantially identical to the distance D 2 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the distance D 2 may be from 0.9 μm (e.g., W 1 =3.5 μm, W 2 =1.7 μm) to 2.5 μm (e.g., W 1 =6 μm, W 2 =1 μm). In some embodiments, the ratio of D 2 to W 2 may be from 0.52 (e.g., D 2 =0.9 μm, W 2 =1.7 μm) to 2.5 (e.g., D 2 =2.5 μm, W 2 =1 μm). In some embodiments, the ratio of D 2 to W 1 may be from 0.25 (e.g., D 2 =0.9 μm, W 1 =3.5 μm) to 0.42 (e.g., D 2 =2.5 μm, W 2 =6 μm).

In some embodiments, when D 1 /W 2 and/or D 2 /W 2 is from 0.52 to 2.5, passivation cracking between the pads 110 and 120 may be effectively avoided. In some embodiments, the D 1 /W 1 and/or D 2 /W 1 is from 0.25 to 0.42, passivation cracking between the pads 110 and 120 may be effectively avoided. The reasons why passivation cracking between the two pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

FIG. 1 B is a cross-section of the semiconductor device 100 of FIG. 1 A along line AA′, in accordance with some embodiments of the present disclosure. In FIG. 1 B , the x-axis may be horizontal, the z-axis may be vertical, and the y-axis may be orthogonal to the plane of the figure.

In FIG. 1 B , the via 112 may be formed at a level lower than that of pad 110 . The via 122 may be formed at a level lower than that of pad 120 . In some embodiments, the pad 110 and via 112 may be formed in a single process (e.g., a deposition process). The pad 120 and via 122 may be formed in a single process (e.g., a deposition process).

FIG. 1 B further shows the metal contacts 113 and 123 . The metal contact 113 may be formed at a level lower than those of the via 112 and the pad 110 . The metal contact 123 may be formed at a level lower than those of the via 122 and the pad 120 . The pad 110 may be connected to the metal contact 113 through the via 112 . The pad 110 may be connected to the metal contact 113 through the vias 111 and 112 . The pad 120 may be connected to the metal contact 123 through the via 122 . The pad 120 may be connected to the metal contact 123 through the vias 121 and 122 . The metal contacts 113 and 123 may comprise copper, aluminum, aluminum copper, tungsten, nickel, the like, or a combination thereof. The metal contacts 113 and 123 may be ultra-thick metal (UTM) contacts. For example, UTM contacts may be formed at a thickness of about 3 times the thickness a typical top metal or about 10 times the thickness of the other metal layers Mn through M 1 . The metal contacts 113 and 123 may be a part of a top metal layer in a semiconductor device.

In some embodiments, a passivation layer (e.g., passivation layer 518 ) may be disposed between the pads 110 and 120 and the metal contacts 113 and 123 ; the passivation layer (e.g., passivation layer 518 ) may surround the vias 111 , 112 , 121 , and 122 . In some embodiments, a passivation layer (e.g., passivation layer 520 ) may cover and surround the pads 110 and 120 .

In FIG. 1 B , the pads 110 and 120 may be spaced apart by the spacing S 1 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 1 may not exceed 5 μm.

In FIG. 1 B , the distance D 1 may be measured from the left side of the via 112 to the left side of the pad 110 along the width (e.g., the direction of the width W 1 or W 2 ). The distance D 2 may be measured from the right side of the via 112 to the right side of the pad 110 along the width. The distance D 1 may be measured from the boundary of the via 112 to the boundary of the pad 110 on the left side. The distance D 2 may be measured from the boundary of the via 112 to the boundary of the pad 110 on the right side.

In FIG. 1 B , the distance D 2 may be measured from the right side of the via 122 to the right side of the pad 120 along the width (e.g., the direction of the width W 1 or W 2 ). The distance D 1 may be measured from the left side of the via 122 to the left side of the pad 120 along the width (e.g., W 1 or W 2 ). The distance D 2 may be measured from the boundary of the via 122 to the boundary of the pad 120 on the right side. The distance D 1 may be measured from the boundary of the via 122 to the boundary of the pad 120 on the left side.

In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the distance D 1 may be from 0.9 μm (e.g., W 1 =3.5 μm, W 1 =1.7 μm) to 2.5 μm (e.g., W 1 =6 μm, W 2 =1 μm). In some embodiments, the ratio of D 1 to W 2 may be from 0.52 (e.g., D 1 =0.9 μm, W 2 =1.7 μm) to 2.5 (e.g., D 1 =2.5 μm, W 2 =1 μm). In some embodiments, the ratio of D 2 to W 1 may be from 0.25 (e.g., D 2 =0.9 μm, W 1 =3.5 μm) to 0.42 (e.g., D 2 =2.5 μm, W 1 =6 μm). In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the distance D 2 may be from 0.9 μm (e.g., W 1 =3.5 μm, W 2 =1.7 μm) to 2.5 μm (e.g., W 1 =6 μm, W 2 =1 μm). In some embodiments, the ratio of D 2 to W 2 may be from 0.52 (e.g., D 2 =0.9 μm, W 2 =1.7 μm) to 2.5 (e.g., D 2 =2.5 μm, W 2 =1 μm). In some embodiments, the ratio of D 2 to W 1 may be from 0.25 (e.g., D 2 =0.9 μm, W 1 =3.5 μm) to 0.42 (e.g., D 2 =2.5 μm, W 1 =6 μm). When the via 112 is located at the center of the pad 110 along the width, D 1 and D 2 may be substantially identical. When the via 122 is located at the center of the pad 120 along the width, D 1 and D 2 may be substantially identical.

In some embodiments, the pad 110 , the via 112 , and the metal contact 113 may be substantially identical to the pad 120 , the via 122 , and the metal contact 123 , respectively.

FIG. 2 A is a diagram of a layout of a semiconductor device 200 , in accordance with some embodiments of the present disclosure. In FIG. 2 A , the x-axis may be horizontal, the y-axis may be vertical, and the z-axis may be orthogonal to the plane of the figure.

The semiconductor device 200 includes pads 110 , 120 , and 230 and vias 111 , 112 , 121 , 122 , 231 , and 232 . Compared with the semiconductor device 100 of FIG. 1 A , the semiconductor device 200 further includes the pad 230 and the vias 231 and 232 . With the pad 230 , the passivation layer on the pad 120 (i.e., the center pad) may suffer more stress and may be cracked with a high probability. The pad 230 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof. The vias 231 and 232 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof. In some embodiments, the pad 230 and vias 231 and 232 may be formed in a single process (e.g., a deposition process). The pad 230 may connect with the vias 231 and 232 . The vias 231 and 232 may be formed at a level lower than that of pad 230 .

The semiconductor device 200 may be manufactured under processes of different nanometer scale. Similar to the semiconductor device 100 , the semiconductor device 200 may be manufactured under a 28 nm process. In some embodiments, the width W 1 of the pad 230 may be from 3.5 μm to 6 μm. The widths of pads 110 , 120 , and 230 may be substantially identical. Similar to the semiconductor device 100 , the width W 2 of the via 231 may be from 1 μm to 1.7 μm; the width W 2 of the via 232 may be from 1 μm to 1.7 μm. In an embodiment, the width W 2 of the vias 231 and 232 may be 1.7 μm. The widths of the via 231 and 232 may be substantially identical. The widths of the vias 111 , 112 , 121 , 122 , 231 , and 232 may be substantially identical. In some embodiments, when the ratio of the width W 2 of the vias (e.g., 111 , 112 , 121 , 122 , 231 , and 232 ) to the width W 1 of the pads (e.g., 110 , 120 , and 230 ) is from 0.16 to 0.48, passivation cracking between two pads may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

Similar to the semiconductor device 100 , the length of the pad 230 may be from 10 μm to 2000 μm. The lengths of the pads 110 , 120 , and 230 may be substantially identical. When lengths of the pads 110 , 120 , and 230 are substantially identical and pads 110 , 120 , and 230 parallel, the parallel run length (PRL) of the pads 110 , 120 , and 230 may be from 10 μm to 2000 μm.

Similar to the semiconductor device 100 , the length of the via 231 may be from 5 μm to 30 μm and the length of the via 232 may be from 5 μm to 30 μm. In an embodiment, the lengths of the vias 231 and 232 may be 7.2 μm. The lengths of the vias 231 and 232 may be substantially identical. The lengths of the vias of 111 , 112 , 121 , 122 , 231 , and 232 may be substantially identical. In some embodiments, when the ratio of the width of the vias (e.g., 111 , 112 , 121 , 122 , 231 ) to the length of the vias (e.g., 111 , 112 , 121 , 122 , 231 ) does not exceed 0.34, passivation cracking between the two pads may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

In FIG. 2 A , the pads 110 and 120 may be spaced apart by the spacing S 1 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 1 may not exceed 5 μm. The pads 120 and 230 may be spaced apart by the spacing S 2 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 2 may not exceed 5 μm.

The pads 110 and 120 may be spaced apart by the spacing S 1 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 1 may not exceed 5 μm. The pads 120 and 230 may be spaced apart by the spacing S 1 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 1 may not exceed 5 μm.

FIG. 2 B is a cross-section of the semiconductor device 200 of FIG. 2 A along line BB′, in accordance with some embodiments of the present disclosure. In FIG. 2 B , the x-axis may be horizontal, the z-axis may be vertical, and the y-axis may be orthogonal to the plane of the figure.

Similar to the semiconductor device 100 , the metal contact 233 may be formed at a level lower than those of the via 232 and the pad 230 . The pad 230 may be connected to the metal contact 233 through the via 232 . The metal contact 233 may comprise copper, aluminum, aluminum copper, tungsten, nickel, the like, or a combination thereof. The metal contacts 113 , 123 , and 233 may be ultra-thick metal contacts. The metal contacts 113 , 123 , and 233 may be a part of a top metal layer in a semiconductor device.

In FIG. 2 B , the pads 110 and 120 may be spaced apart by the spacing S 1 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 1 may not exceed 5 μm. The pads 120 and 230 may be spaced apart by the spacing S 2 . In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacing S 2 may not exceed 5 μm.

Similar to the semiconductor device 100 , the distance D 1 may be measured from the left side of the via 232 to the left side of the pad 230 along the width (W 1 or W 2 ); the distance D 2 may be measured from the right side of the via 232 to the right side of the pad 230 along the width (W 1 or W 2 ). In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), these two distances may be from 0.9 μm (e.g., width W 1 of the pad 230 =3.5 μm, width W 2 of the via 232 =1.7 μm) to 2.5 μm (e.g., width W 1 of the pad 230 , 6 μm, width W 2 of the via 232 , 1 μm). In some embodiments, the ratio of one of these two distances (D 1 or D 2 ) to the width W 2 of the via 232 may be from 0.52 (e.g., distance D 1 or D 2 =0.9 μm, width W 2 of the via 232 =1.7 μm) to 2.5 (e.g., distance D 1 or D 2 =2.5 μm, width W 2 of the via 232 , 1 μm), and passivation cracking between any two of the pads 110 , 120 , and 230 may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

In some embodiments, the ratio of one of these two distances (D 1 or D 2 ) to the width W 1 of the pad 230 may be from 0.25 (e.g., distance D 1 or D 2 =0.9 μm, width W 1 of the pad 230 =3.5 μm) to 0.42 (e.g., distance D 1 or D 2 =2.5 μm, width W 1 of the pad 230 , 6 μm), and passivation cracking between any two of the pads 110 , 120 , and 230 may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads. When the via 232 is located at the center of the pad 230 along the width, these two distances may be substantially identical.

FIG. 3 is a cross-section of a semiconductor device 500 , in accordance with some embodiments of the present disclosure. The cross-section of the semiconductor device 500 shown in FIG. 3 may be observed along a line similar to the line BB′ of semiconductor device 200 of FIG. 2 A .

A portion of semiconductor device 500 includes a substrate 510 with an interconnect structure 511 , metal contacts 522 A, 522 B, and 522 C, a passivation layer 518 , vias 524 A, 524 B, and 524 C, and pads 526 A, 526 B, and 526 C, and a passivation layer 520 . In this embodiment, the substrate 510 may be silicon. In other embodiments, the substrate 510 may include silicon germanium (SiGe), silicon oxide, nitride, the like, or a combination thereof. The substrate 510 may include integrated circuits comprising active devices and passive devices.

The interconnect structure 511 comprises metal lines 514 and vias 516 to electrically connect the various active devices and/or passive devices to form functional circuitry or an integrated circuit. Conductive materials, such as copper, aluminum, or the like, with or without a barrier layer, can be used as the metal lines 514 and the vias 516 . The metal lines 514 and the vias 516 may be formed using a single and/or dual damascene process, via-first process, or metal-first process. Interconnect structure 511 may include a plurality of metal layers, namely M 1 , Mn, . . . , and Mtop. The metal layer M 1 may be the metal layer immediately above the substrate 510 . The metal layer Mn may be an intermediate layer above metal layer M 1 . The metal layer Mtop may be the top metal layer immediately under the vias 524 A, 524 B, and 524 C and pads 526 A, 526 B, and 526 C. Throughout the description, the term “metal layer” may refer to the collection of the metal lines in the same layer. Metal layers M 1 through Mn through Mtop may be formed in inter-metal dielectrics (IMDs) (or passivation layers) 512 , which may be formed of oxides such as silicon oxide, borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), low-k dielectric materials, the like, or a combination thereof. The low-k dielectric materials may have k values lower than 3.9.

The metal layer Mtop may comprise one or more contacts, such as metal contacts 522 A, 522 B, and 522 C. The metal contacts 522 A, 522 B, and 522 C may be formed over and in electrical contact with the metal layers Mn of the interconnect structure 511 . The metal contacts 522 A, 522 B, and 522 C may comprise copper, aluminum, aluminum copper, tungsten, nickel, the like, or a combination thereof. In some embodiments, the metal lines 514 and metal contacts 522 A, 522 B, and 522 C may be formed at a thickness from about 0.3 μm to about 1.2 μm. In other embodiments, the metal layer Mtop and metal contacts 522 A, 522 B, and 522 C may be a top metal or an ultra-thick metal (UTM). An UTM may be formed at a thickness of about 3 times the thickness a typical top metal or about 10 times the thickness of the other metal layers Mn through M 1 . It is understood, however, that the dimensions recited throughout the description are merely examples, and may be changed in alternative embodiments.

The passivation layer 518 may be formed over the interconnect structure 511 and the metal contacts 522 A, 522 B, and 522 C. In an embodiment, the passivation layer 518 may be formed at a thickness between about 0.7 μm and about 1 μm. After the passivation layer 518 has been formed, one or more openings (e.g., the openings for the vias 524 A, 524 B, and 524 C) may be formed through the passivation layer 518 by removing portions of the passivation layer 518 to expose at least a portion of the underlying metal contacts 522 A, 522 B, and 522 C. The via 524 A may allow contact between the metal contact 522 A and the pad 526 A. The via 524 B may allow contact between the metal contact 522 B and the pad 526 B. The via 524 C may allow contact between the metal contact 522 C and the pad 526 C. The passivation layer 518 may surround the vias 524 A, 524 B, and 524 C. The vias 524 A, 524 B, and 524 C may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the metal contacts 522 A, 522 B, and 522 C may be used.

After the vias 524 A, 524 B, and 524 C have been formed, the pads 526 A, 526 B, and 526 C may be formed to extend along the passivation layer 518 and may be in electrical connection with the metal contacts 522 A, 522 B, and 522 C. The pads 526 A, 526 B, and 526 C may be utilized to provide electrical connection between the metal contacts 522 A, 522 B, and 522 C and the metal features in layers above the pads 526 A, 526 B, and 526 C. In an embodiment, the pads 526 A, 526 B, and 526 C may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof and may be formed to have a substantial height H 11 (or a substantial thickness) between about 1.4 μm and about 2.8 μm. In one embodiment, the substantial height H 11 of the pads 526 A, 526 B, and 526 C may be 2.5 μm. In some embodiments, the via 524 A and the pad 526 A may be formed in a single process (e.g., a deposition process). The via 524 B and the pad 526 B may be formed in a single process (e.g., a deposition process). The via 524 C and the pad 526 C may be formed in a single process (e.g., a deposition process). In some embodiments, one or more barrier layers (not shown) may be formed at the bottom of the vias 524 A, 524 B, and 524 C comprising titanium, titanium nitride, tantalum, tantalum nitride, the like, or a combination thereof.

The pads 526 A and 526 B may be spaced apart by a spacing. The pads 526 B and 526 C may be spaced apart by a spacing. The spacings between pads 526 A and 526 B and between 526 B and 526 C may be substantially identical. In some embodiments (e.g., semiconductor devices manufactured under a 28 nm process), the spacings between pads 526 A and 526 B and between pads 526 B and 526 C may not exceed 5 μm.

After the formation of the pads 526 A, 526 B, and 526 C, the passivation layer 520 may be formed. In an embodiment, the passivation layer 520 may be conformal with substantially the same thickness across the semiconductor device 500 . The passivation layer 520 may comprise high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxide (e.g., SiOx), silicon nitride (e.g., SiN), the like, or a combination thereof. In an embodiment, the passivation layer 520 may be formed to have a thickness between about 2.9 μm and about 3.5 μm. The passivation layer 520 may surround and/or cover the pads 526 A, 526 B, and 526 C.

In some embodiments, because pad 526 A and via 524 A may be formed in a single process, a recess 528 A may be formed on the top of the pad 526 A. Because pad 526 B and via 524 B may be formed in a single process, a recess 528 B may be formed on the top of the pad 526 B. Because pad 526 C and via 524 C may be formed in a single process, a recess 528 C may be formed on the top of the pad 526 C.

In FIG. 3 , the x-axis may be horizontal, the z-axis may be vertical, and the y-axis may be orthogonal to the plane of the figure. The widths or the radii of the recesses 528 A, 528 B, and 528 C (along the x-axis) may be associated with the widths or the radii (along the x-axis) of the vias 524 A, 524 B, and 524 C, respectively. When the widths or the radii of the vias 524 A, 524 B, and 524 C (along the x-axis) increase, the widths or the radii of the recesses 528 A, 528 B, and 528 C (along the x-axis) may increase correspondingly. When the widths or the radii of the vias 524 A, 524 B, and 524 C (along the x-axis) decrease, the widths or radii of the recesses 528 A, 528 B, and 528 C (along the x-axis) may decrease correspondingly.

The depths (along the z-axis) of the recesses 528 A, 528 B, and 528 C may be associated with the widths or the radii of the vias 524 A, 524 B, and 524 C (along the x-axis), respectively. When the widths or the radii of the vias 524 A, 524 B, and 524 C increase (along the x-axis), the depths of the recesses 528 A, 528 B, and 528 C (along the z-axis) may increase correspondingly.

The depths (along the z-axis) of the recesses 528 A, 528 B, and 528 C may be associated with the lengths of the vias 524 A, 524 B, and 524 C (along the y-axis), respectively. When the lengths of the vias 524 A, 524 B, and 524 C increase (along the y-axis), the depths of the recesses 528 A, 528 B, and 528 C (along the y-axis) may increase correspondingly.

The passivation layer 520 may be conformal with the pads 526 A, 526 B, and 526 C and the passivation layer 518 . Recesses 530 A, 530 B, and 530 C on the passivation layer 520 may be formed corresponding to the recesses 528 A, 528 B, and 528 C, respectively.

The widths or radii of the recesses 530 A, 530 B, and 530 C (along the x-axis) may be associated with the widths or radii of the recesses 528 A, 528 B, and 528 C (along the x-axis), respectively. The widths or the radii of the recesses 530 A, 530 B, and 530 C (along the x-axis) may be associated with the widths or the radii (along the x-axis) of the vias 524 A, 524 B, and 524 C, respectively. When the widths or the radii of the vias 524 A, 524 B, and 524 C (along the x-axis) increase, the widths or the radii of the recesses 530 A, 530 B, and 530 C (along the x-axis) may increase correspondingly. When the widths or the radii of the vias 524 A, 524 B, and 524 C (along the x-axis) decrease, the widths or the radii of the recesses 530 A, 530 B, and 530 C (along the x-axis) may decrease correspondingly.

Voids (or seams, cavities) 532 A and 532 B may be formed within the passivation layer 520 . Because the passivation layer 520 may be grown from a partial surface of the passivation layer 518 , the sidewalls of the pads 526 A to 526 C, and the top surfaces of the pads 526 A to 526 C, the voids 532 A and 532 B may thus be formed with the passivation layer 520 . The passivation layer 520 may be substantially continuous since no obvious trenches are formed between the pads 526 A, 526 B and 526 C.

The void 532 A may be formed between the pads 526 A and 526 B. The void 532 A may be separated from the pads 526 A and 526 B by the same distances. The void 532 A may be formed at the central point of the line connected the pads 526 A and 526 B. The void 532 B may be formed between the pads 526 B and 526 C. The void 532 B may be separated from the pads 526 B and 526 C by the same distances. The void 532 B may be formed at the central point of the line connected the pads 526 A and 526 B.

Each of voids 532 A and 532 B may be shaped as fusiform when observed in the cross-section shown in FIG. 3 . The voids 532 A and 532 B may be formed to have a width (e.g., along the x-direction) between about 0.13 μm and about 0.15 μm. The voids 532 A and 532 B may be formed to have a length (e.g., along the z-direction) between about 1.9 μm and about 2.07 μm.

The passivation layer 520 may include a layer of dielectric material 520 A, a layer of dielectric material 520 B, and a layer of dielectric material 520 C. The dielectric material 520 A may include undoped silicate glass (USG). The dielectric material 520 B may include high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition). The dielectric material 520 C may include silicon nitride (e.g., SiN).

The layer of dielectric material 520 A may be formed to have a thickness TH 11 about 0.2 μm. A part of the layer of dielectric material 520 A on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 11 about 0.2 μm. The layer of dielectric material 520 B may be formed to have a thickness TH 12 about 1.3 μm. A part of the layer of dielectric material 520 B on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 12 about 1.3 μm. The layer of dielectric material 520 C may be formed to have a thickness TH 13 between about 1.4 μm and about 2 μm. A part of the layer of dielectric material 520 C on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 13 between about 1.4 μm and about 2 μm. In some embodiments, the thickness TH 13 may exceed 2 μm. The passivation layer 520 may be formed to have a thickness between about 2.9 μm and about 3.5 μm. A part of the passivation layer 520 on the pad 526 A, 526 B, or 526 C may be formed to have a thickness between about 2.9 μm and about 3.5 μm. In some embodiments, the thickness of the passivation layer 520 may exceed 3.5 μm. The voids 532 A and 532 B may be formed within the passivation layer 520 . The voids 532 A and 532 B may be formed within the layer of dielectric material 520 C.

When the passivation layer 520 is formed to have a thickness between about 2.9 μm and about 3.5 μm or a thickness exceeding 3.5 μm, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 . When the layer of dielectric material 520 C is formed to have a thickness TH 13 between about 1.4 μm and about 2 μm or a thickness TH 13 exceeding 2 μm, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 . When a ratio of the thickness TH 13 to the thickness TH 11 exceeds 7, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 .

When the passivation layer 520 is sufficiently thick to have voids (e.g., 532 A and 532 B) between pads (e.g., 526 A to 526 C), passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 . When the layer of dielectric material 520 C is sufficiently thick to have voids (e.g., 532 A and 532 B) between pads (e.g., 526 A to 526 C), passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 .

In some embodiments, when the ratio of the width of the vias 524 A, 524 B, and 524 C (along the x-axis) to the length of the vias 524 A, 524 B, and 524 C (along the y-axis) does not exceed 0.34, the recesses 528 A, 528 B, and 528 C may be narrow or elongated, and the thickness of the passivation layer 520 may be more uniform. Thus, passivation cracking (e.g., between the pads 526 A and 526 B or between the pads 526 B and 526 C) may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

In some embodiments, when the ratio of the width (along the x-axis) of the vias (e.g., vias 524 A, 524 B, and 524 C) to the width (along the x-axis) of the pads (e.g., pads 526 A, 526 B, and 526 C) is from 0.16 to 0.48, passivation cracking (e.g., at the trench 532 A or 532 B) may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

Similar to the semiconductor device 100 , the distance may be measured from the left side of a via (e.g., one of the vias 524 A, 524 B, and 524 C) to the left side of the corresponding pad along the width; another distance may be measured from the right side of the via to the right side of the corresponding pad along the width. In some embodiments, when the ratio of one of these two distances to the width of the via is from 0.52 to 2.5, passivation cracking (e.g., at the trench 532 A or 532 B) may be effectively avoided. In some embodiments, the ratio of one of these two distances to the width of the corresponding pad is from 0.25 to 0.42, passivation cracking (e.g., between the pads 526 A and 526 B or between the pads 526 B and 526 C) may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

FIG. 4 is a cross-section of the semiconductor device 500 , in accordance with some embodiments of the present disclosure. The cross-section of the semiconductor device 500 shown in FIG. 4 may be observed along a line similar to the line CC′ of semiconductor device 200 of FIG. 2 A . No vias may appear in the cross-section of FIG. 4 .

Compared with FIG. 3 , the cross-section of FIG. 4 may not include the vias 524 A, 524 B, and 524 C, the recesses 528 A, 528 B, and 528 C, and the recesses 530 A, 530 B, and 530 C. Because the cross-section of FIG. 4 does not include the vias 524 A, 524 B, and 524 C, the recesses 528 A, 528 B, and 528 C and the recesses 530 A, 530 B, and 530 C may not be formed correspondingly.

Similar to the cross-section of FIG. 3 , the pads 526 A, 526 B, and 526 C shown in the cross-section of FIG. 4 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof and may be formed to have a substantial height H 11 (or a substantial thickness) between about 1.4 μm and about 2.8 μm. In one embodiment, the substantial height H 11 of the pads 526 A, 526 B, and 526 C may be 2.5 μm (e.g., semiconductor devices manufactured under a 28 nm process).

Similar to the cross-section of FIG. 3 , the passivation layer 520 may include a layer of dielectric material 520 A, a layer of dielectric material 520 B, and a layer of dielectric material 520 C. The dielectric material 520 A may include undoped silicate glass (USG). The dielectric material 520 B may include high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition). The dielectric material 520 C may include silicon nitride (e.g., SiN).

The semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the layer of dielectric material 520 A may be formed to have a thickness TH 11 about 0.2 μm. A part of the layer of dielectric material 520 A on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 11 about 0.2 μm. The layer of dielectric material 520 B may be formed to have a thickness TH 12 about 1.3 μm. A part of the layer of dielectric material 520 B on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 12 about 1.3 μm. The layer of dielectric material 520 C may be formed to have a thickness TH 13 between about 1.4 μm and about 2 μm. A part of the layer of dielectric material 520 C on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 13 between about 1.4 μm and about 2 μm. In some embodiments, the thickness TH 13 may exceed 2 μm. The passivation layer 520 may be formed to have a thickness between about 2.9 μm and about 3.5 μm. A part of the passivation layer 520 on the pad 526 A, 526 B, or 526 C may be formed to have a thickness between about 2.9 μm and about 3.5 μm. In some embodiments, the thickness of the passivation layer 520 may exceed 3.5 μm.

The voids 532 A and 532 B may be formed within the passivation layer 520 . Because the passivation layer 520 may be grown from a partial surface of the passivation layer 518 , the sidewalls of the pads 526 A to 526 C, and the top surfaces of the pads 526 A to 526 C, the voids 532 A and 532 B may thus be formed with the passivation layer 520 . The passivation layer 520 may be substantially continuous since no obvious trenches are formed between the pads 526 A, 526 B and 526 C.

The voids 532 A and 532 B may be formed within the layer of dielectric material 520 C. Because the layer of dielectric material 520 C may be grown from the top surfaces and sidewalls of the layer of dielectric material 520 B, the voids 532 A and 532 B may thus be formed with the layer of dielectric material 520 C. The layer of dielectric material 520 C may be substantially continuous since no obvious trenches are formed between the pads 526 A, 526 B and 526 C.

The void 532 A may be formed between the pads 526 A and 526 B. The void 532 A may be separated from the pads 532 A and 532 B by the same distances. The void 532 A may be formed at the central point of the line connected the pads 526 A and 526 B. The void 532 B may be formed between the pads 526 B and 526 C. The void 532 B may be separated from the pads 532 B and 532 C by the same distances. The void 532 B may be formed at the central point of the line connected the pads 526 A and 526 B.

Each of voids 532 A and 532 B may be shaped as fusiform when observed in the cross-section of FIG. 4 . The voids 532 A and 532 B may be formed to have a width (e.g., along the x-direction) between about 0.13 μm and about 0.15 μm. The voids 532 A and 532 B may be formed to have a length between about 1.9 μm and about 2.07 μm (e.g., along the z-direction).

When the passivation layer 520 is formed to have a thickness between about 2.9 μm and about 3.5 μm or a thickness exceeding 3.5 μm, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 . When the layer of dielectric material 520 C is formed to have a thickness TH 13 between about 1.4 μm and about 2 μm or a thickness TH 13 exceeding 2 μm, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 . When a ratio of the thickness TH 13 to the thickness TH 11 exceeds 7, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 .

When the passivation layer 520 is sufficiently thick to have voids (e.g., 532 A and 532 B) between pads (e.g., 526 A to 526 C), passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 . When the layer of dielectric material 520 C is sufficiently thick to have voids (e.g., 532 A and 532 B) between pads (e.g., 526 A to 526 C), passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided because the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer 520 .

Table 1 shows the probability of passivation cracking in different cases. In the cases shown, the passivation layer (e.g., the passivation layer 520 ) may be formed to have a normal thickness. For example, the passivation layer of the cases in Table 1 may be formed to have a thickness about 2.5 μm (e.g., semiconductor devices manufactured under a 28 nm process). In some embodiments, the passivation layer of the cases in Table 1 may be formed to include a SiN layer having a thickness about 1 μm (e.g., semiconductor devices manufactured under a 28 nm process). The leftmost column shows the different widths of the vias, e.g., the widths of the vias 111 , 112 , 121 , and 122 or the widths of the vias 524 A, 524 B, and 524 C). The second column shows different parallel run lengths, e.g., the lengths of pads 110 and 120 or the lengths the pads 526 A, 526 B, and 526 C. The first row shows different spacings between pads e.g., the spacing of pads 110 and 120 or the spacing of pads 526 A, 526 B, and 526 C. The third to fifth columns show the probability of passivation cracking under different conditions. In general, when the parallel run length increases, the probability increases. When the spacing between pads decreases, the probability may increase. When the width of the vias between pads decreases, the probability may decrease. In some embodiments, even though the width of the vias decreases, the length of the vias may increase to keep the area the same and keep conductivity unchanged.

Table 2 shows the probability of passivation cracking in other cases. With respect to the cases shown in Table 1, the passivation layer (e.g., the passivation layer 520 ) of the cases shown in Table 2 may be formed to be thicker. For example, the passivation layer of the cases in Table 2 may be formed have a thickness about 3.5 μm (e.g., semiconductor devices manufactured under a 28 nm process). In some embodiments, a portion of the passivation layer of the cases in Table 2 may be formed to include a SiN layer having a thickness about 2 μm (e.g., semiconductor devices manufactured under a 28 nm process), such as the layer of dielectric material 520 C. Compared with Table 1, under the same width of the vias, same PRL, and same spacing between pads, the probabilities of passivation cracking shown in Table 2 are much lower than those shown in Table 1. Thus, increasing the thickness of the passivation layer (e.g., the passivation layer 520 ) and/or the thickness of the layer of dielectric material 520 C can decrease the probability of passivation cracking.

Table 3 shows the probability of passivation cracking in different cases. In the cases shown in Table 3, different spacing between two pads (e.g., 526 A to 526 C) and different thickness of the layer of dielectric material 520 C are discussed. The dielectric material 520 C may include SiN. The first column shows different spacings between two pads. The second column shows the probabilities of passivation cracking with the layer of dielectric material 520 C having a thickness of 1 μm under different spacings between two pads. The third column shows the probabilities of passivation cracking with the layer of dielectric material 520 C having a thickness of 1.4 μm under different spacings between two pads. The fourth column shows the probabilities of passivation cracking with the layer of dielectric material 520 C having a thickness of 1.6 μm under different spacings between two pads. The fifth column shows the probabilities of passivation cracking with the layer of dielectric material 520 C having a thickness of 1.8 μm under different spacings between two pads. The sixth column shows the probabilities of passivation cracking with the layer of dielectric material 520 C having a thickness of 2 μm under different spacings between two pads. In the cases shown in Table 3, other dielectric materials included in the passivation layer (e.g., dielectric material 520 A and 520 B) may keep the same thickness. The passivation layer (e.g., the passivation layer 520 ) may be formed to have a thickness between about 2.5 μm and about 3.5 μm (e.g., semiconductor devices manufactured under a 28 nm process). The thickness of the layer of dielectric material 520 C may be measured for the part on the pad 526 A, 526 B, or 526 C. The thickness of the passivation layer (e.g., the passivation layer 520 ) may be measured for the part on the pad 526 A, 526 B, or 526 C.

In general, when the spacing decreases, the probability of passivation cracking increases. When the thickness of the layer of dielectric material 520 C increases, the probability of passivation cracking may decrease. When the thickness of the passivation layer (e.g., the passivation layer 520 ) increases, the probability of passivation cracking may decrease. When the spacing between two pads is narrower, the layer of dielectric material 520 C (or the passivation layer 520 ) may be thicker so as to be free of passivation cracking.

FIGS. 5 to 9 illustrate various stages of manufacturing the semiconductor device 500 , in accordance with some embodiments of the present disclosure.

FIG. 5 illustrates a substrate 510 and metal layers M 1 through Mtop at an intermediate stage of processing. The substrate 510 may be silicon, SiGe, silicon carbide, the like, or a combination thereof. The substrate 510 may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

The substrate 510 may include integrated circuits comprising active and passive devices (not shown). As one of ordinary skill in the art could recognize, a wide variety of active and passive devices such as transistors, capacitors, resistors, combinations of these, or the like may be used to generate the structural and functional requirements of the design for the semiconductor device 500 . The integrated circuits comprising active and passive devices may be formed using any suitable methods.

As shown in FIG. 5 , the IMDs 512 and metal lines 514 and vias 516 may be formed over the substrate 510 . In an embodiment, the metal lines 514 and vias 516 may be coupled to the integrated circuits on the substrate 510 to allow other devices to be coupled to the integrated circuits. Each of the IMDs 512 can be silicon oxide, BPSG, PSG, FSG, the like, or a combination thereof, formed by chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), furnace deposition, plasma-enhanced CVD (PECVD), the like, or a combination thereof. The metal lines 514 and vias 516 in each of the IMDs 512 may be formed using, for example, a damascene process like a dual damascene and may comprise aluminum, or copper aluminum alloys, the like, or a combination thereof. The metal lines 514 and the vias 516 may be deposited using, for example, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), the like, or a combination thereof. A polishing and/or grinding process, such as chemical mechanical polishing (CMP), may remove excess conductive materials. The IMDs 512 may be sequentially formed, along with the respective vias 516 and metal lines 514 .

The metal contacts 522 A, 522 B, and 522 C may be formed over the metal lines 514 and vias 516 . The metal contacts 522 A, 522 B, and 522 C may comprise copper, aluminum, aluminum copper, tungsten, nickel, the like, or a combination thereof and may be formed by a similar process as the metal lines 514 as described. In another embodiment, the metal contacts 522 A, 522 B, and 522 C may be formed and patterned before the formation of the top IMD 512 . The metal contacts 522 A, 522 B, and 522 C may be a top metal or an UTM. An UTM may be formed at a thickness of about 3 times the thickness of a typical top metal or about 10 times the thickness of the other metal layers Mn and M 1 . In another embodiment, the metal contacts 522 A, 522 B, and 522 C may be a similar thickness to the other metal layers Mn through M 1 . It should be noted that many other components may be included in an embodiment that are not expressly depicted. For example, etch stop layers can be disposed between the various interfaces between layers of the substrate 510 and IMDs 512 . Further, more or fewer IMDs 512 and metal layers may be used.

In FIG. 6 , the formation of the passivation layer 518 is illustrated. The passivation layer 518 may be formed over the metal contacts 522 A, 522 B, and 522 C and the top IMD 512 . The passivation layer 518 can be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, the like, or a combination thereof, and deposited by CVD or the like.

FIG. 7 illustrates the formation of openings 534 A, 534 B, and 534 C on the passivation layer 518 . The openings 534 A, 534 B, and 534 C may be formed through the passivation layer 518 by removing portions of the passivation layer 518 to expose at least a portion of the underlying metal contacts 522 A, 522 B, and 522 C. The vias 524 A, 524 B, and 524 C may allow contact to the metal contacts 522 A, 522 B, and 522 C, respectively. The openings 534 A, 534 B, and 534 C may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the metal contacts 522 A, 522 B, and 522 C may be used.

In FIG. 8 , openings 536 A, 536 B, and 536 C for the pads 526 A, 526 B, and 526 C may be formed in a photoresist layer 538 . The photoresist layer 538 may be removed over the vias 524 A, 524 B, and 524 C and the pads 526 A, 526 B, and 526 C are formed.

In some embodiments, one or more barrier layers (not shown) may be formed at the bottom of the openings 534 A, 534 B, and 534 C comprising titanium, titanium nitride, tantalum, tantalum nitride, the like, or a combination thereof. The one or more barrier layers may be formed along the passivation layer 518 and at the bottom of the openings 534 A, 534 B, and 534 C by CVD, PVD, PECVD, ALD, the like, or a combination thereof. In an embodiment, the photoresist layer 538 may cover a seed layer (not shown) of a titanium copper alloy on one or more barrier layers, if present, through CVD, sputtering, the like, or a combination thereof.

In FIG. 9 , the formation of the vias 524 A, 524 B, and 524 C and the pads 526 A, 526 B, and 526 C is illustrated. The vias 524 A and pad 526 A may be formed in the openings 534 A and 536 A in a single process (e.g., a deposition process). The vias 524 B and pad 526 B may be formed in the openings 534 B and 536 B in a single process (e.g., a deposition process). The vias 524 C and pad 526 C may be formed in the openings 534 C and 536 C in a single process (e.g., a deposition process). After the vias 524 A, 524 B, and 524 C and the pads 526 A, 526 B, and 526 C are formed, the photoresist layer 538 may be removed.

In an embodiment, the vias 524 A, 524 B, and 524 C and the pads 526 A, 526 B, and 526 C may be formed by forming a seed layer (not shown) of a titanium copper alloy on the one or more barrier layers, if present, through CVD, sputtering, the like, or a combination thereof. The photoresist layer 538 may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the pads 526 A, 526 B, and 526 C are to be located. Once the photoresist layer 538 has been formed and patterned, a conductive material, such as copper, aluminum, aluminum copper, gold, the like or a combination thereof may be formed on the seed layer through deposition such as plating, CVD, PVD, the like, or a combination thereof. Once the conductive material has been formed, the photoresist layer 538 may be removed through a suitable removal process such as ashing. Additionally, after the removal of the photoresist, those portions of the seed layer that were covered by the photoresist may be removed through, for example, a suitable etching process using the conductive material as a mask.

FIG. 9 illustrates the removal of the photoresist layer 538 after the formation of the vias 524 A, 524 B, and 524 C and the pads 526 A, 526 B, and 526 C.

In some embodiments, a ratio of the width of the via 524 A to the length of the via 524 A may not exceed 0.34. A ratio of the width of the via 524 B to the length of the via 524 B may not exceed 0.34. A ratio of the width of the via 524 C to the length of the via 524 C may not exceed 0.34.

In some embodiments, a ratio of the width of the via 524 A to the width of the pad 526 A may be between 0.16 and 0.48. A ratio of the width of the via 524 B to the width of the pad 526 B may be between 0.16 and 0.48. A ratio of the width of the via 524 C to the width of the pad 526 C may be between 0.16 and 0.48.

In some embodiments, along the width of the pad 526 A, a first distance may be measured between the boundary of the pad 526 A and the boundary of the via 524 A on the same side (e.g., on the right side or on the left side). A ratio of the first distance to the width of the via 524 A may be between 0.52 and 2.5. A second distance may be measured between the boundary of the pad 526 B and the boundary of the via 524 B on the same side (e.g., on the right side or on the left side). A ratio of the second distance to the width of the via 524 B may be between 0.52 and 2.5. A third distance may be measured between the boundary of the pad 526 C and the boundary of the via 524 C on the same side (e.g., on the right side or on the left side). A ratio of the third distance to the width of the via 524 C may be between 0.52 and 2.5.

After the removal of the photoresist layer 538 , the passivation layer 520 may be formed on the pads 526 A, 526 B, and 526 C and the passivation layer 518 . The passivation layer 520 may comprise high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxide (e.g., SiOx), silicon nitride (e.g., SiN), the like, or a combination thereof. The passivation layer 520 may be conformally deposited, by CVD or the like, over the pads 526 A, 526 B, and 526 C and the passivation layer 518 to have the substantially same thickness across the semiconductor device 500 . After the passivation layer 520 is formed, the semiconductor device 500 as shown in FIG. 3 may be formed.

FIG. 10 is a flowchart illustrating a method 1000 for manufacturing the semiconductor device 500 in accordance with some embodiments of the present disclosure.

In operation 1001 , the interconnect structure 511 may be formed on the substrate 510 . The interconnect structure 511 comprises metal lines 514 and vias 516 to electrically connect the various active devices and/or passive devices to form functional circuitry or an integrated circuit.

In operation 1003 , the metal contacts 522 A, 522 B, and 522 C may be formed over the substrate 510 . The metal contacts 522 A, 522 B, and 522 C may be formed over and in electrical contact with the interconnect structure 511 .

In operation 1005 , the passivation 518 may be formed over the metal contacts 522 A, 522 B, and 522 C. The passivation layer 518 may be formed over the interconnect structure 511 and the metal contacts 522 A, 522 B, and 522 C.

In operation 1007 , the openings 534 A, 534 B, and 534 C may be formed on the passivation layer 518 . The openings 534 A, 534 B, and 534 C may be formed through the passivation layer 518 by removing portions of the passivation layer 518 to expose at least a portion of the underlying metal contacts 522 A, 522 B, and 522 C.

In operation 1009 , the vias 524 A, 524 B, and 524 C may be formed within the openings 534 A, 534 B, and 534 C, respectively. The via 524 A may allow contact between the metal contact 522 A and the pad 526 A. The via 524 B may allow contact between the metal contact 522 B and the pad 526 B. The via 524 C may allow contact between the metal contact 522 C and the pad 526 C, wherein a ratio of the width of the vias 524 A, 524 B, and 524 C to the length of the vias 524 A, 524 B, and 524 C does not exceed 0.34.

In operation 1011 , the pads 526 A, 526 B, and 526 C may be formed in parallel. The pad 526 A may connect to the metal contact 522 A through the via 524 A. The pad 526 B may connect to the metal contact 522 B through the via 524 B. The pad 526 B may connect to the metal contact 522 B through the via 524 B. The via 524 A and the pad 526 A may be formed in a single process (e.g., a deposition process). The via 524 B and the pad 526 B may be formed in a single process (e.g., a deposition process). The via 524 C and the pad 526 C may be formed in a single process (e.g., a deposition process).

After the formation of the pads 526 A, 526 B, and 526 C, the passivation layer 520 may be formed in operation 1013 . The passivation layer 520 may surround and cover the pads 526 A, 526 B, and 526 C. The passivation layer 520 may be substantially continuous since no obvious trenches are formed between the pads 526 A, 526 B and 526 C.

The passivation layer 520 may include a layer of dielectric material 520 A, a layer of dielectric material 520 B, and a layer of dielectric material 520 C. The dielectric material 520 A may include undoped silicate glass (USG). The dielectric material 520 B may include high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition). The dielectric material 520 C may include silicon nitride (e.g., SiN). The layer of dielectric material 520 C may be substantially continuous since no obvious trenches are formed between the pads 526 A, 526 B and 526 C.

The layer of dielectric material 520 A may be formed to have a thickness TH 11 about 0.2 μm. A part of the layer of dielectric material 520 A on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 11 about 0.2 μm. The layer of dielectric material 520 B may be formed to have a thickness TH 12 about 1.3 μm. A part of the layer of dielectric material 520 B on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 12 about 1.3 μm. The layer of dielectric material 520 C may be formed to have a thickness TH 13 between about 1.4 μm and about 2 μm. A part of the layer of dielectric material 520 C on the pad 526 A, 526 B, or 526 C may be formed to have a thickness TH 13 between about 1.4 μm and about 2 μm. In some embodiments, the thickness TH 13 may exceed 2 μm. The passivation layer 520 may be formed to have a thickness between about 2.9 μm and about 3.5 μm. A part of the passivation layer 520 on the pad 526 A, 526 B, or 526 C may be formed to have a thickness between about 2.9 μm and about 3.5 μm. In some embodiments, the thickness of the passivation layer 520 may exceed 3.5 μm.

The voids 532 A and 532 B may be formed within the passivation layer 520 . The voids 532 A and 532 B may be formed within the layer of dielectric material 520 C. The void 532 A may be formed between the pads 526 A and 526 B. The void 532 A may be separated from the pads 532 A and 532 B by the same distances. The void 532 A may be formed at the central point of the line connected the pads 526 A and 526 B. The void 532 B may be formed between the pads 526 B and 526 C. The void 532 B may be separated from the pads 532 B and 532 C by the same distances. The void 532 B may be formed at the central point of the line connected the pads 526 A and 526 B.

When the passivation layer 520 is formed to have a thickness between about 2.9 μm and about 3.5 μm or a thickness exceeding 3.5 μm, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided. When the layer of dielectric material 520 C is formed to have a thickness TH 13 between about 1.4 μm and about 2 μm or a thickness TH 13 exceeding 2 μm, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided. When a ratio of the thickness TH 13 to the thickness TH 11 exceeds 7, passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

When the passivation layer 520 is sufficiently thick to have voids (e.g., 532 A and 532 B) between pads (e.g., 526 A to 526 C), passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided. When the layer of dielectric material 520 C is sufficiently thick to have voids (e.g., 532 A and 532 B) between pads (e.g., 526 A to 526 C), passivation cracking (e.g., between pads 526 A and 526 B or between pads 526 B and 526 C) may be effectively avoided. The reasons why passivation cracking between the pads is effectively avoided include that the stress (e.g., due to changes of temperature) can be distributed or released by the thick, wide, and/or continuous passivation layer on the pads.

In some embodiments, a ratio of the width of the via 524 A to the length of the via 524 A may not exceed 0.34. A ratio of the width of the via 524 B to the length of the via 524 B may not exceed 0.34. A ratio of the width of the via 524 C to the length of the via 524 C may not exceed 0.34.

In some embodiments, a ratio of the width of the via 524 A to the width of the pad 526 A may be between 0.16 and 0.48. A ratio of the width of the via 524 B to the width of the pad 526 B may be between 0.16 and 0.48. A ratio of the width of the via 524 C to the width of the pad 526 C may be between 0.16 and 0.48.

In some embodiments, along the width of the pad 526 A, a first distance may be measured between the boundary of the pad 526 A and the boundary of the via 524 A on the same side (e.g., on the right side or on the left side). A ratio of the first distance to the width of the via 524 A may be between 0.52 and 2.5. A second distance may be measured between the boundary of the pad 526 B and the boundary of the via 524 B on the same side (e.g., on the right side or on the left side). A ratio of the second distance to the width of the via 524 B may be between 0.52 and 2.5. A third distance may be measured between the boundary of the pad 526 C and the boundary of the via 524 C on the same side (e.g., on the right side or on the left side). A ratio of the third distance to the width of the via 524 C may be between 0.52 and 2.5.

FIG. 11 is a cross-section of the semiconductor device 1100 , in accordance with some embodiments of the present disclosure. The cross-section of the semiconductor device 1100 shown in FIG. 11 may be observed along a line similar to the line CC′ of semiconductor device 200 of FIG. 2 A . No vias may appear in the cross-section of FIG. 11 .

The semiconductor device 1100 may be similar to the semiconductor device 500 shown in FIG. 4 . The semiconductor device 1100 may include pads 1126 A and 1126 B, passivation layer 1120 , and void 1132 A.

The pads 1126 A and 1126 B shown in the cross-section of FIG. 11 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof and may be formed to have a substantial height H 21 between about 1.4 μm and about 2.8 μm. In one embodiment, the substantial height H 21 of the pads 1126 A and 1126 B may be 2.5 μm (e.g., semiconductor devices manufactured under a 28 nm process).

The passivation layer 1120 may include a layer of dielectric material 1120 A, a layer of dielectric material 1120 B, and a layer of dielectric material 1120 C. The dielectric material 1120 A may include undoped silicate glass (USG). The dielectric material 1120 B may include high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition). The dielectric material 1120 C may include silicon nitride (e.g., SiN).

The semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the layer of dielectric material 1120 A may be formed to have a thickness TH 21 about 0.2 μm. A part of the layer of dielectric material 1120 A on the pad 1126 A or 1126 B may be formed to have a thickness TH 21 about 0.2 μm. The layer of dielectric material 1120 B may be formed to have a thickness TH 22 about 1.3 μm. A part of the layer of dielectric material 1120 B on the pad 1126 A or 1126 B may be formed to have a thickness TH 22 about 1.3 μm. The layer of dielectric material 1120 C may be formed to have a thickness TH 23 of about 1.4 μm. A part of the layer of dielectric material 1120 C on the pad 1126 A or 1126 B may be formed to have a thickness TH 23 of about 1.4 μm. The passivation layer 1120 may be formed to have a thickness of about 2.9 μm. A part of the passivation layer 1120 on the pad 1126 A or 1126 B may be formed to have a thickness of about 2.9 μm.

The passivation layer 1120 may be substantially continuous since no obvious trenches are formed between the pads 1126 A and 1126 B. The layer of dielectric material 1120 C may be substantially continuous since no obvious trenches are formed between the pads 1126 A and 1126 B. The profile of the top surface of the passivation layer 1120 may be formed to have a top point and a bottom point. The height H 22 from the bottom point to the top point may be about 1.49 μm.

The void 1132 A may be formed within the passivation layer 1120 . The void 1132 A may be formed within the layer of dielectric material 1120 C. The void 1132 A may be formed between the pads 1126 A and 1126 B. The void 1132 A may be separated from the pads 1132 A and 1132 B by the same distances. The void 1132 A may be formed at the central point of the line connected the pads 1126 A and 1126 B. The void 1132 A may be shaped as fusiform. The semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the void 1132 A may be formed to have a length L 3 about 2.07 μm and a width D 1 about 0.15 μm.

FIG. 12 is a cross-section of the semiconductor device 1200 , in accordance with some embodiments of the present disclosure. The cross-section of the semiconductor device 1200 shown in FIG. 12 may be observed along a line similar to the line CC′ of semiconductor device 200 of FIG. 2 A . No vias may appear in the cross-section of FIG. 12 .

The semiconductor device 1200 may be similar to the semiconductor device 1100 shown in FIG. 11 . The semiconductor device 1200 may include pads 1226 A and 1226 B, passivation layer 1220 , and void 1232 A.

The pads 1226 A and 1226 B shown in the cross-section of FIG. 12 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof and may be formed to have a substantial height H 31 between about 1.4 μm and about 2.8 μm. In one embodiment, the substantial height H 31 of the pads 1226 A and 1226 B may be 2.5 μm (e.g., semiconductor devices manufactured under a 28 nm process).

The passivation layer 1220 may include a layer of dielectric material 1220 A, a layer of dielectric material 1220 B, and a layer of dielectric material 1220 C. The dielectric material 1220 A may include undoped silicate glass (USG). The dielectric material 1220 B may include high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition). The dielectric material 1220 C may include silicon nitride (e.g., SiN).

The semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the layer of dielectric material 1220 A may be formed to have a thickness TH 31 about 0.2 μm. A part of the layer of dielectric material 1220 A on the pad 1226 A or 1226 B may be formed to have a thickness TH 31 about 0.2 μm. The layer of dielectric material 1220 B may be formed to have a thickness TH 32 about 1.3 μm. A part of the layer of dielectric material 1220 B on the pad 1226 A or 1226 B may be formed to have a thickness TH 32 about 1.3 μm. The layer of dielectric material 1220 C may be formed to have a thickness TH 33 of about 1.6 μm. A part of the layer of dielectric material 1220 C on the pad 1226 A or 1226 B may be formed to have a thickness TH 33 of about 1.6 μm. The passivation layer 1220 may be formed to have a thickness of about 3.1 μm. A part of the passivation layer 1220 on the pad 1226 A or 1226 B may be formed to have a thickness of about 3.1 μm.

The passivation layer 1220 may be substantially continuous since no obvious trenches are formed between the pads 1226 A and 1226 B. The layer of dielectric material 1220 C may be substantially continuous since no obvious trenches are formed between the pads 1226 A and 1226 B. The profile of the top surface of the passivation layer 1220 may be formed to have a top point and a bottom point. The height H 32 from the bottom point to the top point may be about 1.30 μm.

The void 1232 A may be formed within the passivation layer 1220 . The void 1232 A may be formed within the layer of dielectric material 1220 C. The void 1232 A may be formed between the pads 1226 A and 1226 B. The void 1232 A may be separated from the pads 1232 A and 1232 B by the same distances. The void 1232 A may be formed at the central point of the line connected the pads 1226 A and 1226 B. The void 1232 A may be shaped as fusiform. For semiconductor devices manufactured under a 28 nm process, the void 1232 A may be formed to have a length L 4 about 2.05 μm and a width D 2 about 0.14 μm. In some embodiments, the semiconductor devices may be manufactured under processes of different nanometer scale.

FIG. 13 is a cross-section of the semiconductor device 1300 , in accordance with some embodiments of the present disclosure. The cross-section of the semiconductor device 1300 shown in FIG. 13 may be observed along a line similar to the line CC′ of semiconductor device 200 of FIG. 2 A . No vias may appear in the cross-section of FIG. 13 .

The semiconductor device 1300 may be similar to the semiconductor device 1100 shown in FIG. 11 . The semiconductor device 1300 may include pads 1326 A and 1326 B, passivation layer 1320 , and void 1332 A.

The pads 1326 A and 1326 B shown in the cross-section of FIG. 13 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof and may be formed to have a substantial height H 41 between about 1.4 μm and about 2.8 μm. In one embodiment, the substantial height H 41 of the pads 1326 A and 1326 B may be 2.5 μm (e.g., semiconductor devices manufactured under a 28 nm process).

The passivation layer 1320 may include a layer of dielectric material 1320 A, a layer of dielectric material 1320 B, and a layer of dielectric material 1320 C. The dielectric material 1320 A may include undoped silicate glass (USG). The dielectric material 1320 B may include high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition). The dielectric material 1320 C may include silicon nitride (e.g., SiN).

In some embodiments, the semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the layer of dielectric material 1320 A may be formed to have a thickness TH 41 about 0.2 μm. A part of the layer of dielectric material 1320 A on the pad 1326 A or 1326 B may be formed to have a thickness TH 41 about 0.2 μm. The layer of dielectric material 1320 B may be formed to have a thickness TH 42 about 1.3 μm. A part of the layer of dielectric material 1320 B on the pad 1326 A or 1326 B may be formed to have a thickness TH 42 about 1.3 μm. The layer of dielectric material 1320 C may be formed to have a thickness TH 43 of about 1.8 μm. A part of the layer of dielectric material 1320 C on the pad 1326 A or 1326 B may be formed to have a thickness TH 43 of about 1.8 μm. The passivation layer 1320 may be formed to have a thickness of about 3.3 μm. A part of the passivation layer 1320 on the pad 1326 A or 1326 B may be formed to have a thickness of about 3.3 μm.

The passivation layer 1320 may be substantially continuous since no obvious trenches are formed between the pads 1326 A and 1326 B. The layer of dielectric material 1320 C may be substantially continuous since no obvious trenches are formed between the pads 1326 A and 1326 B. The profile of the top surface of the passivation layer 1320 may be formed to have a top point and a bottom point. The height H 42 from the bottom point to the top point may be about 1.10 μm.

The void 1332 A may be formed within the passivation layer 1320 . The void 1332 A may be formed within the layer of dielectric material 1320 C. The void 1332 A may be formed between the pads 1326 A and 1326 B. The void 1332 A may be separated from the pads 1332 A and 1332 B by the same distances. The void 1332 A may be formed at the central point of the line connected the pads 1326 A and 1326 B. The void 1332 A may be shaped as fusiform. The semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the void 1332 A may be formed to have a length L 5 about 2.04 μm and a width D 3 about 0.13 μm.

FIG. 14 is a cross-section of the semiconductor device 1400 , in accordance with some embodiments of the present disclosure. The cross-section of the semiconductor device 1400 shown in FIG. 14 may be observed along a line similar to the line CC′ of semiconductor device 200 of FIG. 2 A . No vias may appear in the cross-section of FIG. 14 .

The semiconductor device 1400 may be similar to the semiconductor device 1100 shown in FIG. 11 . The semiconductor device 1400 may include pads 1426 A and 1426 B, passivation layer 1420 , and void 1432 A.

The pads 1426 A and 1426 B shown in the cross-section of FIG. 14 may comprise aluminum, copper, an aluminum copper alloy, the like, or a combination thereof and may be formed to have a substantial height H 51 between about 1.4 μm and about 2.8 μm. In one embodiment, the substantial height H 51 of the pads 1426 A and 1426 B may be 2.5 μm (e.g., semiconductor devices manufactured under a 28 nm process).

The passivation layer 1420 may include a layer of dielectric material 1420 A, a layer of dielectric material 1420 B, and a layer of dielectric material 1420 C. The dielectric material 1420 A may include undoped silicate glass (USG). The dielectric material 1420 B may include high density plasma (HDP) oxide (e.g., a layer of oxide formed by a HDP chemical vapor deposition). The dielectric material 1420 C may include silicon nitride (e.g., SiN).

The semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the layer of dielectric material 1420 A may be formed to have a thickness TH 51 about 0.2 μm. A part of the layer of dielectric material 1420 A on the pad 1426 A or 1426 B may be formed to have a thickness TH 51 about 0.2 μm. The layer of dielectric material 1420 B may be formed to have a thickness TH 52 about 1.3 μm. A part of the layer of dielectric material 1420 B on the pad 1426 A or 1426 B may be formed to have a thickness TH 52 about 1.3 μm. The layer of dielectric material 1420 C may be formed to have a thickness TH 53 of about 2 μm. A part of the layer of dielectric material 1420 C on the pad 1426 A or 1426 B may be formed to have a thickness TH 53 of about 2 μm. The passivation layer 1420 may be formed to have a thickness of about 3.5 μm. A part of the passivation layer 1420 on the pad 1426 A or 1426 B may be formed to have a thickness of about 3.5 μm.

The passivation layer 1420 may be substantially continuous since no obvious trenches are formed between the pads 1426 A and 1426 B. The layer of dielectric material 1420 C may be substantially continuous since no obvious trenches are formed between the pads 1426 A and 1426 B. The profile of the top surface of the passivation layer 1420 may be formed to have a top point and a bottom point. The height H 52 from the bottom point to the top point may be about 0.96 μm.

The void 1432 A may be formed within the passivation layer 1420 . The void 1432 A may be formed within the layer of dielectric material 1420 C. The void 1432 A may be formed between the pads 1426 A and 1426 B. The void 1432 A may be separated from the pads 1432 A and 1432 B by the same distances. The void 1432 A may be formed at the central point of the line connected the pads 1426 A and 1426 B. The void 1432 A may be shaped as fusiform. The semiconductor devices of the present disclosure may be manufactured under processes of different nanometer scale. For semiconductor devices manufactured under a 28 nm process, the void 1432 A may be formed to have a length L 6 about 1.9 μm and a width D 4 about 0.13 μm.

From FIGS. 11 to 14 , it may be observed that the height H 22 exceeds the height H 32 , the height H 32 exceeds the height H 42 , and the height H 42 exceeds H 52 . When the passivation layer (e.g., the passivation layer 1120 , 1220 , 1320 , or 1420 ) is thicker, the height from the bottom point to the top point of the top surface of the passivation layer may be smaller.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device may include a substrate, a first pad, a second pad, a first passivation layer, and a void. The first pad may be over the substrate. The second pad may be over the substrate. The second pad may be parallel to the first pad. The first passivation layer may surround the first pad and the second pad. The void may be within the first passivation layer.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device may include a substrate, a first via, a first pad, a second pad, and a first passivation layer. The first pad may be over the substrate. The second pad may be over the substrate. The second pad may be parallel to the first pad. The first passivation layer may surround the first pad and the second pad. The first passivation layer may include a first part on the first pad. The first passivation layer may include a second part on the second pad. A thickness of the first part of the first passivation layer may exceed a height of the first pad. A thickness of the second part of the first passivation layer may exceed a height of the second pad.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method may include: forming an integrated circuit on a substrate; forming a first metal contact and a second metal contact over the substrate; forming a first passivation layer over the first metal contact and the second metal contact; forming a first opening and a second opening on the first passivation layer; forming a first via within the first opening and a second via within the second opening; forming a first pad and a second pad parallel to the first pad, the first pad connecting to the first metal contact through the first via, the second pad connecting to the second metal contact through the second via; and forming a second passivation layer surrounding the first pad and the second pad. The second passivation layer may include a void between the first pad and the second pad.

A semiconductor device may include a substrate, a first pad over the substrate, a second pad over the substrate, the second pad parallel to the first pad, a first passivation layer surrounding the first pad and the second pad, and a void within the first passivation layer. The first passivation layer may include a first dielectric material, a second dielectric material, and a third dielectric material. The first dielectric material may be on the first pad, the second dielectric material may be on the first dielectric material, the third dielectric material may be on the second dielectric material, and a first ratio of a thickness of the third dielectric material to a thickness of the first dielectric material may exceed 7.

The third dielectric material may include silicon nitride. The first dielectric material may include undoped silicate glass. The second dielectric material may include high density plasma (HDP) oxide. The thickness of the third dielectric material may exceed 1.4 μm.

The void may be between the first pad and the second pad, and the void may be separated from the first pad and the second pad by the same distance.

The semiconductor device may further comprise a first via under the first pad and connecting the first pad. A second ratio of a width of the first via to the width of the first pad may be between 0.16 to 0.48. A third ratio of the width of the first via to a length of the first via may not exceed 0.34.

A semiconductor device may include a substrate, a first pad over the substrate, a second pad over the substrate, where the second pad is parallel to the first pad, and a first passivation layer surrounding the first pad and the second pad. The first passivation layer may include a first part on the first pad and a second part on the second pad. A thickness of the first part of the first passivation layer may exceed a height of the first pad, and a thickness of the second part of the first passivation layer may exceed a height of the second pad.

The first passivation layer may include a first dielectric material, a second dielectric material, and a third dielectric material. The first dielectric material may be on the first pad, the second dielectric material may be on the first dielectric material, and the third dielectric material may be on the second dielectric material. A first ratio of a thickness of the third dielectric material to a thickness of the first dielectric material may exceed 7. The third dielectric material may include silicon nitride. The thickness of the third dielectric material may exceed 1.4 μm.

The semiconductor device may further comprise a void within the first passivation layer and between the first pad and the second pad.

The semiconductor device may further comprise a first via under the first pad and connecting the first pad. A second ratio of a width of the first via to the width of the first pad may be between 0.16 to 0.48. A third ratio of the width of the first via to a length of the first via may not exceed 0.34.

A method of manufacturing a semiconductor device may include forming an integrated circuit on a substrate, forming a first metal contact and a second metal contact over the substrate, forming a first passivation layer over the first metal contact and the second metal contact, forming a first opening and a second opening on the first passivation layer, forming a first via within the first opening and a second via within the second opening, forming a first pad and a second pad parallel to the first pad, and forming a second passivation layer surrounding the first pad and the second pad. The first pad may be connected to the first metal contact through the first via, the second pad may be connected to the second metal contact through the second via, and the second passivation layer may include a void between the first pad and the second pad.

The first passivation layer may include a first dielectric material, a second dielectric material, and a third dielectric material. The first dielectric material may be on the first pad. The second dielectric material may be on the first dielectric material. The third dielectric material may be on the second dielectric material. A ratio of a thickness of the third dielectric material to a thickness of the first dielectric material may exceed 7. The third dielectric material may include silicon nitride. The thickness of the third dielectric material may exceed 1.4 μm. A first ratio of the width of the first and second vias to the length of the first and second vias may not exceed 0.34.

The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.