Oscillator circuit and semiconductor integrated circuit

The present application is based on, and claims priority from, Japan Application Serial Number 2020-074621, filed on Apr. 20, 2020, the disclosure of which is hereby incorporated by reference herein in its entirety.

The present invention relates to an oscillator circuit, and more particularly, to an oscillator circuit using a constant current circuit.

A variety of technologies or applications of constant current circuits have been described in conventional technologies. For example, Japanese Application JP2005234890A discloses using a current mirror circuit for the constant current circuit. Japanese Application JP2013097751A discloses a constant current circuit outputting a constant current without dependency on the supply voltage. In addition, Japanese Application JP2017069825A discloses an oscillator circuit that uses a constant current circuit (implemented by a V/I converting circuit).

FIG. 1 shows a conventional constant current circuit 10 including an operational amplifier OP, PMOS transistors PMOS 1 and PMOS 2 and a variable resistor R T . The node N is located between the PMOS transistor PMOS 1 and the variable resistor R T . The inverting input terminal (−) of the operational amplifier OP receives the reference voltage V REF , and the non-inverting input terminal (+) of the operational amplifier OP receives the voltage V N at the node N. The transistor PMOS 1 and the variable resistor R T are connected in series between the supply voltage VDD and the ground potential GND, and the gate of the transistor PMOS 1 is connected to the output of the operational amplifier OP. The variable resistor R T is configured to fine-tune its resistance value according to such as the tolerance of the circuit element. The operational amplifier OP controls the gate voltage of the transistor PMOS 1 , so that the voltage V N at the node N is equal to the reference voltage V REF (V N =V REF ). In other words, the operational amplifier OP operates as the unity gain buffer. Therefore, the reference current flowing through the transistor PMOS 1 is represented by I REF =V REF /R T , and the reference current I REF becomes the constant current without dependency on the change of the supply voltage. In addition, the output of the operational amplifier OP can be connected to the gate of the transistor PMOS 2 , which forms a current mirror circuit with the transistor PMOS 1 . This way, the transistor PMOS 2 can generate an output current I MIRROR in accordance with the current I REF flowing through the transistor PMOS 1 , and the output current I MIRROR can be provided to the load.

FIG. 2 shows an example of an oscillator circuit using the constant current circuit 10 shown in FIG. 1 . The oscillator circuit 20 comprises a pair of delay circuits 22 and 24 and a flip-flop circuit 26 . The transistor PMOS 2 of the constant current circuit 10 (shown in FIG. 3A ) provides the output current I MIRROR to first input terminals of the delay circuits 22 and 24 . The output OUT 1 of the delay circuit 22 is connected to the input S of the flip-flop circuit 26 , and the output OUT 2 of the delay circuit 24 is connected to the input R of the flip-flop circuit 26 . The output Q of the flip-flop circuit 26 is connected to the second input terminal of the delay circuit 22 and the output Q of the flip-flop circuit 26 is connected to the second input terminal of the delay circuit 24 , and the clock signal CLK is generated at the output Q. The output Q is inverted from the output Q.

FIG. 3B is the operation waveform of the voltage at the input IN of the delay circuit 22 in accordance with time. FIG. 3C is the operation waveform of the voltage at the node N 3 of the delay circuit 22 in accordance with time. FIG. 3D is the operation waveform of the voltage at the output OUT 1 of the delay circuit 22 in accordance with time. As shown in FIG. 3A , the delay circuit 22 comprises an N-type transistor NMOS 1 , a capacitor C and a comparator CMP. The transistor PMOS 2 of the constant current circuit 10 and the transistor NMOS 1 of the delay circuit 22 are connected in series between the supply voltage VDD and the ground potential GND. The output current I MIRROR generated by the transistor PMOS 2 of the constant current circuit 10 is provided to the node N 3 located between the transistor PMOS 2 and the transistor NMOS 1 . The capacitor C and the comparator CMP are connected to the node N 3 . In detail, the inverting input terminal (−) of the comparator CMP receives the reference voltage V REF , and the non-inverting input terminal (+) of the comparator CMP receives the voltage at the node N 3 . The comparator CMP is configured to compare the voltage at the node N 3 with the reference voltage V REF , when the voltage at the node N 3 is lower than or equal to the reference voltage V REF , the comparator CMP outputs the L level; when the voltage at the node N 3 is higher than the reference voltage V REF , the comparator CMP outputs the H level. The output OUT 1 of the comparator CMP is connected to the input S of the flip-flop circuit 26 ; the output Q of the flip-flop circuit 26 is applied to the gate of the transistor NMOS 1 as the input IN. The configuration of the delay circuit 24 is the same as that of the delay circuit 22 .

In detail, during the period from time t 1 to t 4 , the output Q of the flip-flop circuit 26 is at the L level (i.e. the input IN is at the L level). Accordingly, the transistor NMOS 1 is turned off, the capacitor C is connected to the supply voltage VDD via the transistor PMOS 2 . That is, the capacitor C is charged during the period from time t 1 to t 4 .

Before the time t 1 , the input IN is at the H level, thereby making the transistor NMOS 1 turn on, thus the voltage of the node N 3 is discharged to the ground potential GND via the turned-on transistor NMOS 1 . At this time, the current flowing through the transistor PMOS 2 driving by the output voltage Vg of the operational amplifier OP is smaller than the current which can flow through the transistor NMOS 1 , thus the potential at the node N 3 becomes almost equal to the ground potential GND, and the capacitor C is not charged. At the time t 1 , when the transistor NMOS 1 is turned off, the charge will flow from the supply voltage VDD through the transistor PMOS 2 , and the capacitor C is charged. The charging speed depends on the output current I MIRROR flowing through the transistor PMOS 2 .

When the capacitor C is charged and the voltage at the node N 3 becomes higher than the reference voltage V REF , the output OUT 1 of the comparator CMP becomes the H level. After that, since the flip-flop circuit 26 receives the output OUT 1 at the H level from the comparator CMP, at the time t 4 , the output Q (i.e. the input IN) of the flip-flop circuit 26 starts to change to the H level, and the transistor NMOS 1 is turned on, the capacitor C starts to discharge. When the voltage at the node N 3 becomes lower than the reference voltage V REF , the output OUT 1 of the comparator CMP becomes L level. In addition, from the time t 4 , since the output Q of the flip-flop circuit 26 starts to change to the L level, the input IN of the delay circuit 24 starts to change to the L level, such that the capacitor C of the delay circuit 24 starts to be charged. This way, a clock signal CLK is generated from the output Q of the flip-flop circuit 26 through the oscillation generated by the delay circuits 22 and 24 , which are connected together via the flip-flop circuit 26 .

In the constant current circuit 10 , if the supply voltage VDD drops very close to the reference voltage V REF , the transistor PMOS 1 as the output driver of the operational amplifier OP will become unable to operate in the saturation region, making the output voltage Vg of the operational amplifier OP become very low. Therefore, the transistor PMOS 2 also becomes unable to keep operating in the saturation region, and it may generate an output current I MIRROR that is not related to the current mirror ratio, and significantly larger than the reference current I REF of the transistor PMOS 1 .

The output current I MIRROR_L (dashed line) in FIG. 3C shows the non-ideal case when the output current I MIRROR is significantly larger than the reference current I REF . If the output current is increased from I MIRROR_S to I MIRROR_L , the charging time of the capacitor C will be shorter accordingly. Therefore, as shown in FIG. 3D , in the ideal case (i.e. in the embodiment that the output current I MIRROR_S is equal to the reference current I REF ), the output OUT 1 of the comparator CMP becomes the H level at the time t 3 . In contrast, in the non-ideal case (i.e. in the embodiment that the output current I MIRROR_L is significantly larger than the reference current I REF ), the output OUT 1 of the comparator CMP becomes the H level at the time t 2 earlier than the time t 3 . In other words, comparing to the ideal case, in such the non-ideal case, the delay time caused by the charging of the capacitor C becomes shorter, and the oscillation frequency of the generated clock signal CLK becomes higher. If the frequency of the clock signal CLK generated by the oscillator circuit 20 becomes too high, the operation of the circuit which needs to be synchronized with the clock signal CLK cannot be guaranteed.

The purpose of the present invention is to solve the conventional problems described above, and to provide an oscillator circuit which can suppress the upper limit of the frequency of the clock signal.

The oscillator circuit according to the present invention comprises: a constant current circuit, configured to generate a first output current according to a supply voltage; a current limiting circuit, configured to receive the first output current and generate a second output current, and establish an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit; and an oscillator, configured to generate a clock signal according to the second output current.

According to the present invention, since the abnormal current is limited when the supply voltage drops below the lower limit of the guaranteed operational range of the constant current circuit, the frequency of the clock signal can be prevented from being higher than the required value.

FIG. 1 shows the configuration of the conventional constant current circuit.

FIG. 2 shows the configuration of the oscillator circuit using the conventional constant current circuit.

FIG. 3A shows the configuration of the delay circuit of the oscillator; FIGS. 3B-3D show the operation waveforms of the voltages at each node of the delay circuit.

FIG. 4 shows the configuration of an oscillator circuit according to a first embodiment of the present invention.

FIG. 5 shows the configuration of the oscillator circuit according to a second embodiment of the present invention.

FIG. 6 shows the configuration of the delay circuit of the second embodiment according to the present invention.

Next, embodiments of the present invention will be described in detail with reference to the drawings. The oscillator circuit of the present invention can be applied to memory devices such as the dynamic random access memory (DRAM), the static random access memory (SRAM), the resistive random access memory (RRAM), and the magnetic random access memory (MRAM); or can be applied to various semiconductor devices such as the logic and the signal processing.

FIG. 4 shows the configuration of the oscillator circuit of the present embodiment. The same configuration as in FIG. 2 and FIG. 3A is given the same reference number, and the repeated description is omitted.

The oscillator circuit 100 of the present embodiment comprises the constant current circuit 10 , a current limiting circuit 110 and the oscillator circuit 20 . The current limiting circuit 110 is configured between the constant current circuit 10 and the oscillator circuit 20 . Only the delay circuit 22 is shown in the oscillator circuit 20 as the representative, and the other elements of the oscillator circuit 20 , such as the delay circuit 24 and the flip-flop circuit 26 are omitted. In one embodiment, the delay circuits 22 and 24 can be commonly connected to one current limiting circuit 110 . In another embodiment, the oscillator circuit 100 can comprise two transistors PMOS 2 and two current limiting circuits 110 . The delay circuit 22 is connected to one of the transistors PMOS 2 and one of the current limiting circuits 110 connected in series, and the delay circuit 24 is connected to the other transistor PMOS 2 and the other current limiting circuit 110 connected in series.

The current limiting circuit 110 of the present embodiment is configured to establish the upper limit for the frequency of the clock signal CLK generated by the oscillator circuit 20 when the abnormally large constant current flows through the constant current circuit 10 . For example, if the supply voltage VDD provided to the constant current circuit 10 drops from the determined supply voltage VDD (for example, 1.8V) very close to the reference voltage V REF (for example, 1.2V generated by the bandgap reference circuit), the output voltage Vg of the operational amplifier OP will become too low, and the transistors PMOS 1 and PMOS 2 as output drivers will not operate in the saturation region (for example, operate in the linear region). This way, the current mirror circuit formed by the transistors PMOS 1 and PMOS 2 cannot operate normally, and the output current I MIRROR of the transistor PMOS 2 does not follow the current mirror ratio, and may become very large.

As shown in FIG. 3A , each of the delay circuits 22 and 24 of the oscillator circuit 20 comprises a capacitor C. The charging time of the capacitor C depends on the output current I MIRROR . If the output current I MIRROR becomes larger, the charging speed becomes faster, the delay time caused by the delay circuits 22 and 24 becomes shorter, and the frequency of the clock signal CLK becomes higher.

The current limiting circuit 110 of the present embodiment is configured to regulate the upper limit of the output current I MIRROR of the constant current circuit 10 when the supply voltage VDD drops. It also prevents the charging time of the capacitor C of the delay circuit 22 from being too short, which can result in the delay time being shorter than a first predetermined value. Therefore, the frequency of the clock signal CLK is not higher than a second predetermined value. This way, the operation of the circuit synchronized with the clock signal CLK from the oscillator circuit 100 can be guaranteed.

As shown in FIG. 4 , the current limiting circuit 110 of the present embodiment comprises P-type transistors PMOS 4 and PMOS 5 and a resistor R LIM . The transistor PMOS 5 is connected in series between the constant current circuit 10 and the oscillator circuit 20 . In the present embodiment, the transistor PMOS 5 is connected between the transistor PMOS 2 and the transistor NMOS 1 . The current limiting circuit 110 comprises a current I LIM flowing path located between the supply voltage VDD and the ground potential GND, and the transistor PMOS 4 and the resistor R LIM are connected in series in the current I LIM flowing path. The gates of the transistors PMOS 4 and PMOS 5 are commonly connected to the node N 4 located between the transistor PMOS 4 and the resistor R LIM . The transistors PMOS 4 and PMOS 5 form a current mirror circuit. According to the present embodiment, the bias of the gate of the transistor PMOS 5 is determined by the current I LIM flowing through the transistor PMOS 4 and the resistor R LIM . Therefore, the current flowing through the transistor PMOS 5 is determined by the current I LIM . If the supply voltage VDD becomes higher, the current I LIM becomes larger; if the supply voltage VDD becomes lower, the current I LIM becomes smaller. In addition, if the resistance value of the resistor R LIM is adjusted to be smaller, the current I LIM becomes larger; if the resistance value of the resistor R LIM is adjusted to be larger, the current I LIM becomes smaller.

If the supply voltage VDD is significantly higher than the reference voltage V REF , that is, the supply voltage VDD satisfies the lower limit of the guaranteed operational range of the constant current circuit 10 , the transistor PMOS 1 operates in the saturation region, the transistor PMOS 2 follows the current mirror ratio to generate the output current I MIRROR in accordance with the reference current I REF flowing through the transistor PMOS 1 . If the supply voltage VDD drops very close to the reference voltage V REF , or even drops below the reference voltage V REF due to some reasons, the transistor PMOS 1 operates in the linear region, and the transistor PMOS 2 no longer operates as the current mirror of the reference current I REF , resulting in a higher output current I MIRROR larger than the reference current I REF . By the current limiting circuit 110 of the embodiment, the current provided to the capacitor C can be limited to solve the above-mentioned problem.

The resistor R LIM is a variable resistor. When the supply voltage VDD is lower than the lower limit of the guaranteed operational range of the constant current circuit 10 , the current I LIM is adjusted to make sure that the charging time of the capacitor C caused by the drain current flowing through the transistor PMOS 5 is not less than a constant time. For example, when the supply voltage VDD is equal to the lower limit of the guaranteed operational range of the constant current circuit 10 , the resistor R LIM is configured to adjust the current I LIM being equal to the output current I MIRROR . In other words, the adjusted current I LIM is equal to the reference current I REF . This way, when the supply voltage VDD is normal, the reference current I REF controls the output current I MIRROR . On the other hand, when the supply voltage VDD is lower than the lower limit of the guaranteed operational range of the constant current circuit 10 , the output current I MIRROR is suppressed by the current I LIM being smaller than the reference current I REF .

By regulating the upper limit of the output current I MIRROR , as shown in FIG. 3C , the voltage shown by the dashed line can be limited to the voltage shown by the solid line, and the upper limit of the frequency of the clock signal is restricted.

During normal operation, the current I LIM of the current limiting circuit 110 is larger than the reference current I REF , so the output current I MIRROR generated by the transistor PMOS 5 is not limited.

By adjusting the resistance value of the resistor R LIM of the current limiting circuit 110 properly, when the output current I MIRROR of the constant current circuit 10 becomes larger, the current limiting circuit 110 operates as the current limiter, to establish the upper limit for the output current I MIRROR , so that the charging time of the capacitor C is not less than a constant time. When the constant current circuit 10 outputs the normal constant current, the current limiting circuit 110 provides the output current I MIRROR in accordance with the reference current I REF , and does not operate as the current limiter. This way, when an oscillator circuit uses the constant current circuit of the present embodiment, it is possible to prevent the oscillator from generating an unexpected high-frequency clock signal, and the operation of the circuit synchronized with the clock signal can be guaranteed.

FIG. 5 shows the configuration of an oscillator circuit 100 A according to a second embodiment of the present invention. FIG. 6 shows the configuration of the delay circuits 22 ′ and 24 ′ of the second embodiment. In FIG. 5 and FIG. 6 , the same configuration as in FIG. 2 , FIG. 3A and FIG. 4 is given the same reference number, and the repeated description is omitted. According to the oscillator circuit 100 A, the current limiting circuit 110 ′ is configured between the constant current circuit 10 and the oscillator circuit 20 . The current limiting circuit 110 ′ comprises the P-type transistors PMOS 4 , PMOS 5 and PMOS 7 , the resistor R LIM , and the N-type transistors NMOS 2 and NMOS 3 . The drain of the transistor PMOS 5 of the current limiting circuit 110 ′ is connected to the transistor NMOS 2 . Therefore, a first current path K 1 comprises the transistors PMOS 2 , PMOS 5 and NMOS 2 connected in series between the supply voltage VDD and the ground potential GND. A bias voltage BIAS for driving the transistor NMOS 2 can be generated at the node N 2 according to the current flowing from the drain of the transistor PMOS 5 . Similar to the previous embodiment, when the supply voltage VDD is lower than the guaranteed operational range of the constant current circuit 10 , the transistor PMOS 2 may generate the excess output current I MIRROR . The amount of excess output current I MIRROR output to the oscillator circuit 20 can be limited by the current limiting circuit 110 ′.

In addition, the transistors PMOS 7 and NMOS 3 are disposed in the second current path K 2 between the supply voltage VDD and the ground potential GND. The gate of the transistor PMOS 7 is connected to the gate of a P-type transistor PMOS 3 of the oscillator circuit 20 (shown in FIG. 6 ). That is, the transistors PMOS 7 and PMOS 3 form a current mirror circuit. The gate of the transistor NMOS 2 and the gate of the transistor NMOS 3 are commonly connected to the node N 2 , and the bias voltage BIAS is applied to the node N 2 . By the current mirror circuit formed by the transistors NMOS 2 and NMOS 3 , the output current I MIRROR flowing through the second current path K 2 is regulated by the current I LIM . In addition, the bias voltage BIASP can be generated at the node N 5 between the transistors PMOS 7 and NMOS 3 according to the output current I MIRROR flowing through the second current path K 2 , and the bias voltage BIASP is also applied to the gate of the transistor PMOS 7 and the gate of the transistor PMOS 3 shown in FIG. 6 . This way, the output current I MIRROR flowing through the second current path K 2 can regulate the output current I MIRROR flowing through the transistor PMOS 3 . In other words, the current sources of the delay circuits 22 and 24 are limited to a constant value or less.

When the supply voltage VDD becomes lower than the lower limit of the guaranteed operational range of the constant current circuit 10 , the output current I MIRROR in the first current path K 1 provided to the transistor NMOS 2 is limited by the current I LIM of the current limiting circuit 110 ′. That is, the bias voltage BIAS is less than or equal to a predetermined value in response to the current I LIM . Therefore, the drain current of the transistor NMOS 3 establishes the upper limit for the output current I MIRROR in the second current path K 2 . In response to this, the output current I MIRROR flowing through the transistor PMOS 3 of the delay circuit 22 ′ ( 24 ′) will be less than or equal to a predetermined value, so that the current provided to the node N 3 is less than or equal to the predetermined value. This way, the current provided to the capacitor C can be limited, which prevents the charging speed of the capacitor C from being too fast.

According to the present embodiment, it is possible to control the charging time of each capacitor C in a pair of the delay circuits 22 ′ and 24 ′ by one current limiting circuit 110 ′, and it is not necessary to configure each current limiting circuit 110 to the corresponding delay circuits 22 and 24 individually as the first embodiment.

In the above embodiment, the oscillator is designed to comprise a pair of delay circuits and the flip-flop circuit, and the delay circuits are connected together via the flip-flop circuit. However, other well-known structure may also be used. In detail, the current limiting circuit is applied to the oscillator which determines the frequency of the clock signal based on the amount of the current generated by the constant current circuit.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.