Method for forming a semiconductor structure

1. Field of the Invention

The present disclosure relates generally to the field of semiconductor technology. More particularly, the present disclosure relates to a method for forming semiconductor fin structures.

2. Description of the Prior Art

With the process development of semiconductor technology, the structure of semiconductor device has transitioned from 2D planar type devices to 3D fin-type devices. 3D fin-type devices provide many benefits in electrical characteristics. However, the fin structure of a 3D fin-type device is easily impacted by stress in the fabrication processes which induces fin damage, bending, cracking and/or stacking faults.

There is a need in this industry to provide a method for fabricating a 3D fin-type device in order to improve the device performance and product yield.

It is one object of the present disclosure to provide an improved method for fabricating semiconductor fin structures in order to improve the device performance and product yield.

According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 to FIG. 8 are schematic, perspective diagrams showing a method for forming a semiconductor structure in accordance with one embodiment of the invention.

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Please refer to FIG. 1 to FIG. 8 . FIG. 1 to FIG. 8 are schematic, perspective diagrams showing a method for forming a semiconductor structure in accordance with one embodiment of the invention. As shown in FIG. 1 , first, a semiconductor substrate 10 is provided. For example, the semiconductor substrate 10 may be a bulk silicon substrate, but is not limited thereto. In some embodiments, the semiconductor substrate 10 may comprise a silicon-on-insulator (SOI) substrate, an epitaxial substrate, a SiGe substrate or a SiC substrate. Multiple fins 10 extending along a first direction D 1 are formed in the semiconductor substrate 100 . The multiple fins 10 comprises a group of active fins 10 a , a pair of protection fins 10 p sandwiching about the group the active fins 10 a , and dummy fins 10 d around the pair of protection fins 10 p . The fins 10 are formed of an upper portion of the semiconductor substrate 100 and are therefore semiconductor fins. Three-dimensional (3D) finFET devices (not shown) may be formed in the active fins 10 a in the later stages.

For the sake of simplicity, only four consecutive active fins 10 a , two protection fins 10 p and two dummy fins 10 d are shown in the figures. However, it is to be understood that the number of the active fins 10 a , protection fins 10 p and dummy fins 10 d may vary according to the circuit design requirements. According to one embodiment, the fins 10 may be formed by using lithographic processes and etching processes, but is not limited thereto. For example, the fins 10 may be formed by using a self-aligned double patterning (SADP) process or any suitable patterning methods known in the art. According to one embodiment, the fins 10 may be in parallel to one another and may be arranged at a fixed pitch. According to one embodiment, trenches 11 extending along the first direction D 1 are formed between the fins 10 .

According to one embodiment, each of the multiple fins 10 may comprise a pad oxide layer 101 , a pad nitride layer 102 on the pad oxide layer 101 , and a hard mask layer 103 on the pad nitride layer 102 . According to one embodiment, the pad oxide layer 101 may comprise silicon oxide, but is not limited thereto. According to one embodiment, the pad nitride layer 102 may comprise silicon nitride, but is not limited thereto. According to one embodiment, the hard mask layer 103 may comprise silicon oxide, but is not limited thereto.

As shown in FIG. 2 , after forming the multiple fins 10 , a fin cut process is performed. The fin cut process may include lithographic processes and etching processes. For example, a photoresist pattern (not shown) is formed on the semiconductor substrate 100 to cover the active fins 10 a , a pair of protection fins 10 p sandwiching about the group the active fins 10 a and the protection fins 10 p . The dummy fins 10 d are not covered by the photoresist pattern and are exposed. The exposed dummy fins 10 d may be etched by using an anisotropic dry etching process. After removing the dummy fins 10 d , a widened trench 11 d is formed around the pair of protection fins 10 p.

As shown in FIG. 3 and FIG. 4 , after performing the fin cut process, trench isolation structures are formed within the trenches 11 between the multiple fins and within the widened trench 11 d . As shown in FIG. 3 , according to one embodiment, for example, a liner layer 120 is conformally deposited on the multiple fins 10 including the active fins 10 a and the protection fins 10 p . For example, the liner layer 120 may comprise an in-situ steam growth (ISSG) oxide layer 121 and an atomic layer deposition (ALD) oxide layer 122 . Subsequently, a trench-fill oxide layer 123 is deposited on the liner layer 120 . The trench 11 and the widened trench 11 d are filled up with the trench-fill oxide layer 123 .

As shown in FIG. 4 , after depositing the trench-fill oxide layer 123 on the liner layer 120 , a chemical mechanical polishing (CMP) process is then performed to polish the trench-fill oxide layer 123 , the liner layer 120 , and the hard mask layer 103 until the pad nitride layer 102 is exposed, thereby forming the trench isolation structures 14 . In order to improve the quality of the trench isolation structures 14 , an anneal process is then performed. During the anneal process, the protection fins 10 p protect the active fins 10 a from fin damage, bending or cracking due to stresses exerted on the fins.

As shown in FIG. 5 , after annealing the trench isolation structures 14 , a chemical oxide removal (COR) process is then performed to remove (or recess) an upper portion of the trench isolation structures 14 . The COR process is a gaseous process known in the art to selectively remove silicon oxides by reacting gaseous ammonia (“NH 3 ”) and hydrogen fluoride (“HF”) to produce NH 4 F x . The NH 3 and HF react with silicon oxide on a semiconductor wafer to form ammonium hexafluorosilicate (“(NH 4 ) 2 SiF 6 ”). After performing the COR process to remove an upper portion of the trench isolation structures, the pad nitride layer 102 is then removed from each of the active fins 10 a and the protection fins 10 p . The pad oxide layer 101 underneath the pad nitride layer 102 is exposed.

As shown in FIG. 7 , after removing the pad nitride layer 102 , a single diffusion break (SDB) process is then performed to form a SDB trench 15 in the semiconductor substrate 100 . The SDB trench 15 extends along a second direction D 2 such that the group of active fins 10 a and the pair of protection fins 10 p are cut by the SDB trench 15 . According to one embodiment, the first direction D 1 is perpendicular to the first direction D 2 . The detailed process steps of the SDB process is not described for the sake of simplicity. For example, the SDB process may involve a lithographic process and a dry etching process.

As shown in FIG. 8 , after the SDB process is completed, the pair of protection fins 10 p is removed, leaving the active fins 10 a intact. According to one embodiment, the removal of the protection fins 10 p may involves a lithographic process and a dry etching process. For example, a photoresist pattern (not shown) is formed on the semiconductor substrate 100 . The photoresist pattern has openings (not shown) extending along the first direction D 1 . The openings of the photoresist pattern are aligned with the protection fins 10 p , respectively. The protection fins 10 p are then etched away through the openings of the photoresist pattern. The remaining photoresist pattern is then stripped off. After the protection fins 10 p are removed, trenches 17 extending along the first direction D 1 are formed. The trenches 17 intersect the SDB trench 15 .

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.