Bitline settling speed enhancement

This disclosure relates generally to electronic devices, and in particular but not exclusively, relates to image sensors.

Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as medical, automobile, and other applications. The technology used to manufacture image sensors has continued to advance at a great pace. For example, the demands of higher speed and lower power consumption have encouraged the further miniaturization and integration of these devices.

The typical image sensor operates as follows. Image light from an external scene is incident on the image sensor. The image sensor includes a plurality of photosensitive elements such that each photosensitive element absorbs a portion of incident image light. Photosensitive elements included in the image sensor, such as photodiodes, each generate image charge upon absorption of the image light. The amount of image charge generated is proportional to the intensity of the image light. The generated image charge may be used to produce an image representing the external scene.

Image sensors generally have readout circuitry to readout image or pixel data from the photosensitive elements. The speed of readout from the photosensitive elements may be limited by physical parameters of the readout circuitry (e.g., settling time).

Non-limiting and non-exhaustive examples of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1A shows one example of a circuit diagram of part of an image sensor, in accordance with the teachings of the present disclosure.

FIG. 1B illustrates a timing diagram for the circuit diagram of FIG. 1A , in accordance with the teachings of the present disclosure.

FIG. 2A shows one example of a circuit diagram of part of an image sensor, in accordance with the teachings of the present disclosure.

FIG. 2B illustrates a timing diagram for the circuit diagram of FIG. 2A , in accordance with the teachings of the present disclosure.

FIG. 3 depicts a block diagram of an example imaging system including the image sensor of FIG. 1A or FIG. 2A , in accordance with the teachings of the present disclosure.

FIG. 4 depicts an illustration of an example column comparator operation, in accordance with the teachings of the present disclosure.

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Examples of an apparatus and method for enhancing bitline settling speed are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

Some image sensor designs may use a bitline floating method with a specified time control method by disabling the bitline during transfer, so as to enhance bitline settling speed by reducing signal coupling. The technique has the advantage of improving the settling speed while maintaining a similar design architecture. However, the bitline time control method may need to be redesigned to address bitline floating node swing fluctuation and floating diffusion coupling.

Theoretically, image sensor bitlines settle naturally and follow an RC time delay function without using a bitline settling boost function.

If bitline settling time is calculated by the following equation,

t settle = τ · ln ⁢ V in / 2 V 0.5 ⁢ ⁢ LSB

then the bitline has a long settling time with a large voltage swing. The situation with a current slew event is even worse in a large signal settling condition. As will be disclosed, with a differential bitline design in accordance with the teachings of the present disclosure, the system is able to exploit this new architecture to accelerate settling time of the bitline. Although the settling speed itself (compared to a non-differential, single bitline design) can already be decreased by half (because the system has the potential to half the input range), the time constant may still be limited by RC delay, unless the bitline short method for voltage domain global shutter design, presented herein, is implemented.

The example bitline short methods disclosed herein come from the concept of capacitor charge redistribution. If there are two unbalanced capacitors in a parallel connection, once a switch between them is turned on, charge redistribution occurs, and the voltage will settle down towards the same value. The RC delay for charge redistribution is Rs(C 1 /C 2 ), where Rs represents resistance through the switch path. When the bitline short structure is incorporated in the example circuits presented herein, there is a large decrease in settling time since Rs here is much smaller than resistance on the bitlines.

As will be shown, examples disclosed herein may be used for voltage domain global shutter (VDGS) products with differential bitlines. The structures and methods presented herein improve bitline settling speeds during the black (reference) signal and image signal average period by implementing a bitline short. This specific bitline short approach includes (1) the black signal and image signal read out operating simultaneously on two separate bitlines; and (2) after the average, the output will be settled at, or near, the midpoint of the black signal and image signal level. Under this condition, the bitline short method can settle down output 1 and 2 (see e.g., FIGS. 1A-2B ) nodes in advance, and thus significantly reduce the time consumed by an analog to digital converter operating during black signal and image signal average periods.

As will be shown in the figures, the circuit structure design improvements include one additional b 1 _boost switch (e.g., “b 1 _boost”), such as an NMOS, PMOS, or transmission gate between output 1 (e.g., “Out 1 ”) and output 2 (e.g., “Out 2 ”). This switch is coupled between output 1 and output 2 , and when it turns on, the switch immediately pulls output 1 and 2 together to a midpoint. The timing improvement has two purposes (1) settle down outputs 1 and 2 by shorting them; and (2) keeping the mismatch and leakage offset information in storage capacitance using a short and release operation.

During a VDGS global readout period, the black signal and the image signal are captured and stored separately in these two capacitors at nodes C 1 _blk and C 1 _sig (see e.g., FIGS. 1A and 2A ). At the 1st analog to digital conversion (see e.g., “1 st AD” in FIG. 1B ), the comparator will transfer mismatch information out of the circuit with the black signal and image signal as out 1 and out 2 DC levels. At the second analog to digital conversion (see e.g., “2nd AD” in FIG. 1B ), the black signal and image signal voltages will average together and drive output 1 and output 2 close to the middle of the black signal and image signal levels. At the moment of averaging, sample and hold 1 (e.g., “sh 1 ” in FIGS. 1B and 2B ) and sample and hold 2 (e.g., “sh 2 ” in FIGS. 1B and 2B ) transistors open at the same time. The system here may turn on the b 1 _boost switch right after, or slightly before, sample and hold 1 and sample and hold 2 open, and the performance of the bitline boost is similar. Since RC delay limits the bitline settling speed, the bitline short method overcomes this disadvantage by quickly shorting output 1 and output 2 nodes to the same middle potential. Lastly, before sample and hold 1 and sample and hold 2 turn off, the b 1 _boost should be closed first. This is so the circuit recognizes and keeps bitline mismatch information. Since the final voltage of output 1 and output 2 might be slightly different due to a mismatch, as long as this difference is kept in the 2nd analog to digital conversion (e.g., “2 nd AD” in FIG. 1B ), by adapting a correlated double sampling (CDS) method, the mismatch may be canceled out eventually. This mismatch should not be a dominant source of slow settling, considering its relatively small swing value.

To illustrate, the embodiments discussed above, and other embodiments, will be described below as they relate to the figures.

FIG. 1A shows an example circuit diagram 100 of part of an image sensor, in accordance with the teachings of the present disclosure. Circuit diagram 100 includes pixel circuitry (disposed in an image wafer) and readout circuitry disposed in a logic wafer (which may be bonded to a non-illuminated side of the pixel wafer with a bonding oxide, e.g., silicon oxide, or the like). In the depicted example, the pixel circuitry includes photodiode 101 , transfer gate 103 , floating diffusion 105 , source follower transistor 107 , row select transistor 109 , and reset transistor 111 . As shown, transfer gate 103 is coupled to transfer image charge from photodiode 101 to floating diffusion 105 . Source follower transistor 107 is coupled to floating diffusion 105 amplify the charge in floating diffusion 105 . Row select transistor 109 is coupled to output a pixel signal (e.g., amplified image charge or a black level reference signal) to readout circuitry. In response to a reset signal applied to the control terminal of reset transistor 111 , image charge is reset in the pixel circuitry.

Readout circuitry includes first sample and hold transistor 113 , first capacitor 115 , transistor 117 , second sample and hold transistor 119 , second capacitor 121 , transistor 123 , boost transistor 125 , third capacitance 127 , fourth capacitance 133 , first output switch “OUT 1 ” (including transistors 129 and 131 ), second output switch “OUT 2 ” (including transistors 135 and 137 ), transistor 139 , transistor 141 , transistor 143 , transistor 145 , transistor 147 , transistor 149 , transistor 151 , transistor 153 , transistor 155 , and transistor 157 .

As illustrated, first sample and hold transistor 113 is coupled to the pixel circuitry, and first capacitor 115 is coupled to first sample and hold transistor 113 to receive the pixel signal when first sample and hold transistor 113 is turned on. Second sample and hold transistor 119 is coupled to the pixel circuitry, and second capacitor 121 is coupled to second sample and hold transistor 119 to receive the pixel signal when second sample and hold transistor 119 is turned on. When transistor 139 is on, first output switch (“OUT 1 , including NMOS 131 and PMOS 129 transistors) is coupled to output the pixel signal from first capacitor 115 . The pixel signal is amplified by amplifier transistor 117 —since the control terminal is coupled to first capacitor 115 to amplify a signal on first capacitor 115 . Similarly, when transistor 141 is on, second output switch (“OUT 2 , including NMOS 137 and PMOS 135 transistors) is coupled to output the pixel signal from second capacitor 121 . The pixel signal is amplified by amplifier transistor 123 —since the control terminal is coupled to first capacitor 121 to amplify a signal on first capacitor 121 . Boost transistor 125 is coupled to connect the first output switch OUT 1 and the second output switch OUT 2 when boost transistor 125 is turned on. As stated above, when boost transistor 125 is on, a voltage at the first output switch OUT 1 and the second output switch OUT 2 is equalized.

In the depicted example, the pixel signal includes a black level reference voltage (e.g., a reference voltage of pixel circuit before it has generated image charge) and an image signal voltage indicative of image charge generated by photodiode 101 . The black level reference voltage may be stored on first capacitor 115 , and the image signal voltage may be stored on second capacitor 121 . The signals may be output at separate times from pixel circuitry.

In the illustrated example, third capacitance 127 (e.g., a parasitic capacitance) is coupled to ground between a first terminal of boost transistor 125 and the first output switch, and fourth capacitance 133 (e.g., a parasitic capacitance) is also coupled to ground between a second terminal of boost transistor 125 and the second output switch. One of skill in the art will appreciate that capacitors described herein may include parasitic capacitances, as well as doped wells, plate capacitors, metal capacitors, or the like. Transistors 153 and 155 are coupled to power rails. Transistor 149 is coupled between transistors 143 and 155 , and transistor 147 is coupled between transistors 153 and 145 . Transistors 157 and 151 are coupled to the control terminals of transistors 155 and 149 , respectively.

FIG. 1B illustrates an example timing diagram for the circuit of FIG. 1A , in accordance with the teachings of the present disclosure. As shown, b 1 _boost turns on immediately after sh 1 and sh 2 (e.g., 113 and 119 in FIG. 1A ) turn on to average the signals. Then b 1 _boost is turned off before sh 1 and sh 2 turn off to retain sh 1 and sh 2 mismatch info. Bl boost can be turned on before sh 1 and sh 2 turn on, resulting in output 1 and output 2 (“out 1 ” and “out 2 ”, respectively) having additional coupling. It is appreciated that b 1 _boost can be achieved with a PMOS switch, NMOS switch, or transmission gate, depended on the desired design.

FIG. 2A shows an example circuit diagram of part of an image sensor 200 , in accordance with the teachings of the present disclosure. It is appreciated that image sensor 200 is similar to the image sensor of FIG. 1A , however, FIG. 2A further includes first capacitance 261 and second capacitance 263 coupled to alter a capacitance of first capacitor 215 and second capacitor 221 , respectively (e.g., by applying a voltage to the control terminals of the devices). In the depicted example, first capacitance 261 and second capacitance 263 include a first metal-oxide-semiconductor capacitor (“MOSCAP”) device and second MOSCAP device, respectively. In the depicted example, the first MOSCAP device and second MOSCAP device hold equal or less charge than first sample and hold transistor 213 and second sample and hold transistor 219 , respectively (e.g., the MOSCAPs are ˜0.8-1× the size of sh 1 213 and sh 2 219 ). The size ratio of 0.8-to-1 of sh 3 to sh 1 and sh 2 is chosen based on simulations so that sh 3 counterbalances the disturbance of sh 1 /sh 2 with the right amount of voltage impact. In some embodiments, the MOSCAPs may be replaced by metal-insulator-metal (MIM) capacitors.

As will be shown in the timing diagram in FIG. 2B , additional boost bitline speed is achieved by adding charge injection and feed through removal (due to falling edges of sh 1 and sh 2 ) with the MOSCAPS. The sh 3 offset compensation MOSCAP transistors turn on during the average sample and hold time. Sh 1 and sh 2 come on at the same time to merge (share or average) the charges of C 1 _blk and C 2 _sig together, while output 1 and output 2 are also averaged under the control of b 1 _boost.

In the depicted example, the first MOSCAP device and the second MOSCAP device are matched with charge distribution of the first sample and hold transistor and the second sample and hold transistor, respectively. In some examples, matched with charge distribution means that when the rising edges of sh 1 /sh 2 and the falling edge of sh 3 meet each other, the falling sh 3 minimizes (e.g., offsets or balances) the impact of the rising sh 1 /sh 2 from spreading to OUT 1 /OUT 2 through transistors 217 / 223 . This “offset to 0 effect” is balanced between the (value of) first capacitance 261 and the gate-to-source capacitance of 213 , and also, second capacitance 263 and gate-to-source capacitance of transistor 219 .

FIG. 2B illustrates a timing diagram for the circuit diagram of FIG. 2A , in accordance with the teachings of the present disclosure. During the 2 nd phase (readout) of the voltage domain global shutter, the bitline settling time is determined by the difference between the image signal and black signal level. In a simple RC network, settling time is longer for larger input swing. Accordingly, adding the MOSCAP devices depicted in FIG. 2A improves the settling speed by adding a charge injection/feedthrough mechanism. This contribution may dramatically improve bitline settling time especially for the small settling error requirement.

FIG. 3 depicts an example block diagram of an imaging system 300 including the image sensor of FIG. 1A or FIG. 2A , in accordance with the teachings of the present disclosure. Imaging system 300 includes pixel array 305 , control circuitry 321 , readout circuitry 311 , and function logic 315 . In one example, pixel array 305 is a two-dimensional (2D) array of photodiodes, or image sensor pixels (e.g., pixels P 1 , P 2 . . . , Pn). As illustrated, photodiodes are arranged into rows (e.g., rows R 1 to Ry) and columns (e.g., column C 1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc. However, photodiodes do not have to be arranged into rows and columns and may take other configurations.

In one example, after each image sensor photodiode/pixel in pixel array 305 has acquired its image data or image charge, the image data is readout by readout circuitry 311 and then transferred to function logic 315 . In various examples, readout circuitry 311 may include amplification circuitry, analog to digital conversion circuitry (e.g., the ADC depicted to convert the pixel signal into digital image data), and the like. Function logic 315 may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry 311 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques, such as a serial readout or a full parallel readout of all pixels simultaneously.

In one example, control circuitry 321 is coupled to pixel array 305 to control operation of the plurality of photodiodes in pixel array 305 . For example, control circuitry 321 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within pixel array 305 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows. In another example, image acquisition is synchronized with lighting effects such as a flash.

In one example, imaging system 300 may be included in an automobile, cell phone, camera, or the like. Additionally, imaging system 300 may be coupled to other pieces of hardware such as a processor (general purpose or otherwise), memory elements, output (USB port, wireless transmitter, HDMI port, etc.), lighting/flash, electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and/or display. Other pieces of hardware may deliver instructions to imaging system 300 , extract image data from imaging system 300 , or manipulate image data supplied by imaging system 300 .

FIG. 4 depicts an illustration of an example column comparator ramp operation, in accordance with the teachings of the present disclosure. As discussed above, the system here may turn on b 1 _boost immediately after sh 1 and sh 2 turn on to average the signals. The system then turns off b 1 _boost before sh 1 and sh 2 turn off to keep the sh 1 /sh 2 mismatch info. This force and release operation is designed to purposely tune the width of the b 1 _boost signal so that it can force output 1 and output 2 towards a middle level quickly, and then in the b 1 _boost release mode, output 1 and output 2 can settle separately to keep the mismatch information (delta 1 +delta 2 ) in two different bitlines. The short pulse of “b 1 _boost” is to both (1) force the merging of C 1 _BLK and C 2 _SIG when b 1 _boost is on, and (2) to allow the two columns (BLK/SIG) to relax back to their original natural delta 1 and delta 2 when b 1 _boost is off, therefore, when A and B ( FIG. 4 ) are measured by the ADC, both delta 1 and delta 2 have been automatically cancelled out. Put another way, the turning off of b 1 _boost may be used to make sure that the intrinsic delta 1 and delta 2 are not showing in the picture of the measurements of the BLK/SIG signals. It is appreciated that delta 1 and delta 2 represent each bitline output on-silicon voltage deviation from an ideal voltage value without mismatch. For example, process, temperature, and voltage variance on a source follower device compared to an ideal device working with a stable supply at room temperature.

The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.