Reference-free multi-level sensing circuit for computing-in-memory applications, reference-free memory unit for computing-in-memory applications and sensing method thereof

The present disclosure relates to a multi-level sensing circuit for computing-in-memory applications, a memory unit for computing-in-memory applications and a sensing method thereof. More particularly, the present disclosure relates to a reference-free multi-level sensing circuit for computing-in-memory applications, a reference-free memory unit for computing-in-memory applications and a sensing method thereof.

In these years, due to the industrial growth of mobile device, medical electrical equipment, portable storage, etc., requirement of memory with low power, high speed and high density is increased. For computing in memory, a large number of word lines (WL) are activated at same time. Various input patterns cause a widely bit-line (BL) current distribution. The BL current distribution of computational results (multiply-and-accumulate (MAC) value) is dependent on the various input patterns.

FIG. 1 shows a block diagram of a conventional memory unit for computing-in-memory applications; and FIG. 2 shows a schematic view of a probability distribution of a voltage V BL of a first bit line BL of FIG. 1 . The conventional memory unit includes a word-line driver 110 , a memory array 120 , a reference generator 130 and an input/output (I/O) unit 140 . When sensing the memory array 120 , the reference generator 130 needs to generate a plurality of reference voltages corresponding to the various input patterns, and then the voltage V BL of the first bit line BL are digitalized. However, there is a small sensing margin D 1 between one of voltage levels of the first bit lines BL (e.g., “Mac 1 ”-“Mac 8 ” in FIG. 2 ) and one of the reference voltages (e.g., “Ref 1 ”-“Ref 7 ” in FIG. 2 ). The reference generator 130 generates the reference voltages and causes very large power consumption. Therefore, a reference-free multi-level sensing circuit for computing-in-memory applications, a reference-free memory unit for computing-in-memory applications and a sensing method thereof having the features of increasing the sensing margin and removing the power consumption of the reference generator are commercially desirable.

According to one aspect of the present disclosure, a reference-free multi-level sensing circuit for computing-in-memory applications is controlled by a first bit line and a second bit line. The reference-free multi-level sensing circuit for the computing-in-memory applications includes a voltage sense amplifier, a precharging unit and an encoding unit. The voltage sense amplifier is electrically connected to the first bit line and the second bit line. The precharging unit is electrically connected to the voltage sense amplifier. The encoding unit is electrically connected to the voltage sense amplifier. The encoding unit includes a first register, a second register, a third register, a fourth register and an encoder. The first register is electrically connected to the voltage sense amplifier and outputs a first register output value. The first register output value feedback controls the precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value. A voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The second register is electrically connected to the voltage sense amplifier and outputs a second register output value. The third register is electrically connected to the second register and outputs a third register output value. The fourth register is electrically connected to the third register and outputs a fourth register output value. The encoder is electrically connected to the second register, the third register and the fourth register. The encoder generates a plurality of encoded values according to the second register output value, the third register output value and the fourth register output value, and the encoded values and the first register output value are formed a multi-bit signal to estimate voltage levels of the first bit line and the second bit line.

According to another aspect of the present disclosure, a reference-free memory unit for computing-in-memory applications includes at least one memory cell and a reference-free multi-level sensing circuit for computing-in-memory applications. The at least one memory cell is connected between a first bit line and a second bit line. The at least one memory cell is connected to a word line and controlled by the word line. The reference-free multi-level sensing circuit for the computing-in-memory applications is connected to the at least one memory cell and controlled by the first bit line, the second bit line and the word line. The reference-free multi-level sensing circuit for the computing-in-memory applications includes a voltage sense amplifier, a precharging unit and an encoding unit. The voltage sense amplifier is electrically connected to the first bit line and the second bit line. The precharging unit is electrically connected between the first bit line and the second bit line. The encoding unit is electrically connected to the voltage sense amplifier and includes a first register, a second register, a third register, a fourth register and an encoder. The first register is electrically connected to the voltage sense amplifier and outputs a first register output value. The first register output value feedback controls the precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value, and a voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The second register is electrically connected to the voltage sense amplifier and outputs a second register output value. The third register is electrically connected to the second register and outputs a third register output value. The fourth register is electrically connected to the third register and outputs a fourth register output value. The encoder is electrically connected to the second register, the third register and the fourth register. The encoder generates a plurality of encoded values according to the second register output value, the third register output value and the fourth register output value, and the encoded values and the first register output value are formed a multi-bit signal to estimate voltage levels of the first bit line and the second bit line.

According to further another aspect of the present disclosure, a sensing method of the reference-free memory unit for the computing-in-memory applications provides a voltage level applying step, a first sensing step, a second sensing step, a third sensing step and a fourth sensing step. The voltage level applying step is for applying a voltage level to the word line. The first sensing step is for driving the memory cell to generate the first bit line and the second bit line according to the voltage level of the word line. The second sensing step is for driving the voltage sense amplifier to generate an output voltage level of a first output node according to the first bit line and the second bit line. The third sensing step is for driving the encoding unit to generate a switching signal according to the output voltage level of the first output node, and transmitting the switching signal to the precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value. The voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The fourth sensing step is for driving the voltage sense amplifier and the encoding unit to generate the multi-bit signal according to the first bit line and the second bit line.

The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

FIG. 1 shows a block diagram of a conventional memory unit for computing-in-memory applications;

FIG. 2 shows a schematic view of a probability distribution of a voltage of a first bit line of FIG. 1 ;

FIG. 3 shows a block diagram of a reference-free multi-level sensing circuit for computing-in-memory applications according to one embodiment of the present disclosure;

FIG. 4 shows a circuit diagram of a sense amplifier of the reference-free multi-level sensing circuit for the computing-in-memory applications of FIG. 3 ;

FIG. 5 shows a block diagram of a reference-free memory unit for computing-in-memory applications according to another embodiment of the present disclosure;

FIG. 6 shows a circuit diagram of a memory cell of the memory unit of FIG. 5 ;

FIG. 7 shows timing diagrams of voltages of the first bit line, the second bit line and the voltage sense amplifier of FIG. 3 ;

FIG. 8 shows a schematic view of a probability distribution of a voltage of the first bit line of FIG. 3 ; and

FIG. 9 shows a flow chart of a sensing method of a reference-free memory unit for computing-in-memory applications according to further another embodiment of the present disclosure.

Before describing any embodiments in detail, some terms used in the following are described. A voltage level of “1” represents that the voltage is equal to a voltage source VDD. The voltage level of “0” represents that the voltage is equal to a ground voltage. A PMOS transistor and an NMOS transistor represent a P-type MOS transistor and an N-type MOS transistor, respectively.

FIG. 3 shows a block diagram of a reference-free multi-level sensing circuit 100 for computing-in-memory applications according to one embodiment of the present disclosure; and FIG. 4 shows a circuit diagram of a sense amplifier SA of the reference-free multi-level sensing circuit 100 for the computing-in-memory applications of FIG. 3 . The reference-free multi-level sensing circuit 100 for the computing-in-memory applications is controlled by a first bit line BL and a second bit line BLB. The reference-free multi-level sensing circuit 100 for the computing-in-memory applications includes a voltage sense amplifier SA, a precharging unit 200 and an encoding unit 300 .

The voltage sense amplifier SA is electrically connected to the first bit line BL and the second bit line BLB. In detail, the voltage sense amplifier SA has an inner node INP, a first output node Q and a second output node QB, as shown in FIG. 4 . The voltage sense amplifier SA includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 , a seventh transistor M 7 , an eighth transistor M 8 and a ninth transistor M 9 . The first transistor M 1 is connected between the inner node INP and a ground voltage. The second transistor M 2 is connected to the first output node Q and the second output node QB. The third transistor M 3 is connected to the first output node Q and the second output node QB. The fourth transistor M 4 is connected between the second transistor M 2 and the voltage source VDD. The fourth transistor M 4 is connected to the first output node Q and the second output node QB. The fifth transistor M 5 is connected between the third transistor M 3 and the voltage source VDD. The fifth transistor M 5 is connected to the first output node Q and the second output node QB. The sixth transistor M 6 is connected between the second transistor M 2 and the voltage source VDD. The sixth transistor M 6 is connected to the first output node Q. The seventh transistor M 7 is connected between the third transistor M 3 and the voltage source VDD. The seventh transistor M 7 is connected to the second output node QB. The eighth transistor M 8 is connected between the second transistor M 2 and the first transistor M 1 . The eighth transistor M 8 is connected to the inner node INP and the first bit line BL. The ninth transistor M 9 is connected between the third transistor M 3 and the first transistor M 1 . The ninth transistor M 9 is connected to the inner node INP and the second bit line BLB. Each of the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the eighth transistor M 8 and the ninth transistor M 9 is an NMOS transistor. Each of the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 is a PMOS transistor.

The precharging unit 200 is electrically connected between the first bit line BL and the second bit line BLB, so that the precharging unit 200 is electrically connected to the voltage sense amplifier SA via the first bit line BL and the second bit line BLB. The precharging unit 200 is controlled by a switching signal SW 1 , an inverse switching signal SW 1 B and a bias voltage BIAS. The switching signal SW 1 and the inverse switching signal SW 1 B are inverted relative to each other. In detail, the precharging unit 200 has an internal node INN and includes a first precharging transistor PM 1 , a second precharging transistor PM 2 and a third precharging transistor PM 3 . The first precharging transistor PM 1 has a first precharging gate, a first precharging drain and a first precharging source. The first precharging gate is coupled to the bias voltage BIAS. The first precharging drain is connected to the internal node INN, and the first precharging source is coupled to the voltage source VDD. The second precharging transistor PM 2 has a second precharging gate, a second precharging drain and a second precharging source. The second precharging gate is coupled to the switching signal SW 1 . The second precharging drain is connected to the first bit line BL, and the second precharging source is connected to the internal node INN. The third precharging transistor PM 3 has a third precharging gate, a third precharging drain and a third precharging source. The third precharging gate is coupled to the inverse switching signal SW 1 B. The third precharging drain is connected to the second bit line BLB, and the third precharging source is connected to the internal node INN. Each of the first precharging transistor PM 1 , the second precharging transistor PM 2 and the third precharging transistor PM 3 is a PMOS transistor.

The encoding unit 300 is electrically connected to the voltage sense amplifier SA. The encoding unit 300 includes a first register 310 , a second register 320 , a third register 330 , a fourth register 340 and an encoder 350 . The first register 310 is electrically connected to the voltage sense amplifier SA and outputs a first register output value OUT<2>. The first register output value OUT<2> is equal to the switching signal SW 1 . In other words, the first register output value OUT<2> feedback controls the precharging unit 200 so as to enable the precharging unit 200 to precharge one of the first bit line BL and the second bit line BLB according to the first register output value OUT<2>. A voltage level of the one of the first bit line BL and the second bit line BLB is lower than a voltage level of the other one of the first bit line BL and the second bit line BLB. The second register 320 is electrically connected to the voltage sense amplifier SA and outputs a second register output value Q 0 . The third register 330 is electrically connected to the second register 320 and outputs a third register output value Q 1 . The fourth register 340 is electrically connected to the third register 330 and outputs a fourth register output value Q 2 . The encoder 350 is electrically connected to the second register 320 , the third register 330 and the fourth register 340 . The encoder 350 generates a plurality of encoded values according to the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 . The encoded values include a first encoded value OUT<0> and a second encoded value OUT<1>. The encoded values and the first register output value OUT<2> are formed a multi-bit signal OUT<2:0> to estimate voltage levels of the first bit line BL and the second bit line BLB. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 1, 1, 1, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 1, 1, respectively. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 0, 1, 1, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 0, 1, respectively. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 0, 0, 1, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 1, 0, respectively. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 0, 0, 0, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 0, 0, respectively. Therefore, the reference-free multi-level sensing circuit 100 for the computing-in-memory applications of the present disclosure utilizes a differential multi-level sensing scheme without any reference generator so as to increase a sensing margin and remove the power consumption of the reference generator.

FIG. 5 shows a block diagram of a reference-free memory unit 400 for computing-in-memory applications according to another embodiment of the present disclosure; and FIG. 6 shows a circuit diagram of a memory cell MC of the memory unit of FIG. 5 . The reference-free memory unit 400 for the computing-in-memory applications includes a word-line driver 110 , a memory array 120 and a plurality of reference-free multi-level sensing circuits 100 for the computing-in-memory applications.

The word-line driver 110 generates a plurality of word lines WL. The memory array 120 is electrically connected to the word-line driver 110 via the word lines WL. The memory array 120 includes a plurality of memory cells MC. Each of the memory cells MC is connected between a first bit line BL and a second bit line BLB. Each of the memory cells MC is connected to one of the word lines WL and controlled by the one of the word lines WL. Each of the reference-free multi-level sensing circuits 100 for the computing-in-memory applications is connected to the memory array 120 via the first bit line BL and the second bit line BLB. In one embodiment, each of the memory cells MC has a first cell internal node CI 1 and a second cell internal node CI 2 . Each of the memory cells includes a first memory cell transistor CM 1 , a second memory cell transistor CM 2 , a third memory cell transistor CM 3 , a fourth memory cell transistor CM 4 , a fifth memory cell transistor CM 5 and a sixth memory cell transistor CM 6 , as shown in FIG. 6 . The first memory cell transistor CM 1 is connected to the ground voltage, the first cell internal node CI 1 and the second cell internal node CI 2 . The second memory cell transistor CM 2 is connected to the voltage source VDD, the first cell internal node CI 1 and the second cell internal node CI 2 . The third memory cell transistor CM 3 is connected to the ground voltage, the first cell internal node CI 1 and the second cell internal node CI 2 . The fourth memory cell transistor CM 4 is connected to the voltage source VDD, the first cell internal node CI 1 and the second cell internal node CI 2 . The fifth memory cell transistor CM 5 is connected to the first cell internal node CI 1 , the first bit line BL and the word line WL. The sixth memory cell transistor CM 6 is connected to the second cell internal node CI 2 the second bit line BLB and the word line WL. Each of the first memory cell transistor CM 1 , the third memory cell transistor CM 3 , the fifth memory cell transistor CM 5 and the sixth memory cell transistor CM 6 is an NMOS transistor. Each of the second memory cell transistor CM 2 and the fourth memory cell transistor CM 4 is a PMOS transistor. Accordingly, the reference-free memory unit 400 for the computing-in-memory applications of the present disclosure utilizes a differential multi-level sensing scheme without any reference generator so as to increase a sensing margin and remove the power consumption of the reference generator.

FIG. 7 shows timing diagrams of voltages of the first bit line BL, the second bit line BLB and the voltage sense amplifier SA of FIG. 3 ; and FIG. 8 shows a schematic view of a probability distribution of a voltage V BL of a first bit line BL of FIG. 3 . There are four examples in FIG. 7 . In a first example, “Mac 1 ” represents a voltage level of one of the first bit line BL and the second bit line BLB. “Mac 8 ” represents a voltage level of the other one of the first bit line BL and the second bit line BLB. “Mac 1 ” is lower than “Mac 8 ” during four SAEN clock cycles and precharged by the precharging unit 200 . “Mac 1 / 8 ” represents a comparison result between “Mac 1 ” and “Mac 8 ”. In a second example, “Mac 2 ” represents the voltage level of one of the first bit line BL and the second bit line BLB. “Mac 7 ” represents the voltage level of the other one of the first bit line BL and the second bit line BLB. “Mac 2 ” is lower than “Mac 7 ” during three SAEN clock cycles and precharged by the precharging unit 200 . “Mac 2 / 7 ” represents a comparison result between “Mac 2 ” and “Mac 7 ”. In a third example, “Mac 3 ” represents the voltage level of one of the first bit line BL and the second bit line BLB. “Mac 6 ” represents the voltage level of the other one of the first bit line BL and the second bit line BLB. “Mac 3 ” is lower than “Mac 6 ” during two SAEN clock cycles and precharged by the precharging unit 200 . “Mac 3 / 6 ” represents a comparison result between “Mac 3 ” and “Mac 6 ”. In a fourth example, “Mac 4 ” represents the voltage level of one of the first bit line BL and the second bit line BLB. “Mac 5 ” represents the voltage level of the other one of the first bit line BL and the second bit line BLB. “Mac 4 ” is lower than “Mac 5 ” during one SAEN clock cycle and precharged by the precharging unit 200 . “Mac 4 / 5 ” represents a comparison result between “Mac 4 ” and “Mac 5 ”. In FIGS. 2 and 8 , it is obvious that a sensing margin D 2 of the present disclosure is about twice greater than a sensing margin D 1 of the conventional memory unit due to the lack of the reference generator.

FIG. 9 shows a flow chart of a sensing method 500 of a reference-free memory unit 400 for computing-in-memory applications according to further another embodiment of the present disclosure. The sensing method 500 provides a voltage level applying step S 1 , a first sensing step S 2 , a second sensing step S 3 , a third sensing step S 4 and a fourth sensing step S 5 .

The voltage level applying step S 1 is for applying a voltage level to the word line WL. The first sensing step S 2 is for driving the memory cell MC to generate the voltage levels of the first bit line BL and the second bit line BLB according to the voltage level of the word line WL. The second sensing step S 3 is for driving the voltage sense amplifier SA to generate an output voltage level of a first output node Q according to the first bit line BL and the second bit line BLB. The third sensing step S 4 is for driving the encoding unit 300 to generate a switching signal SW 1 (i.e., the first register output value OUT<2>) according to the output voltage level of the first output node Q, and transmitting the switching signal SW 1 to the precharging unit 200 so as to enable the precharging unit 200 to precharge one of the first bit line BL and the second bit line BLB according to the first register output value OUT<2>. The voltage level of the one of the first bit line BL and the second bit line BLB is lower than a voltage level of the other one of the first bit line BL and the second bit line BLB. The fourth sensing step S 5 is for driving the voltage sense amplifier SA and the encoding unit 300 to generate the multi-bit signal OUT<2:0> according to the first bit line BL and the second bit line BLB.

In addition, in the third sensing step S 4 , the precharging unit 200 is coupled between the first bit line BL and the second bit line BLB. The precharging unit 200 is electrically connected to the memory cell MC via the first bit line BL and the second bit line BLB. The precharging unit 200 is controlled by a switching signal SW 1 , an inverse switching signal SW 1 B and a bias voltage BIAS, and the first register output value OUT<2> is equal to the switching signal SW 1 . The precharging unit 200 includes a first precharging transistor PM 1 , a second precharging transistor PM 2 and a third precharging transistor PM 3 . The first precharging transistor PM 1 , the second precharging transistor PM 2 and the third precharging transistor PM 3 are controlled by the bias voltage BIAS, the switching signal SW 1 and the inverse switching signal SW 1 B, respectively. In the fourth sensing step S 5 , the encoded values include a first encoded value OUT<0> and a second encoded value OUT<1>. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 1, 1, 1, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 1, 1, respectively. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 0, 1, 1, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 0, 1, respectively. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 0, 0, 1, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 1, 0, respectively. When the second register output value Q 0 , the third register output value Q 1 and the fourth register output value Q 2 are equal to 0, 0, 0, respectively, the first encoded value OUT<0> and the second encoded value OUT<1> are equal to 0, 0, respectively. Therefore, the sensing method 500 of the present disclosure utilizes a differential multi-level sensing scheme without any reference generator to sense the first bit line BL and the second bit line BLB to obtain the switching signal SW 1 , and then precharge the lower potential one of the first bit line BL and the second bit line BLB via the switching signal SW 1 . Moreover, the sensing method 500 of the present disclosure utilizes a single-ended precharging scheme which does not consume additional power because the first bit line BL and the second bit line BLB still need to be precharged in the next cycle, so that the sensing method 500 of the present disclosure is suitable for the computing-in-memory applications.

According to the aforementioned embodiments and examples, the advantages of the present disclosure are described as follows.

1. The reference-free multi-level sensing circuit for the computing-in-memory applications, the reference-free memory unit for the computing-in-memory applications and the sensing method thereof utilize a differential multi-level sensing scheme without any reference generator so as to increase sensing margin to achieve high accuracy and remove the power consumption of the reference generator.

2. The sensing method of the present disclosure utilizes a differential multi-level sensing scheme without any reference generator to sense the first bit line and the second bit line to obtain the switching signal, and then precharge the lower potential one of the first bit line and the second bit line via the switching signal. Moreover, the sensing method of the present disclosure utilizes a single-ended precharging scheme which does not consume additional power because the first bit line and the second bit line still need to be precharged in the next cycle, so that the sensing method of the present disclosure is suitable for the computing-in-memory applications.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.