Memory device with multiple layers

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-045645, filed Mar. 13, 2018, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a memory device.

Development of memory devices including memory cells arranged in three dimensions is ongoing. For example, in a NAND-type nonvolatile memory device, a plurality of word lines and a plurality of select gates are stacked with intervening interlayer insulating films and semiconductor pillars penetrating the word lines and the select gates in the layer stacking direction are provided. Memory cells are disposed at location where the semiconductor pillars intersect the plurality of word lines. To increase the memory capacity of such a semiconductor device, it is effective to make thinner the word lines, the select gates, and the interlayer insulating films and to increase the number of the stacked word lines. However, making the word lines and the select gates thinner increases parasitic resistances of the word lines and the select gates and making the interlayer insulating films thinner increases parasitic capacitances. This often causes malfunctioning of the memory cells.

FIG. 1 is a perspective view schematically illustrating a memory device according to an embodiment.

FIG. 2 is a partial cross-sectional view schematically illustrating the memory device according to the embodiment.

FIG. 3 is a block diagram illustrating a configuration of the memory device according to the embodiment.

FIGS. 4A and 4B are time charts illustrating operation of the memory device according to the embodiment.

FIGS. 5A and 5B are schematic diagrams illustrating operation of a memory device according to a comparison.

FIGS. 6A and 6B are schematic diagrams illustrating procedures of manufacturing the memory device according to the embodiment.

FIGS. 7A and 7B are schematic diagrams illustrating procedures, subsequent to those of FIGS. 6A and 6B , of manufacturing the memory device according to the embodiment.

FIGS. 8A and 8B are schematic diagrams illustrating procedures, subsequent to those of FIGS. 7A and 7B , of manufacturing the memory device according to the embodiment.

FIGS. 9A and 9B are schematic diagrams illustrating procedures, subsequent to those of FIGS. 8A and 8B , of manufacturing the memory device according to the embodiment.

An embodiment provides a memory device that can prevent malfunctioning of memory cells.

In general, according to one embodiment, a memory device includes a plurality of word lines spaced from one another in a first direction, a first insulating film provided between the word lines adjacent to each other in the first direction, a plurality of select gates located above the plurality of word lines in the first direction, a first intermediate electrode provided between the plurality of word lines and the select gates, a second insulating film provided between the first intermediate electrode and the select gates, a semiconductor pillar extending through the plurality of word lines, the first insulating film, the first intermediate electrode, the second insulating film, and the select gates, and extending in the first direction, and a charge retention film located between each of the plurality of word lines and the semiconductor pillar. The second insulating film has a second thickness in the first direction that is greater than a first thickness of the first insulating film in the first direction.

Embodiments will be described hereinafter with reference to the drawings. In the drawings, the same sections are denoted by the same reference signs and detailed description of the same sections is omitted as appropriate, while different sections will be described. It is noted that the drawings are either schematic or conceptual and the relationship between a thickness and a width of each section, a proportion of magnitudes of sections, and the like are not necessarily identical to actual ones. Furthermore, even the same sections are often depicted at different sizes or different proportions depending on the drawings.

Moreover, arrangement and a configuration of each section will be described using an X-axis, a Y-axis, and a Z-axis shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to one another and represent an X direction, a Y direction, and a Z direction, respectively. Furthermore, the description is often given while assuming that the Z direction is upward and an opposite direction to the Z direction is downward.

FIG. 1 is a perspective view schematically illustrating a memory device 1 according to an embodiment. The memory device 1 is, for example, a NAND-type nonvolatile memory device and it includes a memory cell array MCA. In FIG. 1 , portions of the insulating films are omitted for illustrating a configuration of the memory cell array MCA.

The memory cell array MCA includes a conductive layer CL, a plurality of electrode layers, and interlayer insulating films 13 , 15 , and 17 . The conductive layer CL is, for example, a P-type well provided in a silicon substrate (not shown) or in a semiconductor layer provided on the silicon substrate over an intervening interlayer insulating film. The plurality of electrode layers are stacked over the conductive layer CL and include, for example, a select gate SGS, a plurality of word lines WL, and a select gate SGD.

The plurality of electrode layers also include dummy word lines WLS and WLD. The dummy word line WLS is provided between the select gate SGS and the word line WL proximate to the select gate SGS. The dummy word line WLD is provided between the select gate SGD and the word line WL proximate to the select gate SGD.

As shown in FIG. 1 , the select gate SGD is divided into a plurality of select gates SGDA and a plurality of select gates SGDB by an isolation groove SHL. The select gates SGDA and the select gates SGDB are stacked on the word lines WL.

The interlayer insulating film 13 is provided between the conductive layer CL and the select gate SGS. The interlayer insulating films 15 are each provided between each two electrode layers adjacent to each other in the Z direction. The interlayer insulating film 17 is provided on the select gate SGD.

The memory cell array MCA further includes a plurality of semiconductor pillars SP. The semiconductor pillars SP penetrate the word lines WL and the select gate SGD and extend in the Z direction (refer to FIG. 2 ).

The memory device 1 further includes bit lines BL and a source line SL provided above the memory cell array MCA. The semiconductor pillars SP are each electrically connected to one bit lines BL via connection plugs CH and V 1 . The source line SL is electrically connected to the conductive layer CL via, for example, a connection conductor LI. The connection conductor LI is, for example, a plate-like conductor provided on a lateral side of the memory cell array MCA.

FIG. 2 is a partial cross-sectional view schematically illustrating a portion of the memory device 1 according to the embodiment. FIG. 2 is a schematic diagram illustrating configurations of a memory hole MH including the semiconductor pillar and the electrode layers.

As shown in FIG. 2 , the semiconductor pillar SP is provided within the memory hole MH (refer to FIG. 6B ) penetrating the word lines WL and the select gate SGD and it extends in the Z direction. The semiconductor pillar SP includes a semiconductor film SF and an insulating core IC. The insulating core IC is, for example, silicon oxide and extends in the Z direction within the memory hole MH. The semiconductor film SF is, for example, a polysilicon film and provided to cover the insulating core IC.

The semiconductor pillar SP is connected to a single bit line BL via the connection plugs CH and V 1 . Specifically, the connection plug CH is connected to the semiconductor film SF on an upper end of the semiconductor pillar SP. On the other hand, a semiconductor layer SC is provided between a lower end of the semiconductor pillar SP and the conductive layer CL. The semiconductor layer SC extends through the select gate SGS. The lower end of the semiconductor layer SC is connected to the conductive layer CL and an upper end thereof is connected to the semiconductor pillar SP. Furthermore, an insulating film 25 is provided between the semiconductor layer SC and the adjacent portion of the select gate SGS.

Moreover, a memory film MF is provided within the memory hole MH. The memory film MF is provided between the semiconductor pillar SP and the inner wall of the memory hole MH. The memory film MF includes, for example, a block insulating film FL 1 , a charge retention film FL 2 , and a tunnel insulating film FL 3 . The block insulating film FL 1 , the charge retention film FL 2 , and the tunnel insulating film FL 3 are stacked in order on the inner wall of the memory hole MH.

As shown in FIG. 2 , dummy word lines WLD 0 and WLD 1 are disposed between the select gate SGD and the uppermost word line WL. The dummy word line WLD 0 is disposed between the select gate SGD and the dummy word line WLD 1 .

In the memory device 1 according to the present embodiment, an interlayer insulating film 15 M is provided between the select gate SGD and the dummy word line WLD 0 . The interlayer insulating film 15 M contains the same material as, for example, that of the interlayer insulating films 15 provided between the word lines WL adjacent in the Z direction. The interlayer insulating film 15 M is, for example, a silicon oxide film. Furthermore, the interlayer insulating film 15 M is formed to have a thickness T 2 in the Z direction that is larger than a thickness T 1 of the interlayer insulating films 15 in the Z direction.

FIG. 3 is an electrical schematic diagram illustrating a configuration of the memory device according to the embodiment. The word lines WL are each connected to, for example, a drive circuit WD 1 . The dummy word lines WLD 0 and WLD 1 are connected to a common drive circuit WD 2 . The select gates SGD and SGS are connected to drive circuits GD 1 and GD 2 , respectively. The drive circuits WD 1 , WD 2 , GD 1 and GD 2 are connected to a voltage source (not shown), and selectively supply a voltage to the string or strings of select gate transistors or memory cells connected thereto. Furthermore, the semiconductor pillars SP are each connected to a sense amplifier SA via the bit line BL.

As shown in FIG. 3 , a memory cell MC is disposed at the location where each semiconductor pillar SP intersects each word line WL. The memory cell MC includes part of the memory film MF located between the semiconductor pillar SP and the word line WL as a charge retention section.

A select transistor STD is provided at the location where each semiconductor pillar SP intersects the select gate SGD. The select transistor STD includes part of the memory film MF located, for example, between the semiconductor pillar SP and the select gate SGD as a gate insulating film. Moreover, a select transistor STS is provided at the location where the select gate SGS intersects the semiconductor layer SC. The select transistor STS includes the insulating film 25 located between the semiconductor layer SC and the select gate SGS as a gate insulating film (refer to FIG. 2 ).

FIGS. 4A and 4B are time charts illustrating operation of the memory device 1 according to the embodiment. FIGS. 4A and 4B illustrate biases supplied from the drive circuits WD 1 , WD 2 , and GD 1 to the electrode layers when data is written to one memory cell MC.

A select gate SGD_SEL shown in FIG. 4A is, for example, the SGDA shown in FIG. 1 , and a select gate SGD_USEL shown in FIG. 4B is, for example, the SGDB shown in FIG. 1 . In the following description, it is assumed that the select gate SGDA is the selected select gate SGD_SEL and that the select gate SGDB is the unselected select gate SGD_USEL.

FIGS. 4A and 4B illustrate biases V SGD , V WLD , and V WL supplied to the select gates SGD_SEL and SGD_USEL, and the word lines WL and the dummy word lines WLD located below the select gates SGD_SEL and SGD_USEL when data is written to the memory cell MC. It is noted that the same bias V WLD is supplied to the dummy word lines WLD 0 and WLD 1 . In the following description, the dummy word lines WLD 0 and WLD 1 are collectively expressed as “dummy word lines WLD”. FIG. 4A also illustrates a bias V BL supplied to unselected bit lines BL_USEL.

As shown in FIGS. 4A and 4B , from time t 0 to t 1 , a bias V PC is supplied to the select gates SGD_SEL and SGD_USEL. The select transistors STD are thereby turned on. On the other hand, a bias V DD is supplied to the bit lines BL_USEL. A bias of the selected bit line BL (not shown) is 0 V. At this time, the source-side select transistor STS is turned off. As a result, the semiconductor pillars SP connected to the unselected bit lines BL_USEL charge-up to a potential V DD .

It means herein that the selected bit line BL is the bit line BL connected to the semiconductor pillar SP that includes the memory cell MC to which data is to be written, while the unselected bit lines BL_USEL are the bit lines BL connected to the semiconductor pillars SP that do not include the memory cell MC to which data is to be written. The same thing is true for other elements.

At the time t 1 , supply of the bias V PC to the select gates SGD_SEL and SGD_USEL is stopped. Owing to this, the bias V SGD of each of the select gates SGD_SEL and SGD_USEL decreases at an attenuation factor determined by a time constant CR resulting from a parasitic resistance and a parasitic capacitance of the select gate SGD_SEL or SGD_USEL.

As shown in FIGS. 4A and 4B , the potential V SGD of the select gates SGD_SEL and SGD_USEL decreases on a near side NS closer to the drive circuit GD 1 and becomes 0 Vat, for example, time t 2 . On the other hand, a decrease in the potential V SGD is slower on a far side FS of the string of select transistor STD far from the drive circuit GD 1 because of an increase in the time constant CR. For example, in some cases, the potential VSGD does not decrease down to 0 V within a data write cycle.

Next, as shown in FIG. 4A , at the time t 2 , a bias V SON is supplied to the select gate SGD_SEL. At this time, the potential of the selected bit line BL is 0 V and the selected cell transistor STD provided in the semiconductor pillar SP including the memory cell MC to which data is to be written is turned on. On the other hand, a bias V DD is supplied to the bit lines BL_USEL. Owing to this, the select transistor STD provided in the semiconductor pillars SP that do not include the memory cell MC to which data is to be written are turned off.

Moreover, a bias is not supplied to the select gate SGD_USEL shown in FIG. 4B from the drive circuit GD 1 and yet the potential of the bit lines BL_USEL is V DD ; thus, the select transistor STD including the select gate SGD_USEL is turned off. As a result, the select transistors STS and STD are turned off in the semiconductor pillars SP_USEL other than the semiconductor pillar SP_SEL including the memory cell MC to which data is to be written and the semiconductor pillars SP_USEL have a floating potential.

On the other hand, at the time t 2 , a bias V PASS is supplied to the word lines WL and the dummy word lines WLD. A channel of each memory cell MC is thereby turned on. Moreover, at time t 3 , a bias V PG is supplied to the selected word line WL_SEL. It is thereby possible to write data to the memory cell MC to which data is to be written.

On the other hand, potentials of the semiconductor pillars SP_USEL that do not include the memory cell MC to which data is to be written are boosted in response to the bias supplied to each word line WL; thus, a potential difference narrows between, for example, the semiconductor pillar SP_USEL and the word line WL_SEL to which the bias V PG is supplied. It is thereby possible to prevent data from being erroneously written to unselected memory cells MC.

It is noted that the write potential V PG is not supplied to the dummy word lines WLD 0 and WLD 1 . In other words, the drive circuit WD 1 that supplies the bias to each word line WL is configured to be able to supply the higher bias than the bias supplied by the drive circuit WD 2 to the dummy word lines WLD 0 and WLD 1 (refer to FIG. 3 ). The bias V PG exceeds, for example, 10 V. By contrast, the bias V PASS supplied to the dummy word lines WLD is, for example, a few volts.

FIGS. 5A and 5B are schematic diagrams illustrating operation of a memory device 2 according to a comparison. FIG. 5A is a schematic cross-sectional view illustrating a structure of the memory device 2 . FIG. 5B is a time chart illustrating the operation of the memory device 2 .

As shown in FIG. 5A , in the memory device 2 , the interlayer insulating film 15 is provided between the select gate SGD and the dummy word line WLD 0 . In other words, a thickness of the insulating film provided between the select gate SGD and the dummy word line WLD 0 in the Z direction is generally identical to the thickness of the interlayer insulating films 15 provided between the word lines WL in the Z direction.

As shown in FIG. 5B , the bias V PC is supplied to the select gate SGD_USEL when data is written to one memory cell MC, and supply of the bias V PC is stopped at the time t 1 . Subsequently, the potential of the select gate SGD_USEL gradually decreases.

Next, at the time t 2 , the bias V PASS is supplied to the word lines WL and the dummy word lines WLD. At this time, an induced potential V CP is induced to the select gate SGD_USEL by coupling via a parasitic capacitance Cp between the select gate SGD_USEL and the dummy word line WLD; thus, the potential of the select gate SGD_USEL increases.

For example, on the far side FS of the select transistor STD far from the drive circuit GD 1 , the potential of the select gate SGD_USEL does not completely decrease from V PC and the induced potential V CP is superimposed on the potential. Owing to this, portions of the select transistors STD are turned on, which often causes suppression of boosting of the potentials in the semiconductor pillars SP. As a result, a malfunction possibly occurs that data is written to the unselected memory cells MC.

In the memory device 1 according to the present embodiment, by contrast, the interlayer insulating film 15 M is provided between the select gate SGD and the dummy word line WLD 0 . The interlayer insulating film 15 M is formed thicker than the interlayer insulating films 15 provided between the word lines WL in the Z direction. Owing to this, the parasitic capacitance Cp between the select gate SGD and the dummy word line WLD 0 is decreased, and thus, parasitic coupling is prevented. It is thereby possible to prevent data from being erroneously written to the unselected memory cells MC.

A method of manufacturing the memory device 1 according to the embodiment will next be described with reference to FIGS. 6A to 9B . FIGS. 6A to 9B are schematic cross-sectional views illustrating procedures of manufacturing the memory device 1 .

As shown in FIG. 6A , the interlayer insulating films 13 , 15 , and 17 and sacrificial films 23 are stacked on the conductive layer CL. A sacrificial film 23 is provided between each two interlayer insulating films 13 , 15 , and 17 adjacent to each other in the Z direction. The interlayer insulating film 13 is provided between the conductive layer CL and the lowermost sacrificial film 23 among the plurality of sacrificial films 23 . The interlayer insulating film 17 is provided on the uppermost sacrificial film 23 among the plurality of sacrificial films 23 . The interlayer insulating films 13 , 15 , and 17 are, for example, silicon oxide films. The sacrificial films 23 are, for example, silicon nitride films.

For example, the interlayer insulating films 15 include the interlayer insulating film 15 M. The interlayer insulating film 15 M is formed so that the thickness T 1 thereof in the Z direction is larger than the thickness T 2 of the other interlayer insulating films 15 in the Z direction. The thickness T 1 is, for example, 1.5 to 3.0 times as large as the thickness T 2 .

As shown in FIG. 6B , a memory hole MH having a depth extending from an upper surface of the interlayer insulating film 17 to the conductive layer CL is formed. The memory hole MH is formed to have, for example, a circular, elliptical, or polygonal opening on the upper surface of the interlayer insulating film 17 .

Subsequently, the semiconductor layer SC is formed on a bottom portion of the memory hole MH. For example, the conductive layer CL is a silicon layer. The semiconductor layer SC is a polysilicon layer using, for example, CVD (Chemical Vapor Deposition), and is formed so as not to be deposited on the interlayer insulating films 13 , 15 , and 17 exposed to a side wall of the memory hole MH, but to be selectively deposited on the conductive layer CL. In addition, the semiconductor layer SC is formed so that an upper surface TSS thereof is located, for example, on a level between the lowermost sacrificial film 23 and the sacrificial film 23 located over the lowermost sacrificial film 23 .

As shown in FIG. 7A , the memory film MF and a semiconductor film SF 1 are formed within the memory hole MH. The memory film MF has a stacked structure shown in, for example, FIG. 2 . The memory film MF is formed in contact with an upper surface of the semiconductor layer SC on a bottom surface of the memory hole MH. The semiconductor film SF 1 is, for example, an amorphous silicon film. The memory film MF and the semiconductor film SF 1 are formed to have thicknesses such that a space remains within the memory hole MH.

As shown in FIG. 7B , a semiconductor film SF 2 that covers an inner surface of the memory hole MH is formed. Prior thereto, part of the semiconductor film SF 1 and part of the memory film MF stacked on the bottom surface of the memory hole MH are selectively removed by, for example, anisotropic RIE (Reactive Ion Etching). During this etching, the semiconductor film SF 1 protects the memory film MF remaining on the inner wall of the memory hole MH from being removed by etching.

Subsequently, a semiconductor film SF 2 that covers the inner surface of the memory hole MH is formed. The semiconductor film SF 2 is, for example, an amorphous silicon film and formed to have a thickness such that a space remains within the memory hole MH. Moreover, the semiconductor films SF 1 and SF 2 are crystallized by a heat treatment, thereby forming the semiconductor film SF. The resulting semiconductor film SF is, for example, a polysilicon film.

As shown in FIG. 8A , an insulator is buried within the memory hole MH to form the insulating core IC. The insulating core IC is, for example, silicon oxide formed by the CVD. Next, a slit ST is formed to divide the interlayer insulating films 13 , 15 , and 17 , and the sacrificial films 23 and it extends to the conductive layer CL. The slit ST has a thickness, for example, from the upper surface of the interlayer insulating film 17 to the conductive layer CL and extends in the Y direction.

As shown in FIG. 8B , the sacrificial films 23 are selectively removed via the slit ST. The sacrificial films 23 are removed by, for example, wet etching which leaves the interlayer insulating films 13 , 15 , and 17 unremoved. At this time, the memory film MF, the semiconductor film SF, and the insulating core IC formed within the memory hole MH support the interlayer insulating films 13 , 15 and 17 and spaces 23 S are maintained after removal of the sacrificial films 23 .

As shown in FIG. 9A , the insulating film 25 is formed on a surface of the semiconductor layer SC via the slit ST and the spaces 23 S. The insulating film 25 is, for example, a silicon oxide film formed by subjecting the semiconductor layer SC to thermal oxidation.

Subsequently, barrier metal layers BML and core metal layers MLC are formed within the spaces 23 S. The barrier metal layers BML contain, for example, titanium nitride (TiN). In addition, the core metal layers MLC contain, for example, tungsten (W). The barrier metal layers BML and the core metal layers MLC are deposited by, for example, using the CVD method via the slit ST.

As shown in FIG. 9B , the connection conductor LI and an insulating film 27 are formed within the slit ST. Specifically, the barrier metal layer BML and the core metal layer MLC that cover an inner surface of the slit ST are removed by, for example, using isotropic dry etching thereof, and the insulating film 27 that covers the inner surface of the slit ST is then formed. Moreover, N-type impurity ions are implanted into the conductive layer CL via the slit ST to form a contact region LCR. Next, the part of the insulating film 27 that covers a bottom surface of the slit ST is selectively removed, and the barrier metal layer BML that covers the inner surface of the slit ST and the core metal layer MLC filling the remaining portion of the interior of the slit ST are then formed. It is thereby possible to form the connection conductor LI within the slit ST.

Subsequently, interlayer insulating films 19 and 21 , the connection plugs CH and V 1 , and the bit lines BL are formed on the interlayer insulating film 17 ; thus, the memory cell array is completed.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.