Reconfigurable circuit and the method for using the same

This application is a National Stage Entry of PCT/JP2017/014403 filed on Apr. 6, 2017, which claims priority from International Patent Application PCT/JP2016/002358 filed on May 13, 2016, the contents of all of which are incorporated herein by reference, in their entirety.

The present invention relates to a reconfigurable circuit with non-volatile resistive switches, and the method for using the reconfigurable circuit.

A typical semiconductor integrated circuit (IC) is constructed by transistors which is built on a semiconductor substrate and upper layer wires which is used to connect the transistors. The patterns of the transistors and the wires are determined in a design stage of the IC. Interconnections between the transistors and the wires cannot be changed after the fabrication of IC. In order to improve flexibility of IC, field-programmable gate arrays (FPGAs) have been proposed and developed. In FPGAs, configuration data including operation and interconnection information is stored in memories, so that different logic operations and interconnections can be realized by configuring the memories after fabrication according to requirements of end users. Interconnections within FPGA can be altered by controlling ON-and-OFF states of switches in a routing multiplexer (MUX) or routing fabrics arranged in the FPGA in accordance with the interconnection information stored in the memories.

The relatively large energy consumption of FPGAs limits integration of commercial FPGAs into IoT (Internet of Things) devices. In most of commercial FPGAs, SRAM (Static Random Access Memory) is used to store the configuration data. Typically, each memory cell of SRAM is composed of six transistors and each modern FPGA chip has more than 10 M (ten-million) memory cells of SRAM. This causes extremely large area overhead, cost, and energy consumption in FPGAs. In this Description, FPGAs which use SRAM as memories storing configuration data are referred to as SRAM-based FPGAs or SRAM FPGAs.

Recently, FPGAs with non-volatile resistive switches (NVRSs) such as Nanobridge® (NB) integrated between the wires upon a transistor layer have been proposed to overcome the problems of SRAM-based FPGAs and achieve small area overhead [NPL 1, NPL 2]. FPGAs with NBs are referred to as NBFPGAs (Nanobridge® field programmable gate arrays). Non-volatility of NBs also contributes to zero standby power consumption. An example of NVRS which can applied to a memory portion of LSI (Large-Scale Integration) is disclosed in [PTL 1]. An example of structure of the NVRS and the method of writing data in the NVRS is disclosed in [PTL 2].

FIG. 1 illustrates a typical configuration of NBFPGA. A large number of cells 101 constitute a cell array of NBFPGA. Each cell 101 includes routing MUX 102 and logic block 103 . In this example, logic block 103 includes two look-up tables (LUTs) 104 , two D-type flip-flops 105 and two selectors 106 . Routing MUX 102 includes a plurality of input and output lines arranged in a lattice manner which are connected to logic block 103 and adjacent cells 101 . Data routing switch 107 is arranged at each cross-point or intersection between the input lines and the output lines. Therefore, routing MUX 102 has a crossbar structure. In FIG. 1 , enlarged view 110 illustrates four data routing switches 107 or NBs which are arranged at cross-points between input lines IN 0 , IN 1 and output lines OUT 0 , OUT 1 . Each data routing switch 107 is composed of two NVRSs S 101 , S 102 serially connected with each other. One NVRS S 101 is coupled to the input line and the other NVRS S 102 is coupled to the output line. When both NVRSs S 101 , S 102 in one switch 107 of the crossbar are in ON-state or set state in which NVRS has lower resistance, switch 107 electrically connects the input line to the output line. A signal can be transmitted from the input line to the output line. On the other hand, both NVRSs S 101 , S 102 in switch 107 are in OFF-state or reset state in which NVRS has higher resistance, switch 107 does not electrically connect the input line to the output line. No signal can transmit from the input line to the output line. Two NVRSs S 101 , S 102 constituting each switch 107 are used for only data routing in NBFPGA.

Patent Literature

PTL 1: WO 2015/198573 A1

PTL 2: JP 2013-77681A

PTL 3: U.S. Pat. No. 7,486,111 B2

Non Patent Literature

NPL 1: Munehiro Tada, et al., Improved OFF-State Reliability of Nonvolatile Resistive Switch with Low Programming Voltage, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 59, No. 9, pp. 2357-2362, September 2012.

NPL 2: Makoto Miyamura, et al., Low-power programmable-logic cell arrays using nonvolatile complementary atom switch, ISQED 2014, pp. 330-334.

NPL 3: Xu Bai et al., Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics, FPGA 2015, pp. 269.

Technical Problem

In NBFPGA, a NB crossbar requires more than 60% of the total area of the NBFPGA and this somewhat impairs flexibility of NBFPGA. The relatively low flexibility of NBFPGA still limits its wide applications.

An exemplary object of the present invention is to provide a reconfigurable circuit which has flexibility higher than NBFPGA and can function as both an FPGA and a memory.

Another exemplary object of the present invention is to provide a method for using a reconfigurable circuit which can function as both an FPGA and a memory.

Solution to Problem

According to an exemplary aspect of the present invention, a reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line, the resistive switch assembly including a first NRVS (non-volatile resistive switch) and a second NVRS whose first end is coupled to a first end of the first NVRS, wherein a second end of the first NVRS is coupled to the first line, and a second end of the second NVRS is coupled to the second line.

According to another exemplary aspect of the present invention, provided is a method for using reconfigurable circuit comprising a first line, a second line, and a resistive switch assembly disposed between the first line and the second line, wherein the resistive switch assembly includes a first NVRS and a second NVRS whose first end is coupled to a first end of the first NVRS, a second end of the first NVRS is coupled to the first line, and a second end of the second NVRS is coupled the second line. The method includes: using the first NVRS and the second NVRS as a data routing switch between the first line and the second line, by selectively making one of a first state in which the first NVRS and the second NVRS are in ON-state, and a second state in which the first NVRS and the second NVRS are in OFF-state; and using the first NVRS and the second NVRS as a memory element, by making one of the first NVRS and the second NVRS the ON-state and the other the OFF-state.

FIG. 1 is a schematic view illustrating an exemplary structure of NBFPGA.

FIGS. 2A and 2B is circuit diagrams illustrating a reconfigurable circuit according to a first exemplary embodiment of the present invention.

FIGS. 3A to 3D are circuit diagrams illustrating an example of operation of the reconfigurable circuit.

FIG. 4 is a graph showing energy efficiency and flexibility of various semiconductor devices.

FIG. 5 shows sectional views of an example of a non-volatile resistive element.

FIG. 6 is a circuit diagram illustrating another reconfigurable circuit according to the first exemplary embodiment.

FIG. 7A to 7D are timing charts showing programming of the reconfigurable circuit shown in FIG. 6 .

FIG. 8 is a circuit diagram illustrating a reconfigurable circuit according to a second exemplary embodiment.

FIGS. 9A and 9B are circuit diagrams illustrating an example of operation of the reconfigurable circuit shown in FIG. 8 .

FIG. 10 is a circuit diagram of a reconfigurable circuit with a program circuit.

FIG. 11 is a circuit diagram of a reconfigurable circuit with a program circuit and a serial read circuit.

FIG. 12 is a circuit diagram of a reconfigurable circuit with a program circuit and a parallel read circuit.

FIG. 13 is a circuit diagram illustrating a reconfigurable circuit according to a third exemplary embodiment.

FIGS. 14A and 14B are views explaining flexible configuration of NBPLMD (Nanobridge® programmable logic memory device) according to a fourth exemplary embodiment.

FIG. 15 is a circuit diagram illustrating a cell of NBPLMD.

FIG. 16 is a circuit diagram illustrating a reconfigurable circuit according to a fifth exemplary embodiment.

Exemplary embodiments of the present invention will be next described with reference to the accompanying drawings.

First Exemplary Embodiment

FIG. 2A illustrates a fundamental configuration of a reconfigurable circuit according to a first exemplary embodiment of the present invention. The reconfigurable circuit includes: first line L 1 ; first switch element SW 1 disposed between first line L 1 and a first power source line of voltage V 1 ; second line L 2 ; second switch element SW 2 disposed between second line L 2 and a second power source line of voltage V 2 ; and resistive switch assembly 111 disposed between first line L 1 and second line L 2 . The voltages V 1 and V 2 are different from each other. Resistive switch assembly 111 includes: first NVRS (non-volatile resistive switch) S 111 ; and second NVRS S 112 whose first end is coupled to the first end of the first NVRS S 111 . The second end of first NVRS S 111 is coupled to first line L 1 , and the second end of second NVRS S 112 is coupled to second line L 2 . In order to explain the operation of the reconfigurable circuit of the present exemplary embodiment, we introduce three terminals T 1 to T 3 to the circuit as shown in FIG. 2B . Terminals T 1 , T 2 are arranged at ends of first line L 1 and second line L 2 , respectively. Terminal T 3 is connected to the coupling part or node between first NVRS S 111 and second NVRS S 112 . NVRSs S 111 , S 112 can be separately and arbitrarily programmed to ON-state, i.e., lower resistance state, or OFF-state, i.e., higher resistance state, by applying control voltages among first line L 1 , second line L 2 , and the coupling part. Node N 1 separated from both NVRSs S 111 , S 112 may be provided as the coupling part of the first end of first NVRS S 111 and the first end of second NVRS S 112 . Alternatively, a portion of one of first NVRS S 111 and second NVRS S 112 may function as the coupling part.

In one example of the present exemplary embodiment, switch elements SW 1 , SW 2 may be MOS (metal-oxide-semiconductor) transistors, transmission gates, or other controllable devices. Voltages V 1 , V 2 may be power source voltage VDD and ground potential GND, respectively. Alternatively, voltages V 1 , V 2 may be ground potential GND and power source voltage VDD, respectively.

In the reconfigurable circuit shown in FIG. 2A , resistive switch assembly 111 in which two NVRSs S 111 , S 112 are serially connected via the node is disposed between first line L 1 and second line L 2 . Therefore, resistive switch assembly 111 may constitute an one-input-two-output NB (Nanobridge®). The reconfigurable circuit of the present exemplary embodiment uses the NB to implement both a data routing switch and a memory cell. The data routing switch realized by the reconfigurable circuit may be used for path routing in FPGA (field programmable gate array). Here, a mode in which the reconfigure circuit is used as a data routing switch is called data routing mode, and another mode in which the circuit is used as a memory cell is called memory mode.

In the data routing mode, both switch elements SW 1 , SW 2 are turned off. NVRSs S 111 , S 112 are configured to control data routing between terminals T 1 , T 2 , i.e., between first line L 1 and second line L 2 . When enabling data routing between terminals T 1 , T 2 , both NVRSs S 111 , S 112 are programmed to or made ON-state. When disabling data routing between terminals T 1 , T 2 , both NVRSs S 111 , S 112 are made OFF-state. The two serially-connected NVRSs can contribute to low programming voltage and high OFF-state reliability, because voltage stress is divided into half for each NVRS [NPL 1, NPL 2].

In the memory mode, one of NVRSs S 111 , S 112 is made ON-state and the other OFF-state to store data. For example, if NVRS S 111 is turned on and NVRS S 112 is turned off, data “1” is stored. In read operation, both switch elements SW 1 , SW 2 are turned on to apply voltages V 1 , V 2 to lines L 1 , L 2 , respectively. As a result, memory output can be read from terminal T 3 . If the memory stores “1,” the voltage read out from terminal T 3 is a value close to voltage V 1 . When NVRS S 111 is turned off and NVRS S 112 is turned on, data “0” is stored and a voltage close to V 2 may be read out. Voltage stress on either NVRS S 111 or S 112 is twice larger than that in the data routing mode, however, extremely short read time makes no reliability problem happen.

FIGS. 3A to 3D illustrate an example of operation of the reconfigurable circuit of this exemplary embodiment. In FIGS. 3A to 3D , it is assumed that switch elements SW 1 , SW 2 are pMOS transistor M 1 and nMOS transistor M 2 , respectively, and voltages V 1 , V 2 are VDD and GND, respectively. Terminals T 1 , T 2 are input terminal IN and output terminal OUT for data routing, respectively. Terminal T 3 is memory output terminal M OUT . In the data routing mode, a cutoff voltage and ground potential are applied to the gates of pMOS transistor M 1 and nMOS transistor M 2 to turn off them. As shown in FIG. 3A , when both NVRSs S 111 and S 112 are turned on (i.e., in ON-state), a signal can transmit from terminal IN to terminal OUT through NVRSs S 111 , S 112 . As shown in FIG. 3B , when both NVRSs S 111 and S 112 are turned off (i.e., in OFF-state), the path from terminal IN to terminal OFF is cut off. In the memory mode, data “1” is stored by turning on NVRS S 111 and turning off NVRS S 112 , and data “0” is stored by turning off NVRS S 111 and turning on NVRS S 112 . When data is read out, both transistors M 1 , M 2 are turned on. FIG. 3C illustrates reading-out of data “1” in which a voltage close to VDD appears at terminal M OUT . FIG. 3D illustrates reading-out of data “0” in which a voltage close to GND appears at terminal M OUT .

As described above, the present exemplary embodiment provides a novel reconfigurable circuit to implement both FPGA and a non-volatile memory using a single device for flexibility improvement. We name the novel reconfigurable circuit NBPLMD (Nanobridge® programmable logic memory device). FIG. 4 illustrates relationship between energy efficiency and flexibility of various semiconductor devices. As shown in FIG. 4 , ASIC (Application Specific Integrated Circuit) has high energy efficiency and low flexibility while a CPU (Central Processing Unit) has low energy efficiency and high flexibility. SRAM FPGA has middle energy efficiency and middle flexibility. NBFPGA is an improved version in energy efficiency of SRAM FPGA. Our NBPLMD has flexibility higher than NBFPGA. Therefore, NBPLMD has well-balanced characteristics between energy efficiency and flexibility.

Next, NVRS which can be used in the reconfigurable circuit will be described. As described above, NVRS can be altered between ON-state (i.e., set state) and OFF-state (i.e., reset state). In FIG. 5 , two NVRSs 121 , 122 are illustrated, NVRS 121 is in OFF-state, and NVRS 122 is in ON-state. NVRS includes: active electrode 123 made of, for example, cupper (Cu); inert electrode 124 made of, for example, ruthenium (Ru); and solid-electrolyte 125 sandwiched between active electrode 123 and inert electrode 124 .

In the OFF-state, active electrode 123 and inert electrode 124 are electrically separated by solid-electrolyte 125 , and the electric resistance between active electrode 123 and inert electrode 124 is very high. When the voltage of inert electrode 124 is fixed to zero and a positive voltage higher than a threshold voltage is applied to active electrode 123 of NVRS 121 in the OFF-state, metal ions are attracted by the electric field and supplied to solid-electrolyte 125 . Then, metal bridge 126 is formed between active electrode 123 and inert electrode 124 , and both electrode 123 , 124 are electrically short-circuited by metal bridge 126 . The resistance between active electrode 123 and inert electrode 124 is remarkably reduced. This operation making the NVRS ON-state is referred to set operation. When the voltage of inert electrode 124 is fixed to zero and a negative voltage whose absolute value is larger than another threshold voltage is applied to active electrode 123 of NVRS 122 in the ON-state, metal ions in metal bridge 126 move in a direction of active electrode 123 , and metal bridge 126 then disappears. The resistance between active electrode 123 and inert electrode 124 increases and returns the initial value, i.e., the value at the OFF-state. This operation making the NVRS OFF-state is referred to reset operation. NVRS has high ON/OFF resistance ratio (typically, >10 5 ) between the ON- and OFF-states. Small area overhead and high logic density can be achieved by replacing CMOS (Complementary MOS) switch with NVRS.

Two NVRSs are serially connected to constitute resistive switch assembly 111 in the present exemplary embodiment. Since each NVRS has active electrode 123 and inert electrode 124 , there are four ways to serially connect two NVRSs. In order to improve reliability of the NVRSs, especially in the data routing mode, it preferable to connect the active electrodes of both NVRSs to each other, or connect the inert active electrodes of both NVRSs to each other. Two NVRSs in which the active electrodes of both NVRSs are connected to each other or the inert electrodes are connected to each other are called complementary NVRSs. When the inert electrodes of two NVRSs are connected each other, the two NVRSs can share a single inert electrode. In such a case, the coupling part of the two NVRSs is the shared inert electrode. Although the two NVRSs can similarly share a single active electrode, it is preferable to share the inert electrode in comparison with case of the shared active electrode from a viewpoint of compatibility with semiconductor fabrication processes.

FIG. 6 illustrates an example of the reconfiguration circuit with the shared inert electrode. Compared to the reconfigurable circuit shown in FIG. 2A , the reconfigurable circuit shown in FIG. 6 differs in that NVRSs S 111 , S 112 share inert electrode 124 , and that circuits for programming and reading NVRSs S 111 , S 112 are added. The program circuit is used both for programming the NVRSs for the data routing mode and for writing data to the NVRSs for the memory mode. As switch elements SW 1 , SW 2 , pMOS transistor M 1 and nMOS transistor M 2 are used, respectively. Memory enable signal M EN which is active during reading operation is supplied to the reconfigurable circuit and invertor INV generates reversed memory enable signal M EN * based on signal M EN . Shared inert electrode 124 functions as the coupling part between NVRSs S 111 , S 112 . Program drivers PX, PY are connected to lines L 1 , L 2 , respectively, and program driver C is connected to the coupling part of NVRSs S 111 , S 112 . The coupling part is also connected to memory output terminal M OUT through transmission gate TG to which signals M EN , M EN * are supplied. Transistors M 1 , M 2 are configured to turn on when memory enable signal M EN is asserted. Transmission gate TG is also turned on when memory enable signal M EN is asserted. The operation of the circuit shown in FIG. 6 in the data routing mode and the memory mode are the same as those of the circuit shown in FIG. 2A .

FIGS. 7A to 7D illustrate programing of NVRSs S 111 , S 112 in the reconfigurable circuit shown in FIG. 6 . Here, V SET is a voltage enough to change the state of NVRS from OFF-state to ON-state while V RESET is a voltage enough to change the state of NVRS from ON-state to OFF-state. It should be noted that application of voltage of V SET /2, i.e., half of V SET , does not cause the state change of NVRS, and application of V RESET /2 does not cause the change of NVRS. In order to simplify the programming operation, it is preferable that magnitude of V SET is equal to that of V RESET . Voltages V PX , V PY , V C are output voltages of program drivers PX, PY, C, respectively.

FIG. 7A illustrates the set operation for NVRS S 111 . In the initial stage, each of V PX , V PY , V C is maintained at level of V SET /2. Then, V C is changed to the ground potential GND and V PY is subsequently changed to V SET whereby the state of NVRS S 111 shifts into the ON-state. After the transition to the ON-state, V PY is changed back to V SET /2 and V C is subsequently changed to V SET /2. V PX is unchanged throughout the set operation of NVRS S 111 . FIG. 7B illustrates the set operation for NVRS S 112 . The set operation of NVRS S 112 is similar to the set operation of NVRS S 111 , but V PX is changed instead of V PY .

FIG. 7C illustrates the reset operation for NVRS S 111 . In the initial stage, each of V PX , V PY , V C is maintained at level of V RESET /2. Then, V c is changed to V RESET and V PY is subsequently changed to the ground potential GND whereby the state of NVRS S 111 shifts into the OFF-state. After the transition to the OFF-state, V PY is changed back to V RESET /2 and V C subsequently is changed to V RESET /2. V PX is unchanged throughout the reset operation of NVRS S 111 . FIG. 7D illustrates the reset operation for NVRS S 112 . The reset operation of NVRS S 112 is similar to the reset operation of NVRS S 111 , but V PX is changed instead of V PY .

Second Exemplary Embodiment

Next, applications of the above-mentioned reconfigurable circuit will be described. FIG. 8 illustrates the reconfigurable circuit according to the second exemplary embodiment in which a plurality of first lines and a plurality of second lines are arranged and the resistive switch assembly including two NVRSs serially connected to each other is disposed at each cross-point between the first lines and the second lines. In the drawing, the first lines extend in the vertical direction while the second lines extend in the horizontal direction. In the present embodiment too, each resistive switch assembly is a one-input-two-output NB (Nonobridge®) which is used both for a data routing switch between the first line and the second line, and for a memory cell. In FIG. 8 , different reference numerals are assigned to the NVRSs in different resistive switch arrays.

In the example shown in FIG. 8 , two first or vertical lines L V0 , L V1 and two second or horizontal lines L H0 , L H1 are arranged in a lattice manner and a resistive switch assembly or Nonobridge® is arranged at each cross-point between vertical lines L V0 , L V1 and horizontal lines L H0 , L H1 , thereby constituting a 2×2 NB crossbar. Total eight NVRSs S 1 to S 8 are contained in the circuit shown in FIG. 8 . Vertical lines L V0 , L V1 are coupled to power source line VDD via pMOS transistors M 11 , M 12 , respectively. Horizontal lines L H0 , L H1 are coupled to ground line GND via nMOS transistors M 21 , M 22 , respectively. The resistive switch array at the cross-point between lines L V1 and L H0 includes NVRSs S 1 and S 2 and the resistive switch array at the cross-point between lines L V0 and L H0 includes NVRSs S 3 and S 4 . Similarly, NVRSs S 5 and S 6 are arranged at the cross-point between lines L V0 and L H1 , and NVRSs S 7 and S 8 are arranged at the cross-point between lines L V1 and L H1 . NVRSs S 1 , S 3 , S 5 , S 7 are the first NVRSs, and NVRSs S 2 , S 4 , S 6 , S 8 are the second NVRSs. The NB crossbar shown in FIG. 8 can implement both a routing multiplexer (MUX) and a memory array and has different operational modes, i.e., data routing mode and memory mode. FIG. 9A and FIG. 9B illustrate the data routing mode and the memory mode of the circuit shown in FIG. 8 , respectively.

In the data routing mode, transistors M 11 , M 12 , M 21 , M 22 are cut off. It is assumed that ends of vertical lines L V0 , L V1 are input ends IN 0 , IN 1 , respectively, and ends of horizontal lines L H0 , L H1 are output ends OUT 1 , OUT 2 , respectively. As shown in FIG. 9A , to implement a data transfer path from IN 0 to OUT 0 and another data transfer path from IN 1 to OUT 1 , NVRSs S 3 , S 4 , S 7 , S 8 are made ON-state while the NVRSs S 1 , S 2 , S 5 , S 6 are made OFF-state. The two NVRSs at the same cross-point have the same ON/OFF state.

In memory mode, one of two NVRSs at each cross-point is made ON-state and the other OFF-state to store logic value “1” or “0.” In the example illustrated in FIG. 9B , NVRSs S 1 , S 2 are made ON and OFF, respectively, to store logic value “1.” NVRSs S 3 , S 4 are made OFF and ON, respectively, to store logic value “0.” NVRSs S 5 , S 6 are similarly configured to store logic value “1” and NVRSs S 7 , S 8 are configured to store logic value “0.” When the stored values of the memory array are read, transistors M 11 , M 12 , M 21 , M 22 are turned on. Then, the voltage of terminal T 3 which is connected to the coupling part between the two NVRSs at each cross-point indicates the stored logic value. In this case, when the stored value is “0,” the voltage of terminal T 3 approaches to GND while the voltage of terminal T 3 approached to VDD when the stored value is “1.”

Programming of NVRSs in the reconfigurable circuit shown in FIG. 8 will be described. FIG. 10 illustrates a 2×2 NB crossbar in the related art which has only data routing function [NPL 2, PTL 1]. The circuit shown in FIG. 10 is equipped with a program circuit. Portions of the program circuit are surrounded by dashed lines in the drawing. Although the program circuit is used for separately programming NVRSs, the circuit shown in FIG. 10 does not implement a memory array. A control transistor is provided for each cross-point between the vertical lines and the horizontal lines. The source of the control transistor is connected to the coupling part between the two NVRSs at the same cross-point. In FIG. 10 , nMOS transistors Tr 4 to Tr 7 are the control transistors at the respective cross-points. Diodes or the like may be used instead of the control transistors. Vertical lines L V0 , L V1 are coupled to an output of a common column program driver PY via nMOS transistors Tr 0 , Tr 1 , respectively, and horizontal lines L H0 , L H1 are coupled to an output of common row program driver PX via nMOS transistors Tr 2 , Tr 3 , respectively. The line connecting the output of column program driver PY to nMOS transistors Tr 0 , Tr 1 is column program line L PY , and the line connecting the output of row program driver PX to nMOS transistors Tr 2 , Tr 3 is row program line L PX . The drains of the control transistors on the same column are connected with each other, and then coupled to common mid program driver C via one of nMOS transistors Tr 8 , Tr 9 which are provided for the respective columns. The line connecting the output of mid program driver C to nMOS transistors Tr 8 , Tr 9 is mid program line L C . Row address signals X 0 , X 1 and column address signals Y 0 , Y 1 control nMOS transistors Tr 0 to Tr 9 for configuration of the NB crossbar.

In order to realize the novel NB crossbar according to the second exemplary embodiment, which has both data routing function and memory function, we can add read circuits to the circuit of the related art shown in FIG. 10 . FIG. 11 illustrates the reconfigurable circuit, i.e., NB crossbar, according to the second exemplary embodiment with a serial read circuit and the program circuit. The portions of the serial read circuit are surrounded by dashed-and-dotted lines while the portions of the program circuit are surrounded by dashed lines in the drawing.

In the example shown in FIG. 11 , memory enable signal M EN , which is in High level when asserted, is supplied to the read circuit, and its inverse signal M EN * is generated by inverter INV. Power supply voltage VDD is applied to column program line L PY via pMOS transistor Tr 11 which is controlled by signal M EN *. Ground potential GND is applied to row program line L PX via nMOS transistor Tr 12 which is controlled by signal M EN . Since the memory value is read from the coupling part of the two NVRSs of the same cross-point, the memory value is transferred to mid program line L C via the corresponding control transistor and one of nMOS transistors Tr 8 , Tr 9 . In order to supply the memory value to an external circuit, the mid program line is connected to buffer BUF via transmission gate TG controlled by signals M EN , M EN *. The output of buffer BUF is connected to memory output terminal M OUT .

For example, when data stored in the NVRSs at the cross-point of vertical line L V0 and horizontal line L H0 is read, it is necessary to set signal M EN as High, addresses X 0 , Y 0 as High, and addresses X 1 , Y 1 as low. Transistor Tr 0 is turned on to apply power supply voltage VDD to vertical line L V0 , and transistor Tr 2 is turned on to apply ground potential GND to horizontal line L H0 . Transistors Tr 4 , Tr 8 are then turned on to output the data stored in the NVRSs at the target cross-point.

Ten transistors Tr 0 to Tr 9 constitute the program circuit shown in FIG. 11 and these transistors Tr 0 to Tr 9 also engage in the read operation. Additional components for the serial read circuit is only two transistors Tr 11 , Tr 12 , one invertor INV, one transmission gate TG and one buffer BUF. This leads to very small area overhead of the novel NB crossbar with both routing switch function and memory function compared with the NB crossbar of the related art which has only the routing switch function.

The NB crossbar shown in FIG. 11 includes the serial read circuit. When a high memory read rate is required, the serial read circuit can be replaced with a parallel read circuit. FIG. 12 illustrates a reconfigurable circuit with a program circuit and a parallel read circuit which is modification of the circuit shown in FIG. 11 . The circuit shown in FIG. 12 is different from the circuit shown in FIG. 11 only in a parallel read circuit is used instead of the serial read circuit. The portions of the parallel read circuit are surrounded by dashed-and-dotted lines in FIG. 12 .

In the parallel read circuit, invertor INV reverses memory enable signal M EN to generate signal M EN *. Vertical lines L V0 , L V1 are connected to power source line VDD via pMOS transistors Tr 20 , Tr 21 , respectively. Transistors Tr 20 , Tr 21 are controlled by signal M EN *. Ground potential GND is applied to row program line L PX via nMOS transistor Tr 12 controlled by signal M EN . Transmission gates TG 0 , TG 1 are provided for the respective columns. The drains of the control transistors on the same column are connected with each other, and then coupled to the corresponding one of transmission gates TG 0 , TG 1 . Each of transmission gates TG 0 , TG 1 is controlled by signals M EN , M EN *. The outputs of transmission gates TG 0 , TG 1 are connected memory output terminals M OUT0 , M OUT1 via buffers BUF 0 , BUF 1 , respectively.

The circuit shown in FIG. 12 can read memory cells on the same row at the same time. When parallel reading is carried out, power source voltage VDD is applied, without using transistor Tr 0 , Tr 1 , to vertical lines L V0 , L V1 via transistors Tr 20 , Tr 21 controlled by signal M EN *. The memory data is supplied to the transmission gates and buffers for parallel read without using transistors Tr 8 , Tr 9 . For example, if the data stored in the NVRSs at the cross-point of vertical line L V0 and horizontal line L H0 and another data stored at the cross-point of vertical lines L V1 and horizontal line L H0 are read simultaneously, it is necessary to set signal M EN as High, address Y 0 as High, and address Y 1 as low. Signal M EN at High causes voltage VDD to be supplied to both vertical lines L V0 , L V1 . Ground potential GND is supplied to horizontal line L H0 because transistor Tr 2 is turned on by address Y 0 . Transistors Tr 4 , Tr 5 are turned on by address Y 0 , so that memory data corresponding to the cross-point of lines L V0 , L H0 and another data corresponding to the cross-point of lines L V1 , L H0 can be read to memory output terminals M OUT0 , M OUT1 , simultaneously. Thus, data stored in the row corresponding to horizontal line L H0 have been read out in parallel.

In the examples described above, two vertical lines L V0 , L V1 and two horizontal lines L H0 , L H1 are arranged to constitute a crossbar. However, each of the number of the vertical lines and the number of horizontal lines is not limited to two. Three or more vertical lines can be arranged and three or more horizontal lines can be arranged. The larger scale of the lattice structure of the vertical lines and the horizontal lines further improves flexibility of the reconfigurable circuit.

Third Exemplary Embodiment

The reconfigurable circuit based on the present invention can be also applied to time-multiplexed crossbar or interconnect structures, such as proposed in [PTL 3], in which a plurality of switches are arranged at each of cross-points between horizontal lines and vertical lines and the switches are selected in time-divisional manner such that two or more switches are not simultaneously selected. The time-multiplexed crossbar achieves time-divisional changeover of contexts in FPGA. The selection of the switches is performed by using a pass transistor interposed in each switch. Time control signals are applied to the respective pass transistors at each cross-point. Since the selection using the pass transistors can be rapidly executed, the time-multiplex crossbar configuration provides runtime-changeable data signal routing which improves flexibility of FPGA.

FIG. 13 illustrates an example of a reconfigurable circuit according to a third exemplary embodiment in which a plurality of resistive switch assemblies each comprising two NVRSs serially-connected to each other are arranged at each cross-points between the vertical lines and the horizontal lines. The example shown in FIG. 13 is a modification of the circuit shown in FIG. 12 and is thus equipped with two resistive switch assemblies at each cross-point between two vertical lines L V0 , L V1 and two horizontal lines L H0 , L H1 . However, three or more vertical lines and three or more horizontal lines can be arranged. In addition, although two resistive switch assemblies are arranged at each cross-point, the number of resistive switch assemblies per cross-point between the first lines, i.e., the vertical lines, and the second lines, i.e., the second lines, can be three or more. The multiplicity of contexts which are switched in a time-divisional manner increases as the number of resistive switch assemblies per cross-point increases.

A pass transistor is arranged in each of the resistive switch assemblies such that the pass transistor can interrupt the current flowing through the serially-connected two NVRSs in the resistive switch assembly. In FIG. 13 , two resistive switch assemblies are arranged at the cross-point of vertical line L V1 and horizontal line L H0 , the first assembly including two NVRSs S 1 a , S 2 a and pass transistor Tr 15 a , and the second assembly including two NVRSs S 1 b , S 2 b and pass transistor Tr 15 b . In the first resistive switch assembly, the second ends of NVRSs S 1 a , S 1 b are connected to lines L V1 , L H0 , respectively, and pass transistor Tr 15 a which is an nMOS transistor is inserted between the first ends of NVRSs S 1 a , S 2 a . The source of control transistor Tr 5 a is connected to the junction between first end of NVRS S 2 a and pass transistor Tr 15 a . Similarly, in the second resistive switch assembly, the second ends of NVRSs S 1 b , S 2 b are connected to lines L V1 , L H0 , respectively, and pass transistor Tr 15 b is inserted between the first ends of NVRSs S 1 b , S 2 b . Control transistor Tr 5 b is connected to the junction between first end of NVRS S 2 b and pass transistor Tr 15 b . The drains of control transistors Tr 5 a , Tr 5 b are commonly connected to the drains of the other control transistors Tr 7 a , Tr 7 b in the same column, and then connected to transistor Tr 9 which is controlled by address X 1 .

Similarly, NVRSs S 3 a , S 3 b , S 4 a , S 4 b , control transistors Tr 4 a , Tr 4 b and pass transistors Tr 14 a , Tr 14 b are arranged for the cross-point between lines L V0 and L H0 . NVRSs S 5 a , S 5 b , S 6 a , S 6 b , control transistors Tr 6 a , Tr 6 b and pass transistors Tr 16 a , Tr 16 b are arranged for the cross-point between lines L V0 and L H1 . NVRSs S 7 a , S 7 b , S 8 a , S 8 b , control transistors Tr 7 a , Tr 7 b and pass transistors Tr 17 a , Tr 17 b are arranged for the cross-point between lines L V1 and L H1 .

Two time control signals CS 1 , CS 2 are supplied to the reconfigurable circuit. Signal CS 1 is applied to the gates of pass transistors Tr 14 a , Tr 15 a , Tr 16 a , Tr 17 a which are included in the first resistive switch assemblies at the respective cross-points. Signal CS 2 is applied to the gates of pass transistors Tr 14 b , Tr 15 b , Tr 16 b , Tr 17 b which are included in the second resistive switch assemblies at the respective cross-points. In addition, AND gate A 10 receives time control signal CS 1 and address Y 0 , and the output of AND gate A 10 is supplied to the gates of controls transistors Tr 4 a , Tr 5 a in the first resistive assemblies on horizontal line V H0 . Similarly, AND gate A 20 receives time control signal CS 2 and address Y 0 , and the output of AND gate A 20 is supplied to the gates of controls transistors Tr 4 b , Tr 5 b in the second resistive assemblies on horizontal line V H0 . With regard to vertical line V H1 , two AND gates A 11 , A 21 are similarly provided and their outputs are supplied to the gates of control transistors Tr 6 a , Tr 7 a , Tr 6 b , Tr 7 b.

Although the pass transistor is inserted between the first ends of the first NVRS and the second NVRS for each cross-point in the example shown in FIG. 13 , the position of the pass transistor is not limited to this. The pass transistor can be disposed at an arbitrary position between the coupling position of the first NVRS to the first line and the coupling position of the second NVRS to the second line. For example, in the case of the cross-point of vertical line L V1 and horizontal line L H0 shown in FIG. 13 , pass transistor Tr 15 a may be inserted between vertical line L V1 and the second end of NVRS S 1 a . Alternatively, pass transistor Tr 15 a may be inserted between horizontal line L H0 and the second end of NVRS S 2 a.

The operation of the reconfigurable circuit shown in FIG. 13 is the same as that of the circuit shown in FIG. 12 except for selection of one of two resistive switch assemblies at each cross-point by means of time control signals CS 1 , CS 2 . When the first resistive switch assemblies or NBs are used for data routing switches or memory cells, time control signal CS 1 is activated while time control signal CS 2 is kept inactive. On the other hand, if the second resistive switch assemblies are used for data routing switches or memory cells, time control signal CS 2 is activated while time control signal CS 1 is kept inactive. The programming operation to the NVRSs is also carried out by activating one of time control signals CS 1 , CS 2 .

Fourth Exemplary Embodiment

Next, a fourth exemplary embodiment according to the present invention will be explained. As described above, the reconfigurable circuits of the above exemplary embodiments are called as NBPLMD. The present exemplary embodiment explains how to use the novel NBPLMD. FIGS. 14A and 14B illustrate usage of the novel NBPLMD. The NBPLMD has the same structure as the previous NBFPGA shown in FIG. 1 , but with the novel NB crossbar which can be used for both a data routing switch and a memory, as disclosed in the above exemplary embodiments. As shown in FIG. 14A , there are three kinds of usage for the NBPLMD. The first one is that the NBPLMD is configured as a complete NBFPGA if a large-sized application is mapped on the NBPLMD. The second one is that the NBPLMD is configured as a complete memory if only data storage is necessary. The third one is that one part of the NBPLMD is configured as NBFPGA and the other part is configured as a memory if both application and memory are necessary simultaneously. The example shown in FIG. 14B illustrates the case where an application can be realized using 25% of the NBPLMD, the other 75% can be used as a programmable ROM (read only memory). The area ratio between the NBFPGA part and the memory part can be arbitrarily set between the ranges of 1:0 and 0:1. Since the data routing mode, i.e., NBFPGA mode, and the memory mode are different only in the state of memory enable signal M EN and data pattern written to the serially connected two NVRSs in each NB, the mode of NBPLMD can be dynamically change between the NBFPGA mode and the memory mode for each block in the NBPLMD during the operation of the NBPLMD.

FIG. 15 illustrates how a large size FPGA or memory can be provided by NBPLMD with a typical architecture. In this example, it is assumed that cluster size, segment length and segment lane are optimized to be 4 as introduced in [NPL 3], and a cell array of 64×64 cells are arranged in NBPLMD. Each cell has four look-up tables (LUTs), therefore totally 64×64×4=16384 LUTs are provided in the FPGA mode of the NBPLMD. As shown in FIG. 15 , each cell of NBPLMD has thirty-two (32) horizontal lines L H0 to L H31 and sixty-nine (69) vertical lines L V0 to L V68 , therefore a 32×69 NB crossbar is formed per cell. Each of vertical lines L V0 to L V68 is coupled to the first power source line of voltage V 1 through pMOS transistor M 1 which functions as the first switch element. Each of horizontal lines L H0 to L H31 is coupled to the second power source line of voltage V 2 through nMOS transistor M 2 which functions as the second switch element. A resistive switch array including NVRSs S 111 , S 112 and coupling terminal T 3 is arranged at each of cross-points between horizontal lines L H0 to L H31 and vertical lines L V0 to L V68 . In the memory mode, since 32×69×64×64=9,043,968, a 9-megabits memory is provided by the NBPLMD of the current example.

Fifth Exemplary Embodiment

Next, a fifth exemplary embodiment according to the present invention will be explained. As described in above exemplary embodiments, the area ratio between the NBFPGA part and the memory part in the NBPLMD can be arbitrarily set in a range between 1:0 and 0:1. In another word, there is a tradeoff between an NBFPGA area and a memory area in the NBPLMD. The present exemplary embodiment discloses how to break the tradeoff.

FIG. 16 illustrates a reconfigurable circuit according to the fifth exemplary embodiment. Four vertical lines L V0 to L V3 and four horizontal lines L H0 to L H3 are arranged in a lattice manner and a resistive switch assembly or Nanobridge® is arranged at each cross-point between vertical lines L V0 to L V3 and horizontal lines L H0 to L H3 , thereby constituting a 4×4 NB crossbar. Total 32 NVRSs S 11 to S 18 , S 21 to S 28 , S 31 to S 38 , S 31 to S 38 are contained in the circuit shown in FIG. 16 . For example, NVRSs S 11 , S 12 are arranged at the cross-point between vertical line L V3 and horizontal line L H0 and terminal T 3 is connected to the coupling part or node between first NVRS S 11 and second NVRS S 12 . Similarly to the NB crossbar disclosed in the second exemplary embodiment, vertical lines L V0 to L V3 are coupled to power source line VDD via pMOS transistors M 30 to M 33 , respectively. Horizontal lines L H0 to L H3 are coupled to ground line GND via nMOS transistors M 40 to M 43 , respectively. The NB crossbar of the present exemplary embodiment differs from the NB crossbar of the second exemplary embodiment in that vertical lines L V0 to L V3 are connected to input ends IN 0 to IN 3 via input control switches M 50 to M 53 , respectively. Horizontal lines L H0 to L H3 are directly connected to output ends OUT 0 to OUT 3 , respectively. Here, we use nMOS transistors for input control switches M 50 to M 53 as an example, the input control switches may be transmission gates, NVRSs or other controllable switches. Input enable signals EN 0 to EN 3 are applied to the gate terminals of the input control switch transistors M 51 to M 53 for ON/OFF control, respectively.

In case of implementing a data transfer path from input end IN 3 to output end OUT 2 , input control switch transistor M 53 , which corresponds to input end IN 3 , and NVRS S 31 , S 32 are made ON-state while remaining input control switch transistors M 50 , M 51 , M 53 and transistors M 33 , M 42 are made OFF-state. To achieve high reliability in the OFF-state, the other NVRSs S 11 , S 12 , S 21 , S 22 , S 33 to S 38 , S 41 , S 42 which are connected to vertical line L V3 or horizontal line L H2 are preferably made OFF-state, because when a signal is applied to input end IN 0 and propagates on vertical line L V3 and horizontal line L H2 , the applied signal causes voltage stress on the NVRSs and the transistors coupled to vertical line L V3 or horizontal line L H2 . Input control switches M 50 to M 52 which are in the OFF-state cut off input signals applied to input ends IN 0 to IN 2 so that the NVRSs S 13 to S 18 , S 23 to S 28 , S 43 to S 48 can be used as memory cells without reliability problem. Block 131 including NVRSs S 13 to S 18 , S 23 to S 28 constitutes six memory cells, and block 132 including NVRSs S 43 to S 48 constitutes three memory cells. Both memory cells and data routing switches can be implemented in the same NB crossbar. As a result, both memory and NBFPGA can be installed on the whole area of the NBPLMD.

Although, in the circuit shown in FIG. 15 , vertical lines L V0 to L V3 are coupled to input ends IN 0 to IN 3 via input control transistors M 50 to M 53 and horizontal lines L H0 to L H3 are coupled to output ends OUT 0 to OUT 3 , another configuration is possible in which the vertical lines are coupled to the output ends while horizontal lines are coupled to the input ends via the input control transistors. In the present exemplary embodiment, the number of the vertical lines is not limited to four and the number of the horizontal lines is not limited to four.

The reconfigurable circuits of the above exemplary embodiments may be used in, for example, mobile phones, IoT (Internet of Things) devices, and so on. A highly flexible PLMD (programmable logic memory device) can be realized by the reconfigurable circuits described above.

It is apparent that the present invention is not limited to the above exemplary embodiments and examples, but may be modified and changed without departing from the scope and sprit of the invention. The present application claims priority based on international application PCT/JP2016/002358 filed on May 13, 2016, all the disclosure of which is incorporated herein.

The whole or part of the exemplary embodiments disclosed above can be described as, but not limited to, the following supplementary notes.

(Supplementary Note 1)

A reconfigurable circuit comprising:

a first line;

a first switch element disposed between the first line and a first power source line of first voltage;

a second line;

a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and

a resistive switch assembly disposed between the first line and the second line, the resistive switch assembly including a first non-volatile resistive switch and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch,

wherein a second end of the first non-volatile resistive switch is coupled to the first line, and a second end of the second non-volatile resistive switch is coupled to the second line.

(Supplementary Note 2)

The reconfigurable circuit according to Supplementary Note 1, wherein one of the first voltage and the second voltage is a power supply voltage, and the other of the first voltage and the second voltage is ground potential.

(Supplementary Note 3)

The reconfigurable circuit according to Supplementary Note 1 or 2, wherein each of the first non-volatile resistive switch and the second non-volatile resistive switch comprises an active electrode, an inert electrode, and a solid-electrolyte sandwiched between the active electrode and the inert electrode.

(Supplementary Note 4)

The reconfigurable circuit according to Supplementary Note 3, wherein the active electrodes of the first non-volatile resistive switch and the second non-volatile resistive switch are coupled to each other, or the inert electrodes of the first non-volatile resistive switch and the second non-volatile resistive switch are coupled to each other.

(Supplementary Note 5)

The reconfigurable circuit according to any one of Supplementary Notes 1 to 4, wherein each of the first switch element and the second switch element comprises a MOS transistor.

(Supplementary Note 6)

The reconfigurable circuit according to any one of Supplementary Notes 1 to 5, wherein the first switch element and the second switch element are turned on in accordance with a memory enable signal.

(Supplementary Note 7)

The reconfigurable circuit according to any one of Supplementary Notes 1 to 6, wherein a value stored in the resistive switch array is read out from a coupling part of the first end of the first non-volatile resistive switch element and the first end of the second non-volatile resistive element.

(Supplementary Note 8)

The reconfigurable circuit according to any one of Supplementary Notes 1 to 6, further comprising:

a first program driver applying a first program voltage to the first line; a second program driver applying a second program voltage to the second line; and

a third program driver applying a third program voltage to a coupling part of the first ends of the first non-volatile resistive switch and the second non-volatile resistive switch.

(Supplementary Note 9)

The reconfigurable circuit according to Supplementary Note 8, wherein a value stored in the resistive switch array is read out from the coupling part.

(Supplementary Note 10)

The reconfigurable circuit according to any one of Supplementary Notes 1 to 9, wherein a plurality of the resistive switch assemblies are disposed between the first line and the second line, and a pass transistor is arranged in each of the plurality of the resistive switch assemblies such that the pass transistor is inserted in a section between a coupling position of the first non-volatile resistive switch to the first line and a coupling position of the second non-volatile resistive switch to the second line.

(Supplementary Note 11)

The reconfigurable circuit according to Supplementary Note 10, wherein a time control signal is applied to a gate of the pass transistor.

(Supplementary Note 12)

The reconfigurable circuit according to any one of Supplementary Notes 1 to 7, wherein

a plurality of first lines and a plurality of second lines are arranged, and

the resistive switch assembly is disposed at each of cross-points between the plurality of first lines and the plurality of second lines.

(Supplementary Note 13)

The reconfigurable circuit according to Supplementary Note 12, wherein the first switch element is provided for each of the plurality of the first lines and the second switch element is provided for each of the plurality of the second lines.

(Supplementary Note 14)

The reconfigurable circuit according to Supplementary Note 12 or 13, wherein a plurality of the resistive switch assemblies are disposed at each of the cross-points, and a pass transistor is arranged in each of the plurality of the resistive switch assemblies such that the pass transistor is inserted in a section between a coupling position of the first non-volatile resistive switch to the first line and a coupling position of the second non-volatile resistive switch to the second line.

(Supplementary Note 15)

The reconfigurable circuit according to Supplementary Note 14, wherein a time control signal is applied to a gate of the pass transistor.

(Supplementary Note 16)

The reconfigurable circuit according to any one of Supplementary Notes 1 to 15, further comprising:

a third switch element whose first end is coupled to one of the first line and the second line, a second end of the third switch element being used as an input end.

(Supplementary Note 17)

The reconfigurable circuit according to Supplementary Note 16, wherein the third switch element comprises a MOS transistor.

(Supplementary Note 18)

The reconfigurable circuit according to Supplementary Note 16 or 17, wherein the third switch element is turned on in accordance with an input enable signal.

(Supplementary Note 19)

A reconfigurable circuit comprising:

a plurality of first lines;

a plurality of first selection transistors respectively connected to the plurality of first lines and controlled by first address,

a plurality of second lines;

a plurality of second selection transistors respectively connected to the plurality of second lines and controlled by second address,

a resistive switch assembly disposed at each of cross-points between the plurality of first lines and the plurality of second lines, the resistive switch assembly including a first non-volatile resistive switch and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch,

a first switch element connecting at least one of the first lines to a first power source line of first voltage in response to a memory enable signal; and

a second switch element connecting at least one of the second lines to a second power source line of second voltage in response to the memory enable signal, the second voltage being different from the first voltage,

wherein, in each resistive switch assembly, a second end of the first non-volatile resistive switch is coupled to the first line, and a second end of the second non-volatile resistive switch is coupled to the second line.

(Supplementary Note 20)

The reconfigurable circuit according to Supplementary Note 19, further comprising:

a plurality of third lines respectively provided for the plurality of the first lines;

a control transistor provided for each cross-point, one end of the control transistor being connected to a coupling part of the first end of the first non-volatile resistive switch and the first end of the second non-volatile resistive switch, the other end of the control transistor being connected to one of the third lines corresponding to the each cross-point, an address signal of the second address corresponding to the each cross-point being applied to a gate of the control transistor;

a fourth line;

a plurality of third selection transistors respectively connecting the plurality of third lines to the fourth line;

a first program driver applying a first program voltage to the plurality of first lines through the plurality of first selection transistors;

a second program driver applying a second program voltage to the plurality of second lines through the plurality of second selection transistors; and

a third program driver applying a third program voltage to the fourth line.

(Supplementary Note 21)

The reconfigurable circuit according to Supplementary Note 20, wherein stored values associated with the cross-points are serially read through the fourth line in response to the memory enable signal.

(Supplementary Note 22)

The reconfigurable circuit according to Supplementary Note 20, wherein stored values associated with the cross-points are read in parallel through the plurality of the third lines in response to the memory enable signal.

(Supplementary Note 23)

The reconfigurable circuit according to any one of Supplementary Notes 19 to 22, wherein one of the first voltage and the second voltage is a power supply voltage, and the other of the first voltage and the second voltage is ground potential.

(Supplementary Note 24)

The reconfigurable circuit according to any one of Supplementary Notes 19 to 23, wherein each of the first non-volatile resistive switch and the second non-volatile resistive switch comprises an active electrode, an inert electrode, and a solid-electrolyte sandwiched between the active electrode and the inert electrode.

(Supplementary Note 25)

The reconfigurable circuit according to Supplementary Note 24, wherein the active electrodes of the first non-volatile resistive switch and the second non-volatile resistive switch are coupled to each other, or the inert electrodes of the first non-volatile resistive switch and the second non-volatile resistive switch are coupled to each other.

(Supplementary Note 26)

The reconfigurable circuit according to any one of Supplementary Notes 19 to 25, wherein each of the first switch element and the second switch element comprises a MOS transistor.

(Supplementary Note 27)

The reconfigurable circuit according to any one of Supplementary Notes 19 or 26, wherein a plurality of the resistive switch assemblies are disposed at each of the cross-points, and a pass transistor is arranged in each of the plurality of the resistive switch assemblies such that the pass transistor is inserted in a section between a coupling position of the first non-volatile resistive switch to the first line and a coupling position of the second non-volatile resistive switch to the second line.

(Supplementary Note 28)

The reconfigurable circuit according to Supplementary Note 27, wherein a time control signal is applied to a gate of the pass transistor.

(Supplementary Note 29)

The reconfigurable circuit according to any one of Supplementary Notes 19 to 28, further comprising:

a plurality of third switch elements whose first ends are coupled to the plurality of first lines, respectively,

wherein second ends of the third switch elements are used as input ends, and the plurality of second lines are coupled to output ends, respectively.

(Supplementary Note 30)

The reconfigurable circuit according to any one of Supplementary Notes 19 to 28, further comprising:

a plurality of third switch elements whose first ends are coupled to the plurality of second lines, respectively,

wherein second ends of the third switch elements are used as input ends, and the plurality of first lines are coupled to output ends, respectively.

(Supplementary Note 31)

The reconfigurable circuit according to Supplementary Note 29 or 30, wherein each of the third switch elements comprises a MOS transistor.

(Supplementary Note 32)

The reconfigurable circuit according to any one of Supplementary Notes 29 to 31, wherein the third switch elements are turned on in accordance with an input enable signal.

(Supplementary Note 33)

A method for using reconfigurable circuit comprising a first line, a second line, and a resistive switch assembly disposed between the first line and the second line, wherein the resistive switch assembly includes a first non-volatile resistive switch and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch, a second end of the first non-volatile resistive switch is coupled to the first line, and a second end of the second non-volatile resistive switch is coupled to the second line, the method comprising:

using the first non-volatile resistive switch and the second non-volatile resistive switch as a data routing switch between the first line and the second line, by selectively making one of a first state in which the first non-volatile resistive switch and the second non-volatile resistive switch are in ON-state, and a second state in which the first non-volatile resistive switch and the second non-volatile resistive switch are in Off-state; and

using the first non-volatile resistive switch and the second non-volatile resistive switch as a memory element, by making one of the first non-volatile resistive switch and the second non-volatile resistive switch the ON-state and the other the OFF-state.

(Supplementary Note 34)

The method according to Supplementary Note 33, further comprising:

when used as the memory element, applying first voltage to the first line while applying second voltage to the second line, the second voltage being different from the first voltage; and

reading stored value of the memory element from a coupling part of the first end of the first non-volatile resistive switch element and the first end of the second non-volatile resistive element.

(Supplementary Note 35)

The method according to Supplementary Note 34, further comprising:

applying a first program voltage to the first line;

applying a second program voltage to the second line; and

applying a third program voltage to the coupling part,

wherein the first non-volatile resistive switch and the second non-volatile resistive switch are separately made one of the ON-state and the OFF state by a combination of the first program voltage, the second program voltage and the third program voltage.

111 Resistive switch assembly,

L 1 , L 2 lines,

S 111 , S 112 Non-volatile resistive switches (NVRSs),

T 1 , T 2 , T 3 Terminals.