Inventor
Ryusuke Nebashi
Inventor
Tokyo, JP
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores29%
H03KPulse technique23%
G06FElectric digital data processing11%
H10NElectric solid-state devices not otherwise provided for11%
H10BElectronic memory devices10%
H01LSemiconductor devices7%
B82YSpecific uses or applications of nanostructures1%
H02JElectric power networks1%
H10DInorganic electric semiconductor devices1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
PatentTitleYear
11,018,671Reconfigurable circuit and the method for using the same202110,979,053Logic integrated circuit202110,879,902Reconfigurable circuit using nonvolatile resistive switches202010,855,283Routing network for reconfigurable circuit202010,812,076Logic integrated circuit and semiconductor device202010,748,614Semiconductor device and programming method therefor202010,740,435Programmable logic integrated circuit, design support system, and configuration method202010,720,925Integrated circuit202010,396,798Reconfigurable circuit201910,305,485Programmable logic integrated circuit, semiconductor device, and characterization method201910,262,738Content addressable memory cell and content addressable memory201910,074,421Crossbar switch type memory circuit, look-up table circuit, and programming method201810,044,355Reconfigurable circuit with crossbar switches including non-volatile resistive switches201810,037,789Magnetic memory and method for writing data into magnetic memory element20189,898,070'Semiconductor integrated circuit and power supply control method therefor'20189,837,816Semiconductor device, power supply control method of semiconductor device, and sensor node20179,692,422'Programmable logic integrated circuit'20179,536,584'Nonvolatile logic gate device'20179,478,309'Magnetic-domain-wall-displacement memory cell and initializing method therefor'20169,299,435'Nonvolatile content addressable memory and method for operating same'20169,135,988'Semiconductor device and control method of the same'20159,100,013'Nonvolatile resistor network assembly and nonvolatile logic gate with increased fault tolerance using the same'20158,902,644'Semiconductor storage device and its manufacturing method'20148,872,542'Semiconductor device and semiconductor device control method'20148,510,633'Semiconductor storage device and method of operating the same'20138,503,222'Non-volatile logic circuit'20138,354,861'Magnetoresistive element, logic gate and method of operating logic gate'20138,284,595'Magnetic random access memory and operating method of the same'20128,243,502'Nonvolatile latch circuit and logic circuit using the same'20128,174,872'Nonvolatile latch circuit'20128,009,467'Magnetic random access memory'20117,894,249'Magnetoresistive element and magnetic random access memory'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2021Patents assigned to NEC CORP (31)· patent assignee history
2011–2021Based in Tokyo, JP· patent location history
2012–2015Patents assigned to NEBASHI RYUSUKE (10)· patent assignee history
2012–2015Patents assigned to SAKIMURA NOBORU (10)· patent assignee history
2012–2015Patents assigned to SUGIBAYASHI TADAHIKO (8)· patent assignee history
2016–2018Patents assigned to UNIV TOHOKU (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 31 | 2011–2021 |
| NEBASHI RYUSUKEself | 10 | 2012–2015 |
| SAKIMURA NOBORU | 10 | 2012–2015 |
| SUGIBAYASHI TADAHIKO | 8 | 2012–2015 |
| UNIV TOHOKU | 4 | 2016–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 32 | 2011–2021 |