Semiconductor device having vertical channel and method of manufacturing the same

Korean Patent Application No. 10-2017-0117048, filed on Sep. 13, 2017 in the Korean Intellectual Property Office, and entitled: “Semiconductor Device Having Vertical Channel and Method of Manufacturing the Same,” is incorporated by reference herein in its entirety.

1. Field

Embodiments relate to a semiconductor device having a vertical channel and a method of manufacturing the same.

2. Description of the Related Art

As a scaling technique to increase the density of semiconductor devices, multigate field effect transistors (FET) having an active pattern having the form of a fin or a nanowire suppressing a short channel effect have been proposed.

Embodiments are directed to a semiconductor device that includes a substrate; a vertical channel structure including a pair of active fins extended in a first direction, perpendicular to an upper surface of the substrate, and an insulating portion interposed between the pair of active fins; an upper source/drain disposed on the vertical channel structure; a lower source/drain disposed below the vertical channel structure and on the substrate; a gate electrode disposed between the upper source/drain and the lower source/drain and surrounding the vertical channel structure; and a gate dielectric layer disposed between the gate electrode and the vertical channel structure. An interval between the gate electrode and the upper source/drain may be smaller than an interval between the gate electrode and the lower source/drain in the first direction.

Embodiments are also directed to a semiconductor device that includes a substrate; a first vertical channel structure including a pair of first active fins disposed at a first pitch and a first insulating portion interposed between the pair of first active fins on the substrate; a second vertical channel structure including a pair of second active fins disposed at the first pitch and a second insulating portion interposed between the pair of second active fins on the substrate; upper source/drains disposed on the first vertical channel structure and the second vertical channel structure; a lower source/drain disposed below the first vertical channel structure and the second vertical channel structure; and a gate electrode disposed between the upper source/drains and the lower source/drain and surrounding the first vertical channel structure and the second vertical channel structure. The pair of first active fins and the pair of second active fins may be disposed adjacent to each other, and may be disposed at a second pitch greater than the first pitch.

Embodiments are also directed to a method of manufacturing a semiconductor device that includes forming a plurality of active fins alternately disposed on a substrate at a first pitch and a second pitch, greater than the first pitch; forming an insulating portion between the plurality of active fins disposed at the first pitch; forming a lower source/drain on the substrate using an ion implantation process; forming an upper source/drain on the plurality of active fins using a selective epitaxial process; forming a first spacer on a side surface of the upper source/drain; forming a gate dielectric layer and a gate electrode to cover side surfaces of the plurality of active fins and the first spacer; and partially removing the gate dielectric layer and the gate electrode using an anisotropic etching process.

Features will become apparent to those of skill in the art by describing in detail example embodiments with reference to the attached drawings in which:

FIG. 1 is a layout of a semiconductor device according to an example embodiment;

FIG. 2 illustrates a cross-sectional view taken along line I-I′ of a semiconductor device illustrated in FIG. 1 ;

FIG. 3 illustrates an enlarged view of region A of FIG. 2 ;

FIG. 4 illustrates a cross-sectional view taken along line II-II′ of a semiconductor device illustrated in FIG. 1 ;

FIGS. 5 to 18 illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device according to an example embodiment;

FIGS. 19 to 20 illustrate cross-sectional views of a semiconductor device according to an example embodiment;

FIG. 21 illustrates a layout of a semiconductor device according to an example embodiment;

FIG. 22 illustrates a cross-sectional view taken along line I-I′ of a semiconductor device illustrated in FIG. 21 ;

FIG. 23 illustrates a layout of a semiconductor device according to an example embodiment; and

FIG. 24 illustrates a cross-sectional view taken along line I-I′ of a semiconductor device illustrated in FIG. 23 .

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey example implementations to those skilled in the art. In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.

FIG. 1 is a layout of a semiconductor device 10 according to an example embodiment. FIG. 2 is a cross-sectional view taken along line I-I′ of a semiconductor device illustrated in FIG. 1 . FIG. 3 is an enlarged view of region A of FIG. 2 . FIG. 4 is a cross-sectional view taken along line II-II′ of a semiconductor device illustrated in FIG. 1 .

With reference to FIGS. 1 to 4 , the semiconductor device 10 may be provided as a vertical field effect transistor.

The semiconductor device 10 may include a substrate 101 , a first vertical channel structure CS 1 , and a second vertical channel structure CS 2 .

The first vertical channel structure CS 1 may include a pair of first active fins 110 a disposed on the substrate 101 (arranged at a first pitch P 1 in, for example, a third direction (for example, an X-axis direction)). The first active fins 110 a may extend in a first direction (for example, a Z-axis direction) perpendicular to an upper surface of the substrate 101 . The first vertical channel structure CS 1 may also include a first insulating portion 111 a interposed between the pair of first active fins 110 a.

The second vertical channel structure CS 2 may include a pair of second active fins 110 b disposed on the substrate 101 (arranged at the first pitch P 1 ) and extended in the first direction (for example, the Z-axis direction) perpendicular to the upper surface of the substrate 101 . The second vertical channel structure CS 2 may further include a second insulating portion 111 b interposed between the pair of second active fins 110 b.

The semiconductor device 10 may further include upper source/drains 112 disposed on the first vertical channel structure CS 1 and the second vertical channel structure CS 2 ; a lower source/drain 109 disposed below the first vertical channel structure CS 1 and the second vertical channel structure CS 2 ; a gate electrode 120 disposed between the upper source/drains 112 and a lower source/drain 109 and surrounding the first vertical channel structure CS 1 and the second vertical channel structure CS 2 ; and a gate dielectric layer 115 disposed between the gate electrode 120 and the first vertical channel structure CS 1 and between the gate electrode 120 and the second vertical channel structure CS 2 .

The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

A first active fin 110 a and a second active fin 110 b , disposed adjacent to each other, may be disposed at a second pitch P 2 greater than the first pitch P 1 . For example, the first pitch P 1 may be 30 nm or less, while the second pitch P 1 may be 100 nm or less. The first active fins 110 a and the second active fins 110 b may include the same semiconductor material as the substrate 101 .

The first active fins 110 a and the second active fins 110 b may extend in a second direction (for example, a Y-axis direction) intersecting the first direction. The first active fins 110 a and the second active fins 110 b may have a sheet shape in which a width in one direction is different from a width in the other direction. In another implementation, the first active fins 110 a and the second active fins 110 b may have a wire shape having a circular, oval, or polygonal cross section. The widths of the first active fins 110 a and the second active fins 110 b may be, for example, 10 nm or less. The first active fins 110 a and the second active fins 110 b may be referred to as a nanosheet or a nanowire.

In an example embodiment, an interval between the gate electrode 120 and the upper source/drains 112 is smaller than an interval between the gate electrode 120 and the lower source/drain 109 in the first direction perpendicular to the upper surface of the substrate 101 . The interval between the gate electrode 120 and the upper source/drains 112 may be equal to a thickness of the gate dielectric layer 115 .

The first vertical channel structure CS 1 and the second vertical channel structure CS 2 may provide a channel region having a silicon on insulator (SOI) structure. The first insulating portion 111 a and the second insulating portion 111 b may include, for example, a silicon nitride.

Upper surfaces of the first insulating portion 111 a and the second insulating portion 111 b may be disposed to be lower than upper surfaces of the first active fins 110 a and the second active fins 110 b . The upper surfaces of the first insulating portion 111 a and the second insulating portion 111 b may be disposed to be higher than an upper surface of the gate electrode 120 . In an example embodiment, the upper surfaces of the first insulating portion 111 a and the second insulating portion 111 b may be disposed to be lower than the upper surface of the gate electrode 120 . The upper source/drains 112 may be in contact with the first insulating portion 111 a and the second insulating portion 111 b.

Respective upper source/drains 112 may include protrusions 112 p protruding beyond side surfaces of the first vertical channel structure CS 1 and the second vertical channel structure CS 2 , as well as a central portion 112 c between the protrusions 112 p . A portion of the gate electrode 120 may overlap the protrusions 112 p in the first direction. A length of the protrusions 112 p protruding from the side surfaces of the first vertical channel structure CS 1 and the second vertical channel structure CS 2 may be greater than a thickness of the gate dielectric layer 115 . The gate dielectric layer 115 may extend below the protrusions 112 p of the upper source/drains 112 .

The upper source/drains 112 may be provided as an epitaxial layer grown from the first active fin 110 a and the second active fin 110 b using a selective epitaxial growth (SEG) process. The upper source/drains 112 may be doped with impurities. In the case of an n-type field effect transistor, the upper source/drains 112 may be formed using silicon (Si) doped with an n-type impurity. In the case of a p-type field effect transistor, the upper source/drains 112 may be formed using silicon-germanium (SiGe) doped with a p-type impurity.

The lower source/drain 109 disposed below the first active fin 110 a and the second active fin 110 b may be provided as a region doped with impurities using an ion implantation process. In the case of the n-type field effect transistor, the lower source/drains 109 may be doped with the n-type impurity. In the case of the p-type field effect transistor, the lower source/drains 109 may be doped with the p-type impurity.

The semiconductor device 10 may further include a lower spacer layer 131 disposed between the gate electrode 120 and the lower source/drain 109 , first spacers 137 disposed on a side surface of upper source/drains 112 and on the gate electrode 120 , and second spacers 138 covering a side surface of the first spacers 137 and a side surface of the gate electrode 120 . The lower spacer layer 131 may have a bent form. The lower spacer layer 131 , the first spacers 137 , and the second spacers 138 may include, for example, a silicon nitride.

The first spacers 137 may be disposed on a side surface of the protrusions 112 p of the upper source/drains 112 . The gate dielectric layer 115 may extend below the protrusions 112 p and the first spacers 137 . The gate dielectric layer 115 may extend to a lower surface of the first spacers 137 . A first dielectric layer 114 may extend to a lower surface of the protrusions 112 p , while a second dielectric layer 116 may extend to be longer than the first dielectric layer 114 and may extend to the lower surface of the first spacers 137 .

A lower surface of the gate electrode 120 may have a protruding portion corresponding to a form of the lower spacer layer 131 . The side surface of the gate electrode 120 may be coplanar with the side surface of a first spacer 137 . A portion of the gate electrode 120 may extend along the upper surface of the substrate 101 in the second direction. The first gate electrode 120 may include a first conductive layer including, for example, a metal nitride, such as TiN or TaN, and a second conductive layer including, for example, a metal, such as tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al).

The gate dielectric layer 115 may include the first dielectric layer 114 and the second dielectric layer 116 . The second dielectric layer 116 may have a dielectric constant higher than that of the first dielectric layer 114 . The first dielectric layer 114 may include, for example, a silicon oxide, while the second dielectric layer 116 may include, for example, a high-k dielectric material having a dielectric constant higher than that of a silicon oxide.

The high-k dielectric material may be formed using, for example, one or more of hafnium oxide (HfOx), hafnium silicate (FfSiOx), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaOx), lanthanum oxynitride (LaON), lanthanum aluminum oxide (LaAlOx), zirconium oxide (ZrOx), zirconium silicate (ZrSiOx), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaOx), titanium oxide (TiOx), titanium oxynitride (TiON), barium strontium titanium oxide (BaSrTiOx), barium titanium oxide (BaTiOx), strontium titanium oxide (SrTiOx), yttrium oxide (YOx), aluminum oxide (AlOx), aluminum oxynitride (AlON), or lead scandium tantalum oxide (PbScTaOx).

The semiconductor device 10 may further include an upper silicide layer 125 disposed on the upper source/drains 112 , a lower silicide layer 126 disposed in a portion of the lower source/drain 109 , an interlayer insulating layer 170 , and contact plugs 130 , 140 , and 150 , penetrating through the interlayer insulating layer 170 .

A contact plug 130 may be connected to the lower source/drain 109 . The lower silicide layer 126 may be disposed between the contact plug 130 and the lower source/drain 109 . A contact plug 140 may be connected to the upper source/drains 112 . The upper silicide layer 125 may be disposed between the contact plug 140 and the upper source/drains 112 . A contact plug 150 may be connected to the gate electrode 120 . The interlayer insulating layer 170 may include a low-k dielectric material. The contact plugs 130 , 140 , and 150 may include a metal nitride and a metal.

FIGS. 5 to 18 are cross-sectional views of stages in a method of manufacturing a semiconductor device 10 according to an example embodiment.

With reference to FIG. 5 , a plurality of active fins 110 a and 110 b may be formed on a substrate 101 in such a manner that the plurality of active fins 110 a and 110 b are alternately disposed at a first pitch P 1 and a second pitch P 2 greater than the first pitch P 1 (the first and second pitches P 1 , P 2 being in, for example, the third or X-axis direction). The first active fins 110 a may be disposed at the first pitch P 1 , while the second active fins 110 b may be disposed at the first pitch P 1 . The first active fin 110 a and the second active fin 110 b disposed adjacent to each other may be disposed at the second pitch P 2 .

A mask layer 102 may be formed above the substrate 101 , while the mask layer 102 may be etched to have the first pitch P 1 and the second pitch P 2 . The mask layer 102 may be etched using, for example, double patterning technology (DPT), quadruple patterning technology (QPT), or a combination thereof. The mask layer 102 having been patterned may be used as an etching mask, and the substrate 101 may be anisotropically etched, thereby forming the plurality of active fins 110 a and 110 b . The mask layer 102 may remain on the plurality of active fins 110 a and 110 b . The substrate 101 may be provided as a semiconductor substrate, while the mask layer 102 may be formed using an insulating material. For example, the substrate 101 may be provided as a silicon substrate, while the mask layer 102 may be formed using a silicon nitride.

With reference to FIG. 6 , a plurality of active fins 110 a and 110 b , as well as a first insulating layer 131 p covering an upper surface of the substrate 101 may be formed on the substrate 101 . The first insulating layer 131 p may be formed to have a thickness sufficient to entirely fill a space along the third or X-axis direction between the first active fins 110 a disposed at the first pitch P 1 and a space between the second active fins 110 b disposed at the first pitch P 1 .

The second insulating layer 132 may be formed on the first insulating layer 131 p in a region between vertical channel structures CS. The second insulating layer 132 may be formed using a material different from that of the first insulating layer 131 p . For example, the first insulating layer 131 p may be formed using a silicon nitride, while the second insulating layer 132 may be formed using a silicon oxide.

With reference to FIG. 7 , a lower source/drain 109 may be formed using an ion implantation process.

For example, the first insulating layer 131 p may be wet etched using the second insulating layer 132 as an etching mask. The lower spacer layer 131 may be formed below the second insulating layer 132 using an etching process described above. For example, the lower spacer layer 131 may be between the lower source/drain 109 and the second insulating layer 132 , and between the second insulating layer 132 and an adjacent second active fin 110 b.

The first insulating portion 111 a and the second insulating portion 111 b may be formed between the first active fins 110 a and the second active fins 110 b . A first insulating portion 111 a and a pair of first active fins 110 a in contact with the first insulating portion 111 a may form the first vertical channel structure CS 1 . A second insulating portion 111 b and a pair of second active fins 110 b in contact with the second insulating portion 111 b may form the second vertical channel structure CS 2 . Side surfaces of the first active fins 110 a and the second active fins 110 b in contact with the first insulating portion 111 a and the second insulating portion 111 b may be referred to as inner side surfaces. The side surfaces of the first active fins 110 a and the second active fins 110 b not in contact with the first insulating portion 111 a and the second insulating portion 111 b may be referred to as external side surfaces. The external side surfaces of active fins 110 a and 110 b may be exposed using the etching process.

Subsequently, the lower source/drain 109 may be formed by ion implantation and diffusion of impurities. After the ion implantation process of impurities, a heat treatment process of activating and diffusing impurities may be performed. In the case of an n-type field effect transistor, lower source/drains 109 may be doped with an n-type impurity. In the case of a p-type field effect transistor, lower source/drains 109 may be doped with a p-type impurity.

With reference to FIG. 8 , a third insulating layer 133 exposing upper portions of external side surfaces of the plurality of active fins 110 a and 110 b may be formed. The third insulating layer 133 may expose upper portions of the vertical channel structures CS 1 and CS 2 .

The third insulating layer 133 may be formed to cover the plurality of active fins 110 a and 110 b . Subsequently, the third insulating layer 133 may be partially removed to allow an upper surface of a mask layer 102 to be exposed using, for example, a chemical mechanical polishing (CMP) process. Subsequently, the third insulating layer 133 may be further etched. The third insulating layer 133 may be formed using, for example, a silicon oxide.

With reference to FIG. 9 , a fourth insulating layer 134 covering the third insulating layer 133 and the vertical channel structures CS 1 and CS 2 may be formed. Subsequently, a fifth insulating layer 135 may be formed on the fourth insulating layer 134 . The fifth insulating layer 135 may not be formed on the vertical channel structures CS 1 and CS 2 . An upper surface of the fifth insulating layer 135 may be coplanar with an upper surface of the fourth insulating layer 134 . The fourth insulating layer 134 may be formed using a deposition process. The fifth insulating layer 135 may be formed using a deposition process and a CMP process. In detail, the fourth insulating layer 134 may be formed using a silicon oxide, while the fifth insulating layer 135 may be formed using a silicon nitride.

With reference to FIG. 10 , openings OP may be formed on the vertical channel structures CS 1 and CS 2 . The fourth insulating layer 134 and the mask layer 102 may be selectively removed using a dry etching process. In this case, upper portions of insulating portions 111 a and 111 b may be removed together therewith, so that heights of the insulating portions 111 a and 111 b may be reduced. In addition, upper portions of the plurality of active fins 110 a and 110 b may also be removed, so that heights of the plurality of active fins 110 a and 110 b may be reduced. Upper surfaces of the insulating portions 111 a and 111 b may be lower than those of the plurality of active fins 110 a and 110 b . In an example embodiment, the upper surfaces of the insulating portions 111 a and 111 b may be lower than an upper surface of the third insulating layer 133 .

With reference to FIG. 11 , upper source/drains 112 may be formed in the openings OP. A semiconductor layer may be grown from the plurality of active fins 110 a and 110 b to be exposed in the openings OP using a selective epitaxial growth (SEG) process, and the semiconductor layer grown outwardly of the openings OP may be removed using the CMP process, thereby forming the upper source/drains 112 . The upper source/drains 112 may be doped with impurities. Impurities may be implanted while the semiconductor layer is grown. The upper source/drains 112 may be formed using, for example, doped silicon (Si) or doped SiGe.

With reference to FIG. 12 , the upper source/drains 112 may be partially removed, and sixth insulating layers 136 may be formed. Upper surfaces of the sixth insulating layers 136 may be coplanar with the upper surface of the fifth insulating layer 135 . A sixth insulating layer 136 may be formed using, for example, a deposition process and the CMP process. The sixth insulating layer 136 may be formed using, for example, a silicon nitride.

With reference to FIG. 13 , the fifth insulating layer 135 and the fourth insulating layer 134 may be sequentially removed. The fifth insulating layer 135 and the fourth insulating layer 134 may be removed using the dry etching process or a wet etching process. A portion of the sixth insulating layer 136 may be removed together therewith, thereby reducing a thickness of the sixth insulating layer 136 .

With reference to FIG. 14 , first spacers 137 may be formed on side surfaces of the upper source/drains 112 . The first spacers 137 may be formed using, for example, the deposition process and the dry etching process. The first spacers 137 may be formed using, for example, a silicon nitride.

With reference to FIG. 15 , the third insulating layer 133 and the second insulating layer 132 may be removed.

The external side surfaces of the plurality of active fins 110 a and 110 b may be exposed. A lower surface of a portion of the upper source/drains 112 may be exposed. The upper source/drains 112 may have a width in the third or X-axis direction that is greater than those of the underlying vertical channel structures CS 1 and CS 2 . Thus, the upper source/drains 112 may include protrusions protruding further than side surfaces of the vertical channel structures CS 1 and CS 2 in the third or X-axis direction. The third insulating layer 133 and the second insulating layer 132 may be removed using the wet etching process.

With reference to FIG. 16 , a gate dielectric layer 115 and a gate electrode 120 may be formed to cover the side surfaces of the plurality of active fins 110 a and 110 b , as well as the first spacers 137 .

The gate dielectric layer 115 may include a first dielectric layer 114 and a second dielectric layer 116 . The first dielectric layer 114 may be selectively formed on the external side surfaces of the plurality of active fins 110 a and 110 b and on lower surfaces of the protrusions of the upper source/drains 112 . The first dielectric layer 114 may be formed using a thermal oxidation process, a plasma oxidation process, a radical oxidation process, or the like. The first dielectric layer 114 may be formed using, for example, a silicon oxide.

Subsequently, the second dielectric layer 116 covering lower spacer layers 131 , the first dielectric layer 114 , the first spacers 137 , and the sixth insulating layers 136 may be formed. The second dielectric layer 116 may be formed using, for example, a high-k dielectric material.

Subsequently, the gate electrode 120 covering the second dielectric layer 116 may be formed. The gate electrode 120 may include a first conductive layer and a second conductive layer. The first conductive layer may include, for example, a metal nitride, such as TiN or TaN, while the second conductive layer may include, for example, a metal, such as W, Co, Cu, or Al.

The second dielectric layer 116 and the gate electrode 120 may be formed using the deposition process.

With reference to FIG. 17 , the gate dielectric layer 115 and the gate electrode 120 may be partially removed. The gate electrode 120 may only remain below the first spacers 137 using the etching process. Side surfaces of the first spacers 137 may be coplanar with side surfaces of the gate electrode 120 . The second dielectric layer 116 of the gate dielectric layer 115 may be partially removed. The second dielectric layer 116 may only remain below the first spacers 137 . The first spacers 137 may function as an etching mask. The gate electrode 120 and the second dielectric layer 116 may be removed using, for example, an anisotropic dry etching process.

With reference to FIG. 18 , upper silicide layers 125 may be formed on the upper source/drains 112 , while lower silicide layers 126 may be formed on the lower source/drain 109 .

The second spacers 138 may be formed to cover the side surfaces of the gate electrode 120 , and may extend in the first or Z-axis direction so as to completely cover the side surfaces of the gate electrode 120 . The second spacers 138 may be formed using the deposition process and the anisotropic dry etching process. The sixth insulating layer 136 on the upper source/drains 112 may be removed, and the lower spacer layer 131 on the lower source/drain 109 may be partially removed using the anisotropic etching process. Subsequently, the upper silicide layers 125 and the lower silicide layers 126 may be formed on the upper source/drains 112 and the lower source/drain 109 , having been exposed, respectively.

With reference to FIGS. 2 and 4 , an interlayer insulating layer 170 covering structures on the substrate 101 illustrated in FIG. 18 may be formed, and then contact plugs 130 , 140 , and 150 , penetrating through the interlayer insulating layer 170 may be formed.

A contact plug 130 may penetrate through the interlayer insulating layer 170 to be connected to the lower source/drain 109 of the substrate 101 . A contact plug 140 may penetrate through the interlayer insulating layer 170 to be connected to the upper source/drains 112 . A contact plug 150 may penetrate through the interlayer insulating layer 170 to be connected to the gate electrode 120 .

FIGS. 19 to 20 are cross-sectional views of a semiconductor device according to an example embodiment. In terms of a semiconductor device 10 A illustrated in FIGS. 19 and 20 , only differences from the semiconductor device 10 illustrated in FIGS. 2 and 4 will be described.

With reference to FIGS. 19 and 20 , the semiconductor device 10 A may not include lower silicide layers 126 . A lower spacer layer 131 may cover a lower source/drain 109 , while a second spacer 138 may cover the lower spacer layer 131 . A first interlayer insulating layer 165 may cover the second spacer 138 , while a second interlayer insulating layer 170 may be disposed on the first interlayer insulating layer 165 .

FIG. 21 is a layout of a semiconductor device according to an example embodiment. FIG. 22 is a cross-sectional view taken along line I-I′ of a semiconductor device illustrated in FIG. 21 . In terms of a semiconductor device 20 illustrated in FIGS. 21 and 22 , only differences from a semiconductor device 10 illustrated in FIGS. 2 and 4 will be described.

The semiconductor device 20 illustrated in FIGS. 21 and 22 may include a single vertical channel structure CS. A gate electrode 120 may surround a pair of active fins 110 disposed at a first pitch P 1 and side surfaces of the vertical channel structure CS including an insulating portion 111 .

FIG. 23 is a layout of a semiconductor device according to an example embodiment. FIG. 24 is a cross-sectional view taken along line I-I′ of a semiconductor device illustrated in FIG. 23 . In terms of a semiconductor device 30 illustrated in FIGS. 23 and 24 , only differences from a semiconductor device 10 illustrated in FIGS. 2 and 4 will be described.

The semiconductor device 30 illustrated in FIGS. 23 and 24 may include four vertical channel structures CS 1 , CS 2 , CS 3 , and CS 4 . A first vertical channel structure CS 1 may include a pair of first active fins 110 a disposed at a first pitch P 1 and a first insulating portion 111 a . A second vertical channel structure CS 2 may include a pair of second active fins 110 b disposed at the first pitch P 1 and a second insulating portion 111 b . A third vertical channel structure CS 3 may include a pair of third active fins 110 c disposed at the first pitch P 1 and a third insulating portion 111 c . A fourth vertical channel structure CS 4 may include a pair of fourth active fins 110 d disposed at the first pitch P 1 and a fourth insulating portion 111 d . The first active fin 110 a and the second active fin 110 b disposed adjacent to each other may be disposed at a second pitch P 2 greater than the first pitch P 1 . A second active fin 110 b and a third active fin 110 c , disposed adjacent to each other, may be disposed at the second pitch P 2 greater than the first pitch P 1 . A third active fin 110 c and a fourth active fin 110 d , disposed adjacent to each other, may be disposed at the second pitch P 2 greater than the first pitch P 1 .

A gate electrode 120 may surround side surfaces of the four vertical channel structures CS 1 , CS 2 , CS 3 , and CS 4 . A contact plug 140 may be connected to an entirety of upper source/drains 112 disposed on vertical channel structures CS 1 , CS 2 , CS 3 , and CS 4

As set forth above, example embodiments may provide a semiconductor device having a structure appropriate for scaling. According to example embodiments, a change in a threshold voltage may not occur during a manufacturing process, and resistance variation of the semiconductor device may be improved.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.