Memory device and method of operating the same

This application claims the benefit of Korean Patent Application No. 10-2017-0024546 filed on Feb. 24, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

The current disclosure relates to a memory device and a method of operating the same.

Examples of nonvolatile memories using resistance materials include phase-change random access memories (PRAMs), resistive RAMs (RRAMs), and magnetic RAMs (MRAMs). While dynamic RAMs (DRAMs) or flash memories store data using charges, nonvolatile memories using resistance materials store data using a state change of a phase-change material such as a chalcogenide alloy (in the case of PRAMs), a resistance change of a variable resistance material (in the case of RRAMs), or a resistance change of a magnetic tunnel junction (MTJ) thin film according to a magnetization state of a ferromagnetic material (in the case of MRAMs).

In particular, a phase-change material of a PRAM cell assumes a crystalline state or an amorphous state as it is cooled after being heated. The phase-change material has low resistance in the crystalline state and has high resistance in the amorphous state. Therefore, the crystalline state may be defined as corresponding or indicating set data or data 0 , and the amorphous state may be defined as corresponding or indicating reset data or data 1 .

An access element or a selector that controls a PRAM cell may be implemented as a diode type, a transistor type, or an ovonic threshold switch (OTS) type.

Aspects of the disclosure provide a memory device which can secure a sensing margin for memory cells while reducing power consumption.

Aspects of the disclosure also provide a method of operating a memory device which can secure a sensing margin for memory cells while reducing power consumption.

However, aspects of the disclosure are not restricted to the one set forth herein. The above and other aspects of the disclosure will become more apparent to one of ordinary skill in the art to which the disclosure pertains by referencing the detailed description of the disclosure given below.

According to an aspect of the disclosure, there is provided a memory device including a resistive memory cell which is connected to a first node and comprises a variable resistive element and an access element controlling a current flowing through the variable resistive element; a current supply unit which provides a comparison current to be compared with a cell current flowing through the first node to a sensing node in order to read data stored in the resistive memory cell; a clamping unit which is connected between the sensing node and the first node and comprises a transistor and a capacitor connected to a gate of the transistor by a second node; and a sense amplifier which senses the sensing node and transitions an output value when a voltage level of the sensing node is lower than a reference voltage, wherein the clamping unit receives a first read voltage and a boost voltage, ramps up a voltage of the first node in a first precharge mode, and adjusts a level of a second read voltage of the second node in a second precharge mode.

According to another aspect of the disclosure, there is provided a memory device including a resistive memory cell which is connected to a first node and comprises a variable resistive element and an access element controlling a current flowing through the variable resistive element; and a clamping unit which is connected to the first node comprises a transistor, a capacitor connected to a gate of the transistor by a second node, a first switch receiving a first read voltage and providing the first read voltage to the transistor and the capacitor, a second switch connecting the capacitor and the first node, and a third switch receiving a boost voltage and providing the boost voltage to the capacitor, wherein, using the first through third switches, the clamping unit ramps up a voltage of the first node in a first precharge mode and adjusts a level of a second read voltage of the second node in a second precharge mode.

According to still another aspect of the disclosure, there is provided a method of operating a memory device including providing a resistive memory cell which is connected to a first node and comprises a variable resistive element and an access element controlling a current flowing through the variable resistive element; providing a comparison current, which is to be compared with a cell current flowing through the first node, to a sensing node in order to read data stored in the resistive memory cell; ramping up a voltage of the first node in a first precharge mode; adjusting a voltage level of a second node in a second precharge mode; and sensing the sensing node and transitioning an output value when a voltage level of the sensing node is lower than a reference voltage.

According to yet another aspect of the disclosure, there is provided a memory device including a transistor which is included in a nonvolatile memory cell; a capacitor which is connected to a gate of the transistor; a first switch which receives a first read voltage and provides the first read voltage to the transistor and the capacitor; a second switch which connects the capacitor and a source of the transistor; and a third switch which receives a boost voltage and provides the boost voltage to the capacitor, wherein the first through third switches form different circuit configurations in a first operation mode and a second operation mode.

According to a further aspect of the disclosure, a memory device comprises: a memory cell which is connected to a sensing node via a first node, the sensing node being configured to be precharged to a precharge voltage prior to reading data from the memory cell; and a clamping unit which is connected between the first node and the sensing node, and which includes a transistor and a capacitor which is configured to be selectively connected between the first node and a control terminal of the transistor, wherein the clamping unit is configured to ramp up a voltage of the first node and to charge a capacitor in a first precharge period, and to adjust a level of the voltage of the first node in a second precharge period, using a stored voltage charged into the capacitor during the first precharge period.

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a memory system.

FIG. 2 is a block diagram of a memory device.

FIG. 3A , FIG. 3B and FIG. 4 are diagrams illustrating a memory cell array of FIG. 2 .

FIG. 5 is a block diagram of a memory device.

FIG. 6 , FIG. 7 , and FIG. 8 are circuit diagrams of the memory device illustrated in FIG. 5 .

FIG. 9 is a timing diagram for explaining a method of operating a memory device.

FIG. 10 is a circuit diagram of a memory device.

FIG. 11A and FIG. 11B are a circuit diagram and a block diagram of a memory device.

FIG. 12 is a flowchart illustrating a method of operating a memory device.

FIG. 1 is a block diagram of a memory system according to embodiments.

Referring to FIG. 1 , embodiments of a memory system may include a plurality of memory devices 11 _ 1 through 11 _ m (where m is a natural number) and a controller 21 .

Memory devices 11 _ 1 through are connected to controller 21 by control lines and input/output (I/O) data lines. For example, controller 21 may provide various commands (such as a write command and a read command) to memory devices 11 _ 1 through 11 _ m through the control lines. In addition, controller 21 may exchange data with memory devices 11 _ 1 through 11 _ m through the I/O data lines.

In the drawing, memory devices 11 _ 1 through 11 _ m share the control lines and the I/O data lines with each other. However, the disclosure is not limited to this case. For example, memory devices 11 _ 1 through 11 _ m may share only the I/O data lines and may not share the control lines.

Memory devices 11 _ 1 through 11 _ m may include various kinds of memories. Memory devices 11 _ 1 through 11 _ m may include volatile memory devices such as a dynamic random access memory (DRAM) and nonvolatile memory devices such as a NAND flash memory and a NOR flash memory. In addition, memory devices 11 _ 1 through may include nonvolatile memory devices (i.e., resistive memory devices) using a resistance material, such as a phase-change random access memory (PRAM), a resistive RAM (RRAM), and a magnetic RAM (MRAM).

FIG. 2 is a block diagram of a memory device. In FIG. 2 , a nonvolatile memory device composed of sixteen memory banks is illustrated as an example. However, the disclosure is not limited to this example.

Referring to FIG. 2 , the nonvolatile memory device includes a memory cell array, a plurality of sense amplifiers and write drivers 2 _ 1 through 2 _ 8 , and a peripheral circuit region 3 .

The memory cell array may be composed of a plurality of memory banks 1 _ 1 through 1 _ 16 , and each of memory banks 1 _ 1 through 1 _ 16 may be composed of a plurality of memory blocks BLK 0 through BLK 7 . Each of the memory blocks BLK 0 through BLK 7 includes a plurality of nonvolatile memory cells arranged in a matrix. In some embodiments, each of memory banks 1 _ 1 through 1 _ 16 includes eight memory blocks.

Although not specifically illustrated in the drawing, a row select circuit and a column select circuit are placed to correspond to each of memory banks 1 _ 1 through 1 _ 16 . The row select circuit and the column select circuit respectively select a row and a column of resistive memory cells to be written or read.

Each of the sense amplifiers and write drivers 2 _ 1 through 2 _ 8 is placed to correspond to two of memory banks 1 _ 1 through 1 _ 16 and executes read and write operations on the two corresponding memory banks. In some embodiments, each of the sense amplifiers and write drivers 2 _ 1 through 2 _ 8 corresponds to two of memory banks 1 _ 1 through 1 _ 16 . However, in other embodiments, each of the sense amplifiers and write drivers 2 _ 1 through 2 _ 8 can also correspond to one memory bank or four memory banks.

Peripheral circuit region 3 may include a plurality of logic circuit blocks and a voltage generator needed to operate the column select circuit, the row select circuit, and the sense amplifiers and write drivers 2 _ 1 through 2 _ 8 .

FIGS. 3A, 3B and 4 are diagrams illustrating the memory cell array of FIG. 2 .

Referring to FIGS. 3A and 3B , the memory cell array may have a cross-point structure. In the cross-point structure, one memory cell is formed in an area where one line crosses another line. For example, bit lines BL 1 _ 1 through BL 4 _ 1 may extend in a first direction, and word lines WL 1 _ 1 through WL 3 _ 1 may extend in a second direction to cross the bit lines BL 1 _ 1 through BL 4 _ 1 . A resistive memory cell MC may be formed in an area where each of the bit lines BL 1 _ 1 through BL 4 _ 1 crosses each of the word lines WL 1 _ 1 through WL 3 _ 1 .

Here, when the resistive memory cell MC is a PRAM, it may include a variable resistive element GST which contains a phase-change material and an access element which controls a current flowing through the variable resistive element GST.

In FIG. 3A , the access element may be a diode D or a transistor (not illustrated) connected in series to the variable resistive element GST. In FIG. 3B , the access element may be an ovonic threshold switch (OTS) connected in series to the variable resistive element GST.

Examples of the phase-change material include combinations of two elements such as GaSb, InSb, InSe, Sb 2 Te 3 and GeTe, combinations of three elements such as GeSbTe, GaSeTe, InSbTe, SnSb 2 Te 4 and InSbGe, and combinations of four elements such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and Te 81 Ge 15 Sb 2 S 2 . Of these, GeSbTe composed of germanium (Ge), antimony (Sb) and tellurium (Te) may be mainly used.

On the other hand, when the resistive memory cell MC is an RRAM, the variable resistive element may include, for example, NiO or perovskite. The perovskite may be a composition such as manganite (Pr 0.7 Ca 0.3 MnO 3 , Pr 0.5 Ca 0.5 MnO 3 , other PCMO, LCMO, etc.), titanate (STO:Cr), or zirconate (SZO:Cr, Ca 2 Nb 2 O 7 :Cr, Ta 2 O 5 :Cr). A filament may be formed in the variable resistive element GST. The filament serves as a current path of a cell current flowing through the resistive memory cell MC.

The memory cell array may have a 3D stack structure as illustrated in FIG. 4 . The 3D stack structure may denote a structure in which a plurality of memory cell layers 111 _ 1 through 111 _ 8 are vertically stacked. In FIG. 4 , eight memory cell layers 111 _ 1 through 111 _ 8 are stacked. However, the disclosure is not limited to this case. Here, each of memory cell layers 111 _ 1 through 111 _ 8 may include a plurality of memory cell groups and/or a plurality of redundancy memory cell groups. When the memory cell array has the 3D stack structure, each of memory cell layers 111 _ 1 through 111 _ 8 may have, but not necessarily have, the cross-point structure of FIG. 3 .

FIG. 5 is a block diagram of a memory device.

Referring to FIG. 5 , the memory device includes a precharge unit 120 , a clamping unit 130 , a current supply unit 140 , a resistive memory cell 170 , and a sense amplifier 180 .

Precharge unit 120 is connected to a sensing node SN to precharge the sensing node SN. For example, precharge unit 120 may provide a power supply voltage VDD to the sensing node SN before performing a read operation on resistive memory cell 170 .

Clamping unit 130 is connected between a first node N 0 and the sensing node SN and receives a first read voltage Vcmp 0 and a boost voltage Vboost to ramp up the voltage of the first node N 0 .

Current supply unit 140 supplies a comparison current Ibias, which is to be compared with a cell current Icell flowing through the first node N 0 , to the sensing node SN so as to read data stored in resistive memory cell 170 .

Resistive memory cell 170 is connected to the first node N 0 and includes a variable resistive element 171 and an access element 172 (see FIG. 6 ) which controls a current flowing through variable resistive element 171 . As described above with reference to FIGS. 3A and 3B , access element 172 may be a diode D connected in series to the variable resistance element GST or may be an OTS connected in series to the variable resistance element GST.

Sense amplifier 180 senses the sensing node SN and transitions output value SOUT when the voltage level of the sensing node SN is less than a reference voltage Vref.

In the current embodiment, a period during which precharge unit 120 precharges the sensing node SN may be divided into a first precharge mode and a second precharge mode according to the operation of clamping unit 130 .

A first precharge period during which clamping unit 130 ramps up the voltage of the first node N 0 while precharge unit 120 is precharging the sensing node SN is defined as the first precharge mode, and then a second precharge period during which clamping unit 130 cancels a precharge, offset generated by the first node N 0 in the first precharge mode is defined as the second precharge mode.

When clamping unit 130 ramps up the voltage of the first node N 0 , the voltage level of the first node N 0 may be changed according to data stored in resistive memory cell 170 . For example, the voltage level of the first node N 0 when the data stored in resistive memory cell 170 corresponds to RESET data may be greater than the voltage level of the first node N 0 when the data stored in resistive memory cell 170 corresponds to SET data.

The difference in voltage level that occurs during precharging is called a precharge offset. Since the precharge offset should be taken into consideration to perform a read operation on resistive memory cell 170 , the sensing margin of the memory device can be reduced. Therefore, the precharge offset should be cancelled in order to secure an increased sensing margin of the memory device.

To cancel the precharge offset, an operational transconductance amplifier (OTA) may be employed in clamping unit 130 . In this case, an input of the OTA may be connected to the first node N 0 by a negative feedback loop in order to prevent the generation of the precharge offset by the first node N 0 . However, the OTA has drawbacks in that it consumes a lot of power and has high complexity in its design for securing the stability of the feedback loop.

In this regard, there is a need for a method of securing a sensing margin for memory cells while reducing power consumption. In various embodiments, while the sensing node SN is being precharged, clamping unit 130 ramps up the voltage of the first node N 0 (the first precharge mode) and then cancels the precharge offset generated by the first node N 0 using a capacitor C. This will be described in detail later with reference to FIGS. 6 through 9 .

FIGS. 6 through 8 are circuit diagrams of the memory device illustrated in FIG. 5 .

Referring to FIG. 6 , precharge unit 120 may be implemented using a P-type transistor MP 1 gated by an nPchg signal. However, the scope of the disclosure is not limited to this case, and the specific implementation of precharge unit 120 can be changed as desired.

Current supply unit 140 may be implemented using a P-type transistor MP 2 gated by an E signal and a current source Ib. However, the scope of the disclosure is not limited to this case, and the specific implementation of current supply unit 140 can be changed as desired.

Resistive memory cell 170 includes variable resistive element 171 and access element 172 which controls a current flowing through variable resistive element 171 . Resistive memory cell 170 is connected to the first node N 0 .

Clamping unit 130 includes a transistor MN 1 and the capacitor C. The transistor MN 1 may be an N-type transistor MN 1 gated by a second read voltage Vcmp 1 corresponding to a voltage of a second node N 1 . The capacitor C may be connected to a gate of the transistor MN 1 at the second node N 1 .

Clamping unit 130 may ramp up the voltage of the first node N 0 in the first precharge mode and adjust the level of the second read voltage Vcmp 1 of the second node N 1 in the second precharge mode by using the capacitor C.

The capacitor C may sample a gate-source voltage VGS of the transistor MN 1 in the first precharge mode and adjust the voltage level of the second node N 1 using the gate-source voltage VGS of the transistor MN 1 and the boost voltage Vboost in the second precharge mode.

For example, clamping unit 130 may increase the level of the second read voltage Vcmp 1 when the data stored in resistive memory cell 170 corresponds to SET data, and reduce the level of the second read voltage Vcmp 1 when the data stored in resistive memory cell 170 corresponds to RESET data.

The second read voltage Vcmp 1 thus adjusted can cancel a precharge offset generated by the first node N 0 , and the memory device according to the current embodiment can perform a read operation on resistive memory cell 170 based on the second read voltage Vcmp 1 adjusted by clamping unit 130 .

In particular, in the current embodiment, clamping unit 130 may include switches S 0 through S 2 .

A first switch S 0 may provide the first read voltage Vcmp 0 to the transistor MN 1 and the capacitor C, a second switch S 1 may connect the capacitor C and the first node N 0 , and a third switch S 2 may provide the boost voltage Vboost to the capacitor C. However, the scope of the disclosure is not limited to this case, and the specific implementation can be changed as desired.

Referring to FIG. 6 , the first switch S 0 and the second switch S 1 are closed, and the third switch S 2 is opened. FIG. 6 corresponds to the first precharge mode. The first read voltage Vcmp 0 is provided to the gate of the transistor MN 1 and an end of the capacitor C, and the other end of the capacitor C is connected to the first node N 0 . Accordingly, the capacitor C samples the gate-source voltage VGS of the transistor MN 1 .

Referring to FIG. 7 , the first switch S 0 and the second switch S 1 are opened, and the third switch S 2 is closed. FIG. 7 corresponds to the second precharge mode. The boost voltage Vboost is provided to the capacitor C instead of the first read voltage Vcmp 0 being provided to the capacitor C. In addition, the capacitor C and the first node N 0 are disconnected.

Accordingly, the second read voltage Vcmp 1 of the second node N 1 is determined by the gate-source voltage VGS of the transistor MN 1 and the boost voltage Vboost. For example, the second read voltage Vcmp 1 of the second node N 1 may be determined by the sum of the gate-source voltage VGS of the transistor MN 1 and the boost voltage Vboost.

The second read voltage Vcmp 1 thus adjusted can cancel the precharge offset generated by the first node N 0 , and the memory device can perform a read operation on resistive memory cell 170 based on the adjusted second read voltage Vcmp 1 .

Referring to FIG. 8 , all of the switches S 0 through S 2 are opened. FIG. 8 corresponds to a general develop operation performed after the sensing node SN is precharged and after the precharge offset generated by the first node N 0 is cancelled.

FIG. 9 is a timing diagram for explaining a method of operating a memory device.

Referring to FIG. 9 , the method of operating a memory device may be divided into a first section I (i.e., first precharge period), a second section II (i.e., second precharge period), and a third section III (i.e., develop period).

The first section I corresponds to the first precharge mode described above with reference to FIG. 6 . In the first section I, the first switch S 0 and the second switch S 1 are closed, and the third switch S 2 is opened.

Specifically, the sensing node SN is precharged according to the nPchg signal transitioned at a time t 1 .

At this time, the voltage level of the first node N 0 is ramped up and then clamped by clamping unit 130 . As is apparent from FIG. 9 , the voltage level of the first node N 0 when the data stored in resistive memory cell 170 corresponds to RESET data is greater than the voltage level of the first node N 0 when the data stored in resistive memory cell 170 corresponds to SET data. Therefore, a precharge offset is generated, as described above.

The second section II corresponds to the second precharge mode described above with reference to FIG. 7 . In the second section II, the first switch S 0 and the second switch S 1 are opened, and the third switch S 2 is closed.

Specifically, as the states of the first through third switches S 0 through S 2 are changed at a time t 2 , the second read voltage Vcmp 1 provided to the second node N 1 is adjusted. For example, as illustrated in FIG. 9 , when the data stored in resistive memory cell 170 corresponds to SET data, the level of the second read voltage Vcmp 1 may be increased. On the other hand, when the data stored in cell 170 corresponds to RESET data, the level of the second read voltage Vcmp 1 may be reduced.

Accordingly, the precharge offset generated by the first node N 0 is cancelled in the second section II.

The third section III corresponds to the develop mode described above with reference to FIG. 8 . In the third section III, all of the switches S 0 through S 2 are opened. In addition the memory device may perform a read operation on the resistive memory cell 170 based on the second read voltage Vcmp 1 adjusted by clamping unit 130 .

According to the various embodiments described so far, while the sensing node SN is being precharged, clamping unit 130 ramps up the voltage of the first node N 0 and then cancels the precharge offset generated by the first node N 0 using the capacitor C. In this way, it is possible to easily secure a sensing margin for memory cells while reducing power consumption.

As described above with respect to FIGS. 5-9 , in some embodiments a memory device includes a memory cell which is connected to a sensing node via a first node, the sensing node being configured to be precharged to a precharge voltage prior to reading data from the memory cell. A clamping unit is connected between the first node and the sensing node, and includes a transistor and a capacitor which is configured to be selectively connected between the first node and the control terminal (e.g., gate) of the transistor. The clamping unit is configured to ramp up a voltage of the first node and to charge a capacitor in a first precharge period, and to adjust a level of the voltage of the first node in a second precharge period, using a stored voltage charged into the capacitor during the first precharge period.

FIG. 10 is a circuit diagram of a memory device.

Referring to FIG. 10 , the memory device may be implemented to perform differential sensing.

However, a precharge offset generated by a node BL and a node BLb not only can affect the sensing margin of the memory device that performs differential sensing, but can also degrade the performance of the memory device.

To address this problem, the design of clamping unit 130 described above with reference to FIGS. 5 through 9 may be applied to a differential sensing circuit 200 of FIG. 10 .

For example, a circuit 210 including a plurality of switches nPchg 1 , Pchg 1 and Pchg 2 and a capacitor C 1 connected between the switches may be implemented as illustrated in FIG. 10 on a left side of differential sensing circuit 200 . The switches may correspond to the first through third switches S 0 through S 2 of clamping unit 130 described above and may be operated by nPchg 1 , Pchg 1 and Pchg 2 signals. Accordingly, in a first mode, a voltage VPrecmp may be provided to a gate of a left n-channel metal oxide semiconductor (NMOS) transistor of differential sensing circuit 200 and to the capacitor. In a second mode, a boost voltage Vboostcmp may be provided to the capacitor to adjust the voltage level of the gate of the left NMOS transistor such that the precharge offset generated by the node BLb can be cancelled.

Likewise, a circuit 220 including a plurality of switches and a capacitor C 2 connected between the switches may be implemented as illustrated in FIG. 10 on a right side of differential sensing circuit 200 . The switches may correspond to the first through third switches S 0 through S 2 of clamping unit 130 described above and may be operated by nPchg 1 , Pchg 1 and Pchg 2 signals. Accordingly, in the first mode, a voltage VPrecmp may be provided to a gate of a right NMOS transistor of differential sensing circuit 200 and to the capacitor. In the second mode, a boost voltage Vboostcmp may be provided to the capacitor to adjust the voltage level of the gate of the right NMOS transistor such that the precharge offset generated by the node BL can be cancelled.

In this way, it is possible to easily secure the memory cell sensing margin of differential sensing circuit 200 while reducing power consumption.

FIGS. 11A and 11B are a circuit diagram and a block diagram of a memory device.

FIG. 11A illustrates a circuit 310 which is implemented in a sensing circuit 300 of a NAND flash memory cell and corresponds to the design of clamping unit 130 described above with reference to FIGS. 5 through 9 . FIG. 11B illustrates a NAND flash device in which sensing circuit 300 of the memory cell is implemented.

Referring to FIG. 11B , the NAND flash device includes a memory cell array 320 , a row decoder 330 , a page buffer 340 , and a control logic 350 .

Memory cell array 320 is a storage area for storing information. Memory cells included in memory cell array 320 are disposed at intersections of a plurality of word lines WL 0 through WLn−1 and a plurality of bit lines BL 0 through BLm−1, respectively. Each of the memory cells may store 1-bit data or n-bit data (where n is an integer of 2 or more). Page buffer 340 is further provided in the flash memory to store data in memory cell array 320 or to read data from memory cell array 320 .

Row decoder 330 decodes a row address received from a row address buffer and selects any one of the word lines WL 0 through WLn−1 based on the decoding result. Word line voltages are provided to the selected word line according to an operation mode. For example, the word line: voltages include a word line program voltage, a pass voltage, a verify voltage, an erase voltage, and a read voltage.

Page buffer 340 senses data from a page of memory cell array 320 and temporarily stores the data or temporarily stores data to be programmed in a selected page. Page buffer 340 is controlled by control logic 350 to operate as a sense amplifier or a write driver according to the operation mode. In a read/verify operation, page buffer 340 senses data from memory cells of a selected word line through the bit lines BL 0 through BLm−1. In a program operation, page buffer 340 supplies a power supply voltage (or a program-inhibited voltage) or a ground voltage (or a program voltage) to the bit lines BL 0 through BLm−1 according to data to be programmed.

Control logic 350 receives control signals (e.g., /CE, /RE, /WE/, CLE, ALE, /WP, etc.) from an external memory controller and controls all aspects of the memory cells of nonvolatile memory cell array 320 related to program/erase/read/verify operations. Control logic 500 may include a high-voltage generating circuit which generates high voltages required for the program/erase/read/verify operations of the memory cells. For example, in a program operation, the high-voltage generating circuit may provide a program voltage to a selected word line and a pass voltage to an unselected word line. In a read operation, the high-voltage generating circuit may provide a read voltage to the selected word line and a ground voltage to the unselected word line.

Referring to FIG. 11A , circuit 300 for sensing the memory cells of memory cell array 320 may also need to cancel a precharge offset generated by a node BL.

In this case, the design of clamping unit 130 described above with reference to FIGS. 5 through 9 may be applied to sensing circuit 300 of the NAND flash memory cell of FIG. 11 .

For example, circuit 310 including a plurality of switches SW 1 , SW 2 and NM 4 and a capacitor C 2 connected between the switches SW 1 , SW 2 and NM 4 may be implemented so as to be connected to the gate and source of a transistor NM 1 (shown on the left side of transistor NM 1 in FIG. 11A ). The switches SW 1 , SW 2 and NM 4 may correspond to the first through third switches S 0 through S 2 of the clamping unit 130 described above, and the switch NM 4 may be operated by a DIS signal. Accordingly, in a first mode, a read voltage having a predetermined value is provided to a node BLSHF_G, a gate of the transistor NM 1 , and the capacitor C 1 . In a second mode, a boost voltage having a predetermined value is provided to the capacitor C 1 to adjust the voltage level of a node BLSHF_L such that the precharge offset generated by the node BL can be cancelled.

In this way, it is possible to easily secure: the memory cell sensing margin of sensing circuit 300 of the NAND flash memory cell while reducing power consumption.

It should be noted that the circuits illustrated in FIGS. 10 and 11A are merely example implementations to which the design of clamping unit 130 described above with reference to FIGS. 5 through 9 can be applied. That is, it is obvious to those skilled in the art that the design of clamping unit 130 described above with reference to FIGS. 5 through 9 can be applied to various sensing circuits.

It should be particularly noted that the design of clamping unit 130 described above with reference to FIGS. 5 through 9 is generally applicable to resistive memory devices such as a PRAM, an RRAM and an MRAM as well as to other nonvolatile memory devices such as a NAND flash and a NOR flash. Therefore, the scope of application of the various embodiments described herein is not limited to resistive memory devices.

Specifically, a gate of a transistor included in a nonvolatile memory cell may be connected to a capacitor such as those described above with reference to FIGS. 5 through 9 . In addition, a first switch which receives a first read voltage and provides the first read voltage to the transistor and the capacitor, a second switch which connects the capacitor and a source of the transistor, and a third switch which receives a boost voltage and provides the boost voltage to the capacitor may be implemented.

The first through third switches may form different circuit configurations in a first operation mode and a second operation mode corresponding to the first precharge mode and the second precharge mode, as described above with reference to FIGS. 5 through 9 .

FIG. 12 is a flowchart illustrating a method of operating a memory device.

Referring to FIG. 12 , the method of operating a memory device includes sampling a gate-source voltage VSG of a transistor MN 1 while a voltage of a first node N 0 is ramped up in a first precharge mode (operation S 1201 ).

In addition, the method includes adjusting (i.e. boosting) a voltage level of a second node N 1 using the gate-source voltage VGS of the transistor MN 1 and a boost voltage Vboost in a second precharge mode (operation S 1203 ). Here, the term “boost” is a concept encompassing both positive boost and negative boost.

In some embodiments, the adjusting of the voltage level of the second node N 1 may include increasing a level of a second read voltage Vcmp 1 when data stored in a resistive memory cell 170 corresponds to SET data.

In some embodiments, the adjusting of the voltage level of the second node N 1 may include reducing the level of the second read voltage Vcmp 1 when the data stored in the resistive memory cell 170 corresponds to RESET data.

The method further includes performing a read operation (i.e., sensing) on resistive memory cell 170 based on the adjusted voltage level of the second node N 1 (operation S 1205 ).

According to the various embodiments described above, while a sensing node SN is being precharged, clamping unit 130 ramps up the voltage of the first node N 0 and then cancels a precharge offset generated by the first node N 0 using a capacitor C. In this way, it is possible to easily secure a sensing margin for memory cells while reducing power consumption.

While the present disclosure has been particularly illustrated and described with reference to example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims. The example embodiments should be considered in a descriptive sense only and not for purposes of limitation.