Semiconductor device

This nonprovisional application is based on Japanese Patent Application No. 2016-174782 filed on Sep. 7, 2016 and No. 2017-114455 filed on Jun. 9, 2017, with the Japan Patent Office, the entire contents of which are hereby incorporated by reference.

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a searching function.

Description of the Background Art

In recent years, there has been an increasing demand for a content addressable memory (CAM) due to proliferation of the Internet. In addition to the memory's original storage function of holding data, the CAM has a comparison function of detecting a match between the data input from the outside and the data held therein. This CAM is used mainly in a cache memory, an address translation table, and the like.

A search device disclosed in Japanese Patent Laying-Open No. 02-192098 is configured to use a memory cell (CAM cell) incorporating a comparison function of detecting a match for each 1-bit storage circuit for holding data, to thereby detect a match between the data input from the outside and the data held in the storage circuit without reading the data held in the storage circuit.

In addition to the address searching function, the CAM is recently used also in the field of image recognition processing and the like for implementing a similar pattern search (minimum distance search) function of searching for a pattern that is most similar to the input pattern from among the reference patterns stored in the database. As the number of addresses to be searched for and the number of patterns to be processed are increased, the number of times of operation processes in the CAM is increased. Accordingly, particularly in the case where real-time processing is required, the processing speed in the CAM needs to be improved. In addition, the memory capacity of the CAM has recently been increased, so that a highly integrated CAM is also demanded.

The present disclosure has been made in order to solve the above-described problems. In a certain aspect, an object of the present disclosure is to provide a semiconductor device allowing a high-speed data search.

Other problems and new characteristics will become apparent from the description in the present specification and the accompanying drawings.

A semiconductor device according to an embodiment includes: a first cell configured to be capable of holding 1-bit information; a second cell configured to be capable of holding 1-bit information and located adjacent to the first cell; a first match line and a second match line that extend in a first direction; a first search line pair extending in a second direction orthogonal to the first direction, first data being transmitted through the first search line pair when the first data is searched for; a second search line pair extending in the second direction, second data being transmitted through the second search line pair when the second data is searched for; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by each of the first cell and the second cell and the first data transmitted through the first search line pair; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by each of the first cell and the second cell and the second data transmitted through the second search line pair.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to an embodiment.

FIG. 2 is a circuit diagram illustrating a configuration example of a memory cell according to an embodiment.

FIG. 3 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, a contact hole, and a first layer metal interconnection in the memory cell arranged in the semiconductor device.

FIG. 4 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIG. 5 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIG. 6 is a circuit diagram illustrating a configuration example of a memory cell according to another embodiment.

FIG. 7 is a block diagram illustrating a configuration example of a semiconductor device according to another embodiment.

FIG. 8 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, a contact hole, and a first layer metal interconnection in the memory cell according to another embodiment.

FIG. 9 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in the memory cell according to another embodiment.

FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device according to an embodiment.

FIG. 11 is a circuit diagram illustrating a configuration example of a memory cell arranged in the semiconductor device.

FIG. 12 is a diagram showing, in a table form, the correspondence relation between the data held by each of a data cell and a mask data cell, and the data in the memory cell in FIG. 11 .

FIG. 13 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, a contact hole, and a first layer metal interconnection in the memory cell arranged in the semiconductor device.

FIG. 14 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIG. 15 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIG. 16 is a diagram illustrating a metal interconnection pattern in a memory cell according to an embodiment.

FIG. 17 is a circuit diagram illustrating a configuration example of a memory cell as a TCAM cell according to another embodiment.

FIG. 18 is a diagram showing, in a table form, the correspondence relation between the data held by each of a data cell and a mask data cell, and the data in the memory cell in FIG. 17 .

FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device according to another embodiment.

FIG. 20 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, a contact hole, and a first layer metal interconnection in the memory cell as a TCAM cell according to another embodiment.

FIG. 21 is a block diagram illustrating a configuration example of a semiconductor device according to an embodiment.

FIG. 22 is a circuit diagram illustrating a configuration example of a memory cell in the semiconductor device.

FIG. 23 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, a contact hole, and a first layer metal interconnection in the memory cell arranged in the semiconductor device.

FIG. 24 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIG. 25 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIG. 26 is a circuit diagram illustrating a configuration example of a memory cell according to a modification of the third embodiment.

FIG. 27 is a block diagram illustrating a configuration example of a semiconductor device according to the modification of the third embodiment.

FIG. 28 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, a contact hole, and a first layer metal interconnection in the memory cell according to the modification of the third embodiment.

FIG. 29 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIG. 30 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in the memory cell arranged in the semiconductor device.

FIGS. 31A to 31C each are a diagram showing the structure of a transistor.

FIG. 32 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, and a local interconnection in a memory cell according to the fourth embodiment.

FIG. 33 is a plan view showing an arrangement of a via 0 , a local interconnection, and a first layer metal interconnection layer in the memory cell according to the fourth embodiment.

FIG. 34 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in the memory cell according to the fourth embodiment.

FIG. 35 is a circuit diagram illustrating a configuration example of a memory cell in a semiconductor device according to the fifth embodiment.

FIG. 36 is a diagram illustrating a metal interconnection pattern in each memory cell forming the semiconductor device according to the fifth embodiment.

FIG. 37 is a plan view showing an arrangement of a well, a diffusion region, a polysilicon, and a local interconnection in the memory cell according to the fifth embodiment.

FIG. 38 is a plan view showing an arrangement of a via 0 , a local interconnection, and a first layer metal interconnection layer in the memory cell according to the fifth embodiment.

FIG. 39 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in the memory cell according to the fifth embodiment.

FIG. 40 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection, and a third layer metal interconnection in the memory cell according to the fifth embodiment.

FIG. 41 is a plan view showing an arrangement of a via 3 , a third layer metal interconnection, and a fourth layer metal interconnection in the memory cell according to the fifth embodiment.

Each embodiment will be hereinafter described in detail with reference to the accompanying drawings. In the following description, the same components are designated by the same reference characters. Names and functions thereof are also the same. Accordingly, the detailed description thereof will not be repeated.

[First Embodiment]

(Configuration Example of Semiconductor Device)

FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device 100 according to an embodiment. Referring to FIG. 1 , semiconductor device 100 includes a row decoder 102 , search drivers 104 A, 104 B, 106 A, 106 B, read/write circuits 108 , 110 , pre-charging & encoding circuits 112 A, 112 B, and memory cells MC 0 # 0 to MC 1 # 1 (MC 0 # 0 , MC 0 # 1 , MC 1 # 0 , MC 1 # 1 ) forming a memory array. In this case, # 0 to # 1 each are an address number referred to as an entry. For example, # 0 shows the 0 th address number, at which two BCAM cells in memory cell MC 0 # 0 and memory cell MC 1 # 0 are simultaneously accessed during the data reading and writing operations.

The memory array shown in FIG. 1 is configured in a two-column, two-row arrangement for the sake of simple description. The configuration of the memory cell to which the technique disclosed in the present specification is applied is not limited to this configuration.

Row decoder 102 activates one word line of word lines WL 0 and WL 1 according to the input address signal (not shown).

Search driver 104 A drives a search line SLA 0 to the level corresponding to an A-port search data signal S 0 (A), and drives a search line /SLA 0 to its inverted level. Search driver 104 B drives a search line SLB 0 to the level corresponding to a B-port search data signal S 0 (B), and drives a search line /SLB 0 to its inverted level. Search driver 106 A drives a search line SLA 1 to the level corresponding to an A-port search data signal S 1 (A), and drives a search line /SLA 1 to its inverted level. Search driver 106 B drives a search line SLB 1 to the level corresponding to a B-port search data signal S 1 (B), and drives a search line /SLB 1 to its inverted level.

In a certain aspect, read/write circuit 108 amplifies the data (electric potential) read onto a bit line pair BL 0 , /BL 0 by a sense amplifier (not shown), and then reads the amplified data. Thereby, read/write circuit 108 reads the data from each memory cell connected to bit line pair BL 0 , /BL 0 . In another aspect, read/write circuit 108 drives bit line pair BL 0 , /BL 0 according to input data DIO 0 by a writing driver (not shown). Thereby, read/write circuit 108 writes data onto each memory cell connected to bit line pair BL 0 , /BL 0 and having word lines activated therein. Similar to read/write circuit 108 , read/write circuit 110 also amplifies the data read onto bit line pair BL 1 , /BL 1 by a sense amplifier (not shown) in a certain aspect, and then drives bit line pair BL 1 , /BL 1 according to input data DIO 1 by a writing driver (not shown) in another aspect.

Pre-charging & encoding circuit 112 A pre-charges A-port match lines MLA 0 , MLA 1 , and also encodes the search results output through match lines MLA 0 , MLA 1 . Pre-charging & encoding circuit 112 B pre-charges B-port match lines MLB 0 , MLB 1 , and also encodes the search results output through match lines MLB 0 , MLB 1 . In a certain aspect, pre-charging & encoding circuits 112 A and 112 B pre-charge the match line connected thereto to an “H” level.

Each of memory cells MC 0 # 0 to MC 1 # 1 is configured to be capable of holding 1-bit storage data. The storage data is a target data to be compared with the search data.

To each memory cell, one word line, one set of bit line pair, two sets of search line pairs, and two match lines are connected. For example, memory cell MC 0 # 0 is connected to word line WL 0 , bit line pair BL 0 , /BL 0 , search line pair SLA 0 , /SLA 0 and search line pair SLB 0 , /SLB 0 , and match lines MLA 0 , MLB 0 .

To memory cells MC 0 # 0 and MC 0 # 1 on the first column, bit line pair BL 0 , /BL 0 , search line pair SLA 0 , /SLA 0 and search line pair SLB 0 , /SLB 0 are connected in common. To memory cells MC 1 # 0 and MC 1 # 1 on the second column, bit line pair BL 1 , /BL 1 , search line pair SLA 1 , /SLA 1 and search line pair SLB 1 , /SLB 1 are connected in common.

To memory cells MC 0 # 0 and MC 1 # 0 corresponding to the first row (address # 0 ), word line WL 0 and match lines MLA 0 , MLB 0 are connected in common. To memory cells MC 0 # 1 and MC 1 # 1 corresponding to the second row (address # 1 ), word line WL 1 and match lines MLA 1 , MLB 1 are connected in common.

(Circuit Configuration of Memory Cell)

FIG. 2 is a circuit diagram illustrating a configuration example of memory cell MC 0 # 0 according to an embodiment.

Referring to FIG. 2 , memory cell MC 0 # 0 includes a data cell DC 0 capable of holding 1-bit information and configured of: a metal oxide semiconductor (NMOS) transistors NA 0 , NA 1 each serving as an access transistor; NMOS transistors ND 0 , ND 1 each serving as a driver transistor; and PMOS transistors P 0 , P 1 . In a certain aspect, semiconductor device 100 may function as a binary content addressable memory (BCAM).

Memory cell MC 0 # 0 further includes: a bit line pair BL 0 , /BL 0 extending in a column direction (the longitudinal direction in FIG. 2 ); a word line WL 0 extending in the row direction orthogonal to the direction in which the bit line pair extends; a search line pair SLA 0 , /SLA 0 extending in the column direction and through which A-port search data is transmitted; and a search line pair SLB 0 , /SLB 0 extending in the column direction and through which B-port search data is transmitted.

Memory cell MC 0 # 0 includes: match lines MLA 0 , MLB 0 extending in the row direction (the lateral direction in FIG. 2 ); a logical operation cell LCA 0 configured to output a result to match line MLA 0 , the result being obtained based on the information held in the data cell and the A-port search data; and a logical operation cell LCB 0 configured to output a result to match line MLB 0 , the result being obtained based on the information held in the data cell and the B-port search data.

NMOS transistor NA 0 is connected between a storage node A 0 and a bit line BL 0 , and has a gate to which word line WL 0 is connected. NMOS transistor NA 1 is connected between a storage node A 1 and a bit line /BL 0 , and has a gate to which word line WL 0 is connected. PMOS transistor P 0 is connected between storage node A 0 and a power supply line VDD as a power supply potential, and has a gate connected to storage node A 1 . NMOS transistor ND 0 is connected between storage node A 0 and a power supply line VSS as a ground potential, and has a gate connected to storage node A 1 . PMOS transistor P 1 is connected between power supply line VDD and storage node A 1 , and has a gate connected to storage node A 0 . NMOS transistor ND 1 is connected between storage node A 1 and power supply line VSS, and has a gate connected to storage node A 0 .

NMOS transistor ND 0 and PMOS transistor P 0 form an inverter. NMOS transistor ND 1 and PMOS transistor P 1 also form an inverter. One of the inverters has an output connected to an input of the other inverter. Accordingly, a flip-flop formed by NMOS transistors ND 0 and ND 1 and PMOS transistors P 0 and P 1 holds 1-bit information.

Logical operation cell LCA 0 includes NMOS transistors NS 0 , NS 1 , NS 2 , and NS 3 . Logical operation cell LCB 0 includes NMOS transistors NS 4 , NS 5 , NS 6 , and NS 7 .

NMOS transistors NS 0 and NS 1 are connected in series between match line MLA 0 and power supply line VSS as a ground potential. Also, NMOS transistors NS 0 and NS 1 have gates to which search line SLA 0 and storage node A 0 are respectively connected. NMOS transistors NS 2 and NS 3 are connected in series between match line MLA 0 and power supply line VSS. Also, NMOS transistors NS 2 and NS 3 have gates to which search line /SLA 0 and storage node A 1 are respectively connected.

NMOS transistors NS 4 and NS 5 are connected in series between match line MLB 0 and power supply line VSS. Also, NMOS transistors NS 4 and NS 5 have gates to which search line SLB 0 and storage node A 0 are respectively connected. NMOS transistors NS 6 and NS 7 are connected in series between match line MLB 0 and power supply line VSS. Also, NMOS transistors NS 6 and NS 7 have gates to which search line /SLB 0 and storage node A 1 are respectively connected.

To each of memory cells other than memory cell MC 0 # 0 in FIG. 1 , a word line, a match line, a bit line pair, and a search line pair that are different from those in the above-described example are connected, but the inner circuit configuration is the same as that of memory cell MC 0 # 0 , and therefore, the description thereof will not be repeated.

(Writing Operation)

Then, the operation performed on the memory cell at address # 0 will be hereinafter described with reference to FIGS. 1 and 2 .

Row decoder 102 activates word line WL 0 to an “H” level when data is written at address # 0 , and deactivates other word lines (that is, word line WL 1 ) to an “L” level. Then, read/write circuit 108 drives bit line BL 0 to the level corresponding to input data DIO 0 , and drives bit line BL 0 to its inverted level. Read/write circuit 110 drives bit line BL 1 to the level corresponding to input data DIO 1 , and drives bit line BL 1 to its inverted level. At this time, each of the search line pairs is set at the “L” level. Each of match lines does not have to be set at a particular level, but preferably set at the pre-charged “H” level.

In the example shown in FIG. 2 , the data (level) held at storage node A 1 is assumed to be data held by memory cell MC 0 # 0 . More specifically, when storage node A 1 is “1” (at the “H” level), and when storage node A 0 is “0” (at the “L” level), memory cell MC 0 # 0 holds data “1”. On the other hand, when storage node A 1 is “0”, and when storage node A 0 is “1”, memory cell MC 0 # 0 holds data “0”.

By way of example, when data “1” is written onto memory cell MC 0 # 0 , row decoder 102 first activates word line WL 0 to an “H” level. Then, read/write circuit 108 activates bit line BL 0 to an “H” level, and deactivates bit line BL 0 to an “L” level.

By performing the above-described operations, semiconductor device 100 can write the input data onto the memory cell at address # 0 . When the data is read, the potential difference on the bit line is amplified by a sense amplifier (not shown), and the data held in each memory cell is read.

(Search Operation)

Then, the operation during data search will be hereinafter described. When data is searched for, the search data input into each search line pair and the entry data at each of a plurality of addresses # 0 to # 1 are collectively compared with each other. Then, the comparison result showing whether each entry data matches the search data or not is output in one cycle. At this time, word lines WL 0 and WL 1 each are set at an “L” level. Bit lines BL 0 and BL 1 each are preferably set at an “H” level.

According to the configuration of memory cell MC 0 # 0 as described above, when the A-port search data is “1” (that is, search line SLA 0 is “1” and search line /SLA 0 is “0”), and when the data in memory cell MC 0 # 0 is “0” (storage node A 1 is “0” and storage node A 0 is “1”), NMOS transistors NS 0 and NS 1 are brought into an ON state, and the electric potential on match line MLA 0 becomes a ground potential. When the A-port search data is “0” (that is, search line SLA 0 is “0” and search line /SLA 0 is “1”), and when the data in memory cell MC 0 # 0 is “1” (storage node A 1 is “1” and storage node A 0 is “0”), NMOS transistors NS 2 and NS 3 are brought into an ON state, and the electric potential on match line MLA 0 becomes a ground potential. In other words, when the A-port search data does not match the data in memory cell MC 0 # 0 , the electric potential on match line MLA 0 becomes a ground potential.

On the other hand, when the A-port search data is “1” and the data in memory cell MC 0 # 0 is “1”, or when the A-port search data is “0” and the data in memory cell MC 0 # 0 is “0” (that is, the A-port search data matches the data in memory cell MC 0 # 0 ), the electric potential on the pre-charged match line MLA 0 is maintained.

As described above, the electric charge stored on match line MLA 0 is extracted unless the data in each of memory cells (memory cells MC 0 # 0 and MC 1 # 0 ) connected to match line MLA 0 matches the corresponding A-port search data.

According to the above description, logical operation cell LCA 0 includes: a first logic unit formed by NMOS transistors NS 0 and NS 1 ; and a second logic unit formed by NMOS transistors NS 2 and NS 3 . The first logic unit drives match line MLA 0 based on the result of comparison between the information held in mask data cell MDC 0 and the information transmitted through search line SLA 0 . The second logic unit drives match line MLA 0 based on the result of comparison between the information held in data cell DC 0 and the information transmitted through search line /SLA 0 .

Since the behavior of match line MLB 0 is the same as that of match line MLA 0 as described above, the description thereof will not be repeated.

According to the above description, semiconductor device 100 in an embodiment includes an A-port search line pair, a match line and a logical operation cell, and independently therefrom, a B-port search line pair, a match line and a logical operation cell. Thereby, semiconductor device 100 can simultaneously search for the A-port search data and the B-port search data in one cycle. Thus, when there are a plurality of search targets, semiconductor device 100 can implement the searching speed that is twice as high as that of a single-port search device (a BCAM device).

In addition, this semiconductor device 100 searches for the A-port search data and the B-port search data using a common memory array. Accordingly, semiconductor device 100 can be suppressed from being increased in size.

Furthermore, the search device performs a search at the timing according to a clock signal generated by a clock generation circuit (generally not shown). In this regard, since the conventional search device has only one search port, it has to generate a clock signal twice in order to search for two pieces of search data. On the other hand, this semiconductor device 100 only has to generate a clock signal once in order to search for two pieces of search data. Accordingly, this semiconductor device 100 can suppress the power consumption in the clock generation circuit as compared with the conventional case.

(Layout of Memory Cell)

The following is an explanation about memory cell MC 0 # 0 in the layout configuration divided in the stacking direction by way of example with reference to FIGS. 3 to 5 .

FIG. 3 is a plan view showing an arrangement of a well, a diffusion region DF, a polysilicon PO, a contact hole CT, and a first layer metal interconnection in memory cell MC 0 # 0 arranged in semiconductor device 100 . In FIG. 3 , one polysilicon is representatively designated by a symbol P 0 and one diffusion region is representatively designated by a symbol DF. In the example shown in FIG. 3 , the gate of the transistor is made of polysilicon, but the material of the gate is not limited to polysilicon. In another aspect, the gate may be made using metal. In this case, it is preferable that the gate insulating film disposed below a gate made of metal (metal gate) is formed using a High-k material (for example, hafnium oxide) having a high dielectric constant (relative dielectric constant). These conditions are the same also in the figures, which will be described below.

As shown in FIG. 3 , polysilicon (PO) forming a gate of each transistor extends in the row direction while each of the plurality of wells forming a memory cell extends in the column direction. Accordingly, each gate and each well extend in the direction orthogonal to each other. Furthermore, each well is formed so as to be continuous to the corresponding well in the memory cell (memory cell MC 0 # 1 ) that is adjacent thereto in the column direction.

In memory cell MC 0 # 0 , a P well PW 0 having a P type conductivity type, an N well NW 0 having an N-type conductivity type, and a P well PW 1 are sequentially formed in this order in the direction in which word line WL 0 extends (in the row direction). A transistor forming data cell DC 0 is arranged in a region in which P well PW 0 and N well NW 0 are provided. More specifically, PMOS transistors P 0 and P 1 are arranged in N well NW 0 , and NMOS transistors NA 0 , NA 1 , ND 0 , and ND 1 are arranged in P well PW 0 .

NMOS transistors NS 0 to NS 7 for data search are arranged in P well PW 1 . More specifically, two N type diffusion layers DF are formed in P well PW 1 . Transistors NS 0 to NS 3 forming logical operation cell LCA 0 are arranged in one diffusion layer DF while transistors NS 4 to NS 7 forming logical operation cell LCB 0 are arranged in the other diffusion layer DF.

NMOS transistor NA 0 has a source and a drain formed by a pair of N-type diffusion regions FL 302 , FL 304 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 2 to word line WL 0 formed on the upper metal interconnection layer. N-type diffusion region FL 302 is electrically connected through a contact hole CT 6 to bit line BL 0 formed on the upper metal interconnection layer.

NMOS transistor ND 0 has a source and a drain formed by a pair of N-type diffusion regions FL 304 , FL 306 , and also has a polysilicon gate disposed therebetween. N-type diffusion region FL 306 is electrically connected through a contact hole CT 8 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistor ND 1 has a source and a drain formed by a pair of N-type diffusion regions FL 306 , FL 308 , and also has a polysilicon gate disposed therebetween.

NMOS transistor NA 1 has a source and a drain formed by a pair of N-type diffusion regions FL 308 , FL 310 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 4 to word line WL 0 formed on the upper metal interconnection layer. N-type diffusion region FL 310 is electrically connected through a contact hole CT 12 to bit line /BL 0 formed on the upper metal interconnection layer.

PMOS transistor P 0 has a source and a drain formed by a pair of P-type diffusion regions FL 312 , FL 314 , and also has a gate made of polysilicon and disposed therebetween. N-type diffusion region FL 304 , the gate of NMOS transistor ND 1 , and P-type diffusion region FL 312 are connected through contact holes CTB, CT 16 , and CT 18 , respectively, to the common first layer metal interconnection. Thus, these elements are electrically connected to each other. P-type diffusion region FL 314 is electrically connected through a contact hole CT 20 to power supply line VDD formed on the upper metal interconnection layer.

PMOS transistor P 1 has a source and a drain formed by a pair of P-type diffusion regions FL 314 , FL 316 , and also has a gate made of polysilicon and disposed therebetween. N-type diffusion region FL 308 , the gate of NMOS transistor ND 0 , and P-type diffusion region FL 316 are connected through contact holes CT 10 , CT 14 , and CT 22 , respectively, to the common first layer metal interconnection. Thus, these elements are electrically connected to each other.

NMOS transistor NS 2 has a source and a drain formed by a pair of N-type diffusion regions FL 318 , FL 320 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 24 to search line /SLA 0 formed on the upper metal interconnection layer. N-type diffusion region FL 318 is electrically connected through a contact hole CT 28 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistor NS 3 has a source and a drain formed by a pair of N-type diffusion regions FL 320 , FL 322 , and also has a polysilicon gate disposed therebetween. N-type diffusion region FL 322 is electrically connected through a contact hole CT 30 to match line MLA 0 formed on the upper metal interconnection layer.

NMOS transistor NS 1 has a source and a drain formed by a pair of N-type diffusion regions FL 322 , FL 324 , and also has a polysilicon gate disposed therebetween.

NMOS transistor NS 0 has a source and a drain formed by a pair of N-type diffusion regions FL 324 , FL 326 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 26 to search line SLA 0 formed on the upper metal interconnection layer. N-type diffusion region FL 326 is electrically connected through a contact hole CT 32 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistor NS 6 has a source and a drain formed by a pair of N type diffusion regions FL 328 , FL 330 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 40 to a search line /SLB 0 formed on the upper metal interconnection layer. N type diffusion region FL 328 is electrically connected through a contact hole CT 34 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistor NS 7 has a source and a drain formed by a pair of N type diffusion regions FL 330 , FL 332 , and also has a polysilicon gate disposed therebetween. N type diffusion region FL 332 is electrically connected through a contact hole CT 36 to match line MLB 0 formed on the upper metal interconnection layer.

NMOS transistor NS 5 has a source and a drain formed by a pair of N type diffusion regions FL 332 , FL 334 , and also has a polysilicon gate disposed therebetween.

NMOS transistor NS 4 has a source and a drain formed by a pair of N type diffusion regions FL 334 , FL 336 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 42 to search line SLB 0 formed on the upper metal interconnection layer. N type diffusion region FL 336 is electrically connected through a contact hole CT 38 to power supply line VSS formed on the upper metal interconnection layer.

The gate of NMOS transistor ND 0 , the gate of PMOS transistor P 0 , the gate of NMOS transistor NS 3 , and the gate of NMOS transistor NS 7 are formed by common polysilicon.

The gate of NMOS transistor ND 1 , the gate of PMOS transistor P 1 , the gate of NMOS transistor NS 1 , and the gate of NMOS transistor NS 5 are formed by common polysilicon.

NMOS transistors NA 0 , ND 0 , ND 1 , and NA 1 are arranged in the common N type diffusion layer. PMOS transistors P 0 and P 1 are arranged in the common P type diffusion layer.

Each N type diffusion region is formed by pouring N type impurities into active regions of P wells PW 0 and PW 1 . Each P type diffusion region is formed by pouring P type impurities into the active region of N well NW 0 .

As described above, the memory cell forming semiconductor device 100 has a configuration in which NMOS transistors NS 0 to NS 7 for data search are arranged in two N type diffusion layers DF. Generally, the BCAM has a configuration in which transistors for data search are arranged in one diffusion layer DF. Thus, in the memory array forming semiconductor device 100 , the physical distance of the memory cells arranged adjacent to each other in the row direction is slightly longer than that of a generally-used BCAM. Thereby, semiconductor device 100 can reduce the probability of occurrence of a multi bit error. A multi bit error is a phenomenon in which the data held by a plurality of cells arranged in the row direction is inverted by cosmic rays such as an α ray and a neutron ray.

FIG. 4 is a plan view showing an arrangement of via 1 , the first layer metal interconnection layer, and the second layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 100 . Through via 1 , the first layer metal interconnection and the second layer metal interconnection are connected. In FIG. 4 , second layer metal interconnections M 202 to M 224 are arranged in the column direction.

The gate of NMOS transistor NA 0 and the gate of NMOS transistor NA 1 are connected through contact holes CT 2 and CT 4 , respectively, to different first layer metal interconnections. Each of these first layer metal interconnections are connected through a corresponding one of a via 1 V 102 and a via 1 V 104 to common second layer metal interconnection M 202 that forms word line WL 0 .

N-type diffusion region FL 306 forming sources of NMOS transistors ND 0 and ND 1 is connected through contact hole CT 8 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 106 to second layer metal interconnection M 204 that forms power supply line VSS.

N-type diffusion region FL 302 forming a source of NMOS transistor NA 0 is connected through a contact hole CT 6 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 108 to second layer metal interconnection M 206 that forms bit line BL 0 .

N-type diffusion region FL 310 forming a source of NMOS transistor NA 1 is connected through a contact hole CT 10 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 110 to second layer metal interconnection M 208 that forms bit line BL 0 .

P type diffusion region FL 314 forming sources of PMOS transistors P 0 and P 1 is connected through a contact hole CT 20 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 112 to second layer metal interconnection M 210 that forms power supply line VDD.

The gate of NMOS transistor NS 0 is connected through a contact hole CT 26 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 114 to second layer metal interconnection M 212 that forms search line SLA 0 .

N type diffusion region FL 322 forming sources of NMOS transistors NS 1 and NS 3 is connected through a contact hole CT 30 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 116 to second layer metal interconnection M 214 that forms match line MLA 0 .

The gate of NMOS transistor NS 2 is connected through a contact hole CT 24 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 118 to second layer metal interconnection M 216 that forms search line /SLA 0 .

N type diffusion regions FL 318 and FL 328 that form sources of their respective NMOS transistors NS 2 and NS 6 are connected through their respective contact holes CT 28 and CT 34 to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 120 to second layer metal interconnection M 218 that forms power supply line VSS.

N type diffusion region FL 326 forming a source of NMOS transistor NS 0 and N type diffusion region FL 336 forming a source of NMOS transistor NS 4 are connected through contact holes CT 32 and CT 38 , respectively, to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 122 to second layer metal interconnection M 218 .

The gate of NMOS transistor NS 4 is connected through contact hole CT 42 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 124 to second layer metal interconnection M 220 that forms search line SLB 0 .

N type diffusion region FL 332 forming sources of NMOS transistors NS 5 and NS 7 is connected through contact hole CT 36 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 126 to second layer metal interconnection M 222 that forms match line MLB 0 .

The gate of NMOS transistor NS 6 is connected through contact hole CT 40 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 128 to second layer metal interconnection M 224 that forms search line /SLB 0 .

FIG. 5 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 100 . Through via 2 , the second layer metal interconnection and the third layer metal interconnection are connected. In FIG. 5 , third layer metal interconnections M 310 to M 350 are arranged in the row direction.

Second layer metal interconnection M 204 is connected through a via 2 V 220 and a via 2 V 230 to third layer metal interconnections M 310 and M 350 , respectively, that form power supply line VSS. Second layer metal interconnection 218 is connected through a via 2 V 250 and a via 2 V 260 to third layer metal interconnections M 310 and M 350 , respectively.

Second layer metal interconnection M 222 is connected through a via 2 V 270 to third layer metal interconnection M 320 that forms match line MLB 0 .

Second layer metal interconnection M 202 is connected through a via 2 V 210 to third layer metal interconnection M 330 that forms word line WL 0 .

Second layer metal interconnection M 214 is connected through a via 2 V 240 to third layer metal interconnection M 340 that forms match line MLA 0 .

Since the interconnection pattern of the metal interconnection inside memory cell MC 0 # 1 that is adjacent to memory cell MC 0 # 0 in the column direction is the same as the interconnection pattern obtained by arranging the interconnection pattern of memory cell MC 0 # 0 so as to be axisymmetrically in the row direction, the description thereof will not be repeated. In addition, the interconnection pattern of the metal interconnection inside memory cell MC 1 # 0 that is adjacent to memory cell MC 0 # 0 in the row direction may be the same as the interconnection pattern obtained by arranging the interconnection pattern of memory cell MC 0 # 0 so as to be axisymmetrically in the column direction, or may be the same as the interconnection pattern of memory cell MC 0 # 0 .

By configuring the layout as described above, a highly integrated CAM memory array can be realized with layers up to the third layer metal interconnection layer. If the number of interconnection layers can be suppressed, the manufacturing cost can be reduced.

(Modifications)

In the above-described embodiments, each transistor for data search is an NMOS transistor (NS 01 to NS 07 ). In another aspect, the semiconductor device may include a PMOS transistor as a transistor for data search.

FIG. 6 is a circuit diagram illustrating a configuration example of a memory cell MC 0 # 0 according to another embodiment. In FIG. 6 , since the same elements as those in FIG. 2 are designated by the same reference characters, the description thereof will not be repeated.

Logical operation cell LCA 0 according to another embodiment includes PMOS transistors PS 0 , PS 1 , PS 2 , and PS 3 in place of NMOS transistors NS 0 , NS 1 , NS 2 , and

NS 3 . Logical operation cell LCB 0 according to another embodiment includes PMOS transistors PS 4 , PS 5 , PS 6 , and PS 7 in place of NMOS transistors NS 4 , NS 5 , NS 6 , and NS 7 .

PMOS transistors PS 0 and PS 1 are connected in series between match line MLA 0 and power supply line VDD. Also, PMOS transistors PS 0 and PS 1 have gates to which search line SLA 0 and storage node A 0 are respectively connected. PMOS transistors PS 2 and PS 3 are connected in series between match line MLA 0 and power supply line VDD. Also, PMOS transistors PS 2 and PS 3 have gates to which search line /SLA 0 and storage node A 1 are respectively connected.

PMOS transistors PS 4 and PS 5 are connected in series between match line MLB 0 and power supply line VDD. Also, PMOS transistors PS 4 and PS 5 have gates to which search line SLB 0 and storage node A 0 are respectively connected. PMOS transistors PS 6 and PS 7 are connected in series between match line MLB 0 and power supply line VDD. Also, PMOS transistors PS 6 and PS 7 have gates to which search line /SLB 0 and storage node A 1 are respectively connected.

As to the data in memory cell MC 0 # 0 shown in FIG. 2 , data “0” is held when storage node A 1 is at the “L” level while data “1” is held when storage node A 1 is at the “H” level. In a certain aspect, as to the data in memory cell MC 0 # 0 shown in FIG. 6 , data “0” is held when storage node A 0 is at the “L” level while data “1” is held when storage node A 0 is at the “H” level.

FIG. 7 is a block diagram illustrating a configuration example of a semiconductor device 700 according to another embodiment. In FIG. 7 , since the same elements as those in FIG. 1 are designated by the same reference characters, the description thereof will not be repeated.

Memory cells MC 0 # 0 to MC 1 # 1 arranged in semiconductor device 700 each have a PMOS transistor as a transistor for data search, as shown in FIG. 6 .

Semiconductor device 700 includes search drivers 104 A, 104 B, 106 A, and 106 B each having an output terminal that is provided with an inverter Inv. Thereby, the level of each search line becomes an inverted level of the signal that is output from the search driver connected thereto.

Also, semiconductor device 700 includes pre-charging & encoding circuits 112 A and 112 B each having an input terminal that is provided with inverter Inv. Thereby, each of pre-charging & encoding circuits 112 A and 112 B receives an input of the signal of inverted level on a corresponding one of the match lines connected thereto. Each of these inverters Inv serves to invert the output level of a corresponding one of pre-charging & encoding circuits 112 A and 112 B for pre-charging each match line. In a certain aspect, each match line is pre-charged to an “L” level.

The search operation of semiconductor device 700 will be hereinafter described with reference to FIGS. 6 and 7 . When the data in memory cell MC 0 # 0 (the level at storage node A 0 ) matches the search data, the level on the match line is maintained at a pre-charged “L” level. On the other hand, when the data in memory cell MC 0 # 0 does not match the search data, the level on the match line becomes an “H” level.

The following is an explanation about the case where search data signal S 0 (A) is “1” by way of example. In this case, the level on search line SLA 0 is inverted by inverter Inv and thereby becomes an “L” level. Thus, PMOS transistor PS 0 connected to search line SLA 0 is brought into an ON state. In the above-described case, when the data in memory cell MC 0 # 0 is “0”, that is, when the data in memory cell MC 0 # 0 does not match the search data, PMOS transistor PS 1 is brought into an ON state and match line MLA 0 becomes an “H” level. On the other hand, when the data in memory cell MC 0 # 0 is “1”, that is, when the data in memory cell MC 0 # 0 matches the search data, PMOS transistor PS 1 is brought into an OFF state, and match line MLA 0 is maintained at the pre-charged “L” level.

According to the above description, the level on A-port match line MLA 0 is maintained at the “L” level when each data held by the memory cell corresponding to address # 0 matches the corresponding A-port search data, but the level on A-port match line MLA 0 becomes a level “H” when even one piece of data does not match the A-port search data. Due to the effect of inverter Inv, when each data held by the memory cell corresponding to address # 0 matches the corresponding A-port search data, pre-charging & encoding circuit 112 A receives an input of the “H” level. On the other hand, when even one piece of data does not match the A-port search data, pre-charging & encoding circuit 112 A receives an input of the “L” level. This also applies to pre-charging & encoding circuit 112 A included in the above-described semiconductor device 100 . Similarly, the behavior of pre-charging & encoding circuit 112 B included in semiconductor device 700 is the same as the behavior of pre-charging & encoding circuit 112 B included in semiconductor device 100 .

Accordingly, merely by providing an inverter at each output terminal of the search driver and at each input terminal of the pre-charging & encoding circuit, semiconductor device 700 may use a memory cell including a PMOS transistor as a transistor for data search.

In a certain aspect, a silicon germanium layer can be formed in a source region and a drain region in each of the above-described PMOS transistors PS 0 to PS 7 . This causes stress to be applied onto silicon in the adjacent channel portion, so that the lattice constant of this silicon may be increased. Consequently, the speed of the current flowing through the channel portion is raised, so that the switching speed of each of PMOS transistors PS 0 to PS 7 may be improved. In another aspect, the layers formed in the source region and the drain region in each of PMOS transistors PS 0 to PS 7 are not limited to a silicon germanium layer, but may be any element that can apply stress onto silicon of the channel portion.

FIG. 8 is a plan view showing an arrangement of a well, a diffusion region DF, a polysilicon PO, a contact hole CT, and a first layer metal interconnection in memory cell MC 0 # 0 according to another embodiment. In FIG. 8 , since the same elements as those in FIG. 3 are designated by the same reference characters, the description thereof will not be repeated.

As shown in FIG. 8 , the well configuration of memory cell MC 0 # 0 according to another embodiment is different from the well configuration of memory cell MC 0 # 0 illustrated in FIG. 3 in that it does not include P well PW 1 .

PMOS transistors PS 0 to PS 7 for data search are arranged in N well NW 0 . More specifically, three diffusion layers DF extending in the column direction are formed in N well NW 0 . In one diffusion layer DF, PMOS transistors P 0 and P 1 forming data cell DC 0 are arranged. In one diffusion layer DF, PMOS transistors PS 0 to PS 3 forming logical operation cell LCA 0 are arranged. In one diffusion layer DF, PMOS transistors PS 4 to PS 7 forming logical operation cell LCB 0 are arranged.

PMOS transistor PS 2 has a source and a drain that are formed by one pair of P type diffusion regions FL 340 , FL 342 , and also has a polysilicon gate disposed therebetween. This gate is connected through a contact hole CT 44 to the first layer metal interconnection that forms search line /SLA 0 . P type diffusion region FL 340 is connected through a contact hole CT 48 to the first layer metal interconnection that forms power supply line VDD.

PMOS transistor PS 3 has a source and a drain that are formed by one pair of P type diffusion regions FL 342 , FL 344 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 344 is connected through a contact hole CT 50 to the first layer metal interconnection that forms match line MLA 0 .

PMOS transistor PS 1 has a source and a drain that are formed by one pair of P type diffusion regions FL 344 , FL 346 , and also has a polysilicon gate disposed therebetween.

PMOS transistor PS 0 has a source and a drain that are formed by one pair of P type diffusion regions FL 346 , FL 348 , and also has a polysilicon gate disposed therebetween. This gate is connected through a contact hole CT 46 to the first layer metal interconnection that forms search line SLA 0 . P type diffusion region FL 348 is connected through a contact hole CT 52 to the first layer metal interconnection that forms power supply line VDD.

PMOS transistor PS 6 has a source and a drain that are formed by one pair of P type diffusion regions FL 350 , FL 352 , and also has a polysilicon gate disposed therebetween. This gate is connected through a contact hole CT 60 to the first layer metal interconnection that forms search line /SLB 0 . P type diffusion region FL 350 is connected through a contact hole CT 54 to the first layer metal interconnection that forms power supply line VDD.

PMOS transistor PS 7 has a source and a drain that are formed by one pair of P type diffusion regions FL 352 , FL 354 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 354 is connected through a contact hole CT 56 to the first layer metal interconnection that forms match line MLB 0 .

PMOS transistor PS 5 has a source and a drain that are formed by one pair of P type diffusion regions FL 354 , FL 356 , and also has a polysilicon gate disposed therebetween.

PMOS transistor PS 4 has a source and a drain that are formed by one pair of P type diffusion regions FL 356 , FL 358 , and also has a polysilicon gate disposed therebetween. This gate is connected through a contact hole CT 62 to the first layer metal interconnection that forms search line SLB 0 . P type diffusion region FL 358 is connected through a contact hole CT 58 to the first layer metal interconnection that forms power supply line VDD.

The gate of NMOS transistor ND 0 , the gate of PMOS transistor P 0 , the gate of PMOS transistor PS 3 , and the gate of PMOS transistor PS 7 are formed by common polysilicon.

The gate of NMOS transistor ND 1 , the gate of PMOS transistor P 1 , the gate of PMOS transistor PS 1 , and the gate of PMOS transistor PS 5 are formed by common polysilicon.

Since each of memory cells forming semiconductor device 700 does not have P well PW 1 , the number of wells in each of memory cells forming semiconductor device 700 is less by one than the number of wells in each of memory cells forming semiconductor device 100 . Accordingly, the memory cells forming semiconductor device 700 may be formed smaller in size than the memory cells forming semiconductor device 100 .

FIG. 9 is a plan view showing an arrangement of via 1 , the first layer metal interconnection layer, and the second layer metal interconnection layer in memory cell MC 0 # 0 according to another embodiment. In FIG. 9 , since the same elements as those in FIG. 4 are designated by the same reference characters, the description thereof will not be repeated.

The metal interconnection pattern in the second layer of memory cell MC 0 # 0 according to another embodiment is different from the metal interconnection pattern shown in FIG. 4 in that it includes a second layer metal interconnection M 910 in place of second layer metal interconnection M 218 .

P type diffusion region FL 340 forming a source of PMOS transistor PS 2 and P type diffusion region FL 350 forming a source of PMOS transistor PS 6 are connected through contact holes CT 48 and CT 54 , respectively, to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 121 to second layer metal interconnection M 910 that forms power supply line VDD.

P type diffusion region FL 348 forming a source of PMOS transistor PS 0 and P type diffusion region FL 358 forming a source of PMOS transistor PS 4 are connected through contact holes CT 52 and CT 58 , respectively, to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 123 to second layer metal interconnection M 910 that forms power supply line VDD.

Second Embodiment

The semiconductor device shown in the above-described embodiment may function as a dual-port BCAM device. More specifically, the semiconductor device explained in the above-described embodiment has a configuration in which a search line pair, a match line, and a logical operation cell are arranged for each port in the BCAM cell holding binary data. The following is an explanation about the semiconductor device that may function as a dual-port ternary content addressable memory (TCAM) device.

(Configuration Example of Semiconductor Device)

FIG. 10 is a block diagram illustrating a configuration example of semiconductor device 1000 according to an embodiment. In FIG. 10 , since the same elements as those in FIG. 1 are designated by the same reference characters, the description thereof will not be repeated.

Referring to FIG. 10 , semiconductor device 1000 is different from semiconductor device 100 illustrated in FIG. 1 in that two sets of bit line pairs are connected to each memory cell.

More specifically, memory cells MC 0 # 0 and MC 0 # 1 arranged in the column direction are connected to common bit line pairs BL 0 , /BL 0 , and BL 1 , /BL 1 . Memory cells MC 1 # 0 and MC 1 # 1 are connected to common bit line pairs BL 2 , /BL 2 , and BL 3 , /BL 3 .

(Circuit Configuration of Memory Cell)

FIG. 11 is a circuit diagram illustrating a configuration example of memory cell MC 0 # 0 arranged in semiconductor device 1000 .

Referring to FIG. 11 , memory cell MC 0 # 0 arranged in semiconductor device 1000 includes: a data cell DC 0 configured to be capable of holding 1-bit storage data; and a mask data cell MDC 0 configured to be capable of holding other 1-bit data that is independent of the 1-bit information held by data cell DC 0 . Data cell DC 0 and mask data cell MDC 0 are arranged adjacent to each other in the row direction.

Memory cell MC 0 # 0 further includes a bit line pair BL 0 , /BL 0 and a bit line pair BL 1 , /BL 1 extending in the column direction.

Mask data cell MDC 0 is formed by NMOS transistors NA 0 , NA 1 , ND 0 , and ND 1 , and PMOS transistors P 0 and P 1 .

NMOS transistor NA 0 is connected between a storage node m 1 and a bit line BL 0 , and has a gate to which word line WL 0 is connected. NMOS transistor NA 1 is connected between a storage node /m 1 and a bit line /BL 0 , and has a gate to which word line WL 0 is connected. PMOS transistor P 0 is connected between a power supply line VDD and storage node m 1 , and has a gate connected to storage node /m 1 . NMOS transistor ND 0 is connected between storage node m 1 and power supply line VSS, and has a gate connected to storage node /m 1 . PMOS transistor P 1 is connected between power supply line VDD and storage node /m 1 , and has a gate connected to storage node m 1 . NMOS transistor ND 1 is connected between storage node /m 1 and power supply line VSS, and has a gate connected to storage node m 1 .

NMOS transistor ND 0 and PMOS transistor P 0 form an inverter. NMOS transistor ND 1 and PMOS transistor P 1 also form an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop formed by NMOS transistors ND 0 and ND 1 and PMOS transistors P 0 and P 1 holds 1-bit information.

Data cell DC 0 is formed by NMOS transistors NA 2 and NA 3 each serving as an access transistor, NMOS transistors ND 2 and ND 3 each serving as a driver transistor, and PMOS transistors P 2 and P 3 .

NMOS transistor NA 2 is connected between storage node m 0 and bit line BL 1 , and has a gate to which word line WL 0 is connected. NMOS transistor NA 3 is connected between storage node /m 0 and bit line /BL 1 , and has a gate to which word line WL 0 is connected. PMOS transistor P 2 is connected between power supply line VDD and storage node m 0 , and has a gate connected to storage node /m 0 . NMOS transistor ND 2 is connected between storage node m 0 and power supply line VSS, and has a gate connected to storage node /m 0 . PMOS transistor P 3 is connected between power supply line VDD and storage node /m 0 , and has a gate connected to storage node m 0 . NMOS transistor ND 3 is connected between storage node /m 0 and power supply line VSS, and has a gate connected to storage node m 0 .

NMOS transistor ND 2 and PMOS transistor P 2 form an inverter. NMOS transistor ND 3 and PMOS transistor P 3 also form an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop formed by NMOS transistors ND 2 and ND 3 and PMOS transistors P 2 and P 3 holds 1-bit information (storage data).

Memory cell MC 0 # 0 further includes: a logical operation cell LCB 0 arranged adjacent to both of data cell DC 0 and mask data cell MDC 0 in the column direction; and a logical operation cell LCA 0 arranged adjacent to logical operation cell LCB 0 in the column direction.

Logical operation cell LCA 0 outputs the result to match line MLA 0 , the result being obtained based on the data held by each of data cell DC 0 and mask data cell MDC 0 and on the A-port search data. More specifically, logical operation cell LCA 0 drives match line MLA 0 depending on whether the data in data cell DC 0 (the level on storage node m 1 ) matches the A-port search data or not, and whether the data in mask data cell MDC (the level on storage node m 0 ) matches the inverted level of the A-port search data or not. Logical operation cell LCB 0 outputs the result to match line MLA 0 , the result being obtained based on the data held by each of data cell DC 0 and mask data cell MDC 0 and on the B-port search data. More specifically, logical operation cell LCB 0 drives match line MLB 0 depending on whether the data in data cell DC 0 matches the B-port search data or not, and whether the data in mask data cell MDC matches the inverted level of the B-port search data or not.

Logical operation cell LCA 0 includes NMOS transistors NS 0 to NS 3 . Logical operation cell LCB 0 includes NMOS transistors NS 4 to NS 7 .

NMOS transistors NS 0 and NS 1 are connected in series between match line MLA 0 and power supply line VSS. Also, NMOS transistors NS 0 and NS 1 have gates to which search line SLA 0 and storage node m 1 are respectively connected. NMOS transistors NS 2 and NS 3 are connected in series between match line MLA 0 and power supply line VSS. Also, NMOS transistors NS 2 and NS 3 have gates to which search line /SLA 0 and storage node m 0 are respectively connected.

NMOS transistors NS 4 and NS 5 are connected in series between match line MLB 0 and power supply line VSS. Also, NMOS transistors NS 4 and NS 5 have gates to which search line SLB 0 and storage node m 1 are respectively connected. NMOS transistors NS 6 and NS 7 are connected in series between match line MLB 0 and power supply line VSS. Also, NMOS transistors NS 6 and NS 7 have gates to which search line /SLB 0 and storage node m 0 are respectively connected.

To each of memory cells other than memory cell MC 0 # 0 in FIG. 10 , a word line, a match line, a bit line pair, and a search line pair that are different from those in the above-described example are connected, but the inner circuit configuration is the same as that of memory cell MC 0 # 0 , and therefore, the description thereof will not be repeated.

(Data in Memory Cell)

FIG. 12 is a diagram showing, in a table form, the correspondence relation between the data held by each of data cell DC 0 and mask data cell MDC 0 and the data in memory cell MC 0 # 0 in FIG. 11 .

Referring to FIGS. 11 and 12 , memory cell MC 0 # 0 can store three values of “0”, “1” and “*” (don't care) using a 2-bit SRAM cell (data cell DC 0 and mask data cell MDC 0 ). The symbol “*” (don't care) indicates that the value may be “0” or “1”.

Specifically, when “0” (“L” level) is stored in storage node m 0 of data cell DC 0 and “1” (“H” level) is stored in storage node m 1 of mask data cell MDC 0 , “0” is assumed to be stored in memory cell MC 0 # 0 . When “1” is stored in storage node m 0 of data cell DC 0 and “0” is stored in storage node m 1 of mask data cell MDC 0 , “1” is assumed to be stored in memory cell MC 0 # 0 . When “0” is stored in storage node m 0 of data cell DC 0 and “0” is stored in storage node m 1 of mask data cell MDC 0 , “*” (don't care) is assumed to be stored in memory cell MC 0 # 0 . Memory cell MC 0 # 0 is configured such that “1” is not stored simultaneously in storage node m 0 of data cell DC 0 and in storage node m 1 of mask data cell MDC 0 .

(Writing Operation)

Again referring to FIG. 11 , the operation of writing onto memory cell MC 0 # 0 will be hereinafter described. When data is written onto memory cell MC 0 # 0 , row decoder 102 activates word line WL 0 to an “H” level, and deactivates a word line other than word line WL 0 (that is, word line WL 1 ) to an “L” level. Then, read/write circuit 108 drives bit lines BL 0 and BL 1 to the level corresponding to input data DIO 0 , and drives bit lines BL 0 and BL 1 to their respective inverted levels. In this case, each of the search line pairs is set at an “L” level. Although each of the match lines does not have to be set at a specific level, but is preferably set at a pre-charged “H” level.

By way of example, when input data DIO 0 is “1”, read/write circuit 108 drives bit line BL 1 to an “H” level, drives bit line BL 1 to an “L” level, drives bit line BL 0 to an “L” level, and drives bit line BL 0 to an “H” level.

By performing the above-described operations, semiconductor device 1000 can write the input data onto each memory cell. When the data is read, the potential difference on the bit line is amplified by a sense amplifier (not shown), and the data held by each memory cell is read.

In the memory cell arranged in semiconductor device 1000 , the bit line pair to which a data cell is connected is different from the bit line pair to which a mask data cell is connected. Accordingly, in a certain aspect, while performing writing or reading data onto or from the data cells forming a memory cell, semiconductor device 1000 may write or read the data onto or from the mask data cells forming this memory cell.

(Search Operation)

The search operation will be hereinafter described. According to the above-described configuration of memory cell MC 0 # 0 , when the A-port search data is “1” (that is, search line SLA 0 is “1” and search line /SLA 0 is “0”), and when the data in memory cell MC 0 # 0 is “0” (storage node m 0 is “0” and storage node m 1 is “1”), NMOS transistors NS 0 and NS 1 are brought into an ON state, and the electric potential on match line MLA 0 becomes a ground potential. When the A-port search data is “0” (that is, search line SLA 0 is “0” and search line /SLA 0 is “1”), and when the data in memory cell MC 0 # 0 is “1” (storage node m 0 is “1” and storage node m 1 is “0”), NMOS transistors NS 2 and NS 3 are brought into an ON state, and the electric potential on match line MLA 0 becomes a ground potential. In other words, when the A-port search data does not match the data in memory cell MC 0 # 0 , the electric potential on match line MLA 0 becomes a ground potential (“L” level).

On the other hand, when the A-port search data is “1” and the data in memory cell MC 0 # 0 is “1” or “*”, or when the A-port search data is “0” and the data in memory cell MC 0 # 0 is “0” or “*” (that is, when the A-port search data matches the data in memory cell MC 0 # 0 ), the electric potential (“H” level) on pre-charged match line MLA 0 is maintained.

As described above, the electric charge stored in match line MLA 0 is extracted unless the data in each of the memory cells connected to match line MLA 0 (memory cells MC 0 # 0 and MC 1 # 0 ) matches the corresponding A-port search data.

Since the behavior of match line MLB 0 is the same as that of match line MLA 0 described above, the description thereof will not be repeated.

According to the above description, semiconductor device 1000 functioning as a TCAM device can simultaneously search for the A-port search data and the B-port search data in one cycle. Thus, when there are a plurality of search targets, semiconductor device 1000 can implement the searching speed that is twice as high as that of a single-port search device (a TCAM device).

In addition, this semiconductor device 1000 searches for the A-port search data and the B-port search data using a common memory array. Accordingly, semiconductor device 1000 can be suppressed from being increased in size.

Furthermore, in the conventional TCAM device, a clock signal has to be generated twice in order to search for two pieces of search data. On the other hand, in this semiconductor device 1000 , a clock signal only has to be generated once in order to search for two pieces of search data. Thus, this semiconductor device 1000 can suppress power consumption as compared with the conventional device.

(Layout of Memory Cell)

The following is an explanation about memory cell MC 0 # 0 arranged in semiconductor device 1000 in the layout configuration divided in the stacking direction by way of example with reference to FIGS. 13 to 15 . Since the same elements as those in FIGS. 3 to 5 are designated by the same reference characters, the description thereof will not be repeated.

FIG. 13 is a plan view showing an arrangement of a well, a diffusion region DF, a polysilicon PO, a contact hole CT, and a first layer metal interconnection in memory cell MC 0 # 0 arranged in semiconductor device 1000 .

As shown in FIG. 13 , polysilicon (PO) forming a gate of each transistor extends in the row direction while the plurality of wells forming a memory cell extend in the column direction. Thus, each gate and each well extend in the direction orthogonal to each other. Furthermore, each well in a memory cell is formed so as to be continuous to the corresponding well in the memory cell (memory cell MC 0 # 1 ) adjacent thereto in the column direction.

In memory cell MC 0 # 0 according to an embodiment, P well PW 0 having a P type conductivity type, N well NW 0 having an N type conductivity type, P well PW 1 , N well NW 1 , and P well PW 2 are formed sequentially in this order in the direction in which word line WL 0 extends (in the row direction). In a region in which N well NW 1 and P well PW 2 are provided, NMOS transistors NA 2 , NA 3 , ND 2 , ND 3 and PMOS transistors P 2 , P 3 that form data cell DC 0 are arranged. More specifically, PMOS transistors P 2 and P 3 are arranged in N well NW 1 while NMOS transistors NA 2 , NA 3 , ND 2 , and ND 3 are arranged in P well PW 2 .

PMOS transistor P 3 has a source and a drain that are formed by one pair of P type diffusion regions FL 360 and FL 362 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 362 is connected through a contact hole CT 66 to a power supply line VDD formed on the upper metal interconnection layer.

PMOS transistor P 2 has a source and a drain that are formed by one pair of P type diffusion regions FL 362 and FL 364 , and also has a polysilicon gate disposed therebetween.

NMOS transistor NA 3 has a source and a drain that are formed by one pair of N type diffusion regions FL 366 and FL 368 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 84 to word line WL 0 formed on the upper metal interconnection layer. N type diffusion region FL 366 is electrically connected through a contact hole CT 74 to bit line /BL 1 formed on the upper metal interconnection layer.

NMOS transistor ND 3 has a source and a drain that are formed by one pair of N type diffusion regions FL 368 and FL 370 , and also has a polysilicon gate disposed therebetween. N type diffusion region FL 370 is connected through a contact hole CT 78 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistor ND 2 has a source and a drain that are formed by one pair of N type diffusion regions FL 370 and FL 372 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 360 , N type diffusion region FL 368 , and the gate of NMOS transistor ND 2 are connected through contact holes CT 64 , CT 76 and CT 72 , respectively, to the common first layer metal interconnection. Thus, these elements are electrically connected to each other. P type diffusion region FL 364 , the gate of PMOS transistor P 3 , and N type diffusion region FL 372 are connected through contact holes CT 68 , CT 70 and CT 80 , respectively, to the common first layer metal interconnection. Thus, these elements are electrically connected to each other.

NMOS transistor NA 2 has a source and a drain that are formed by one pair of N type diffusion regions FL 372 and FL 374 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 86 to word line WL 0 formed on the upper metal interconnection layer. N type diffusion region FL 374 is electrically connected through a contact hole CT 82 to bit line BL 1 formed on the upper metal interconnection layer.

The gate of NMOS transistor NS 3 , the gate of NMOS transistor NS 7 , the gate of PMOS transistor P 3 , and the gate of NMOS transistor ND 3 are formed by common polysilicon.

The gate of PMOS transistor P 2 and the gate of NMOS transistor ND 2 are formed by common polysilicon.

NMOS transistors NA 0 , ND 0 , ND 1 , and NA 1 are arranged in the common N type diffusion layer. PMOS transistors P 0 and P 1 are arranged in the common P type diffusion layer. PMOS transistors P 3 and P 2 are arranged in the common P type diffusion layer. NMOS transistors NA 3 , ND 3 , ND 2 , and NA 2 are arranged in the common N type diffusion layer.

As shown in FIG. 13 , the memory cell forming semiconductor device 1000 has a configuration in which NMOS transistors NS 0 to NS 7 for data search are arranged in two N type diffusion layers DF. Generally, the TCAM device has a configuration in which a transistor for data search is arranged in one diffusion layer DF. Thus, in the memory array forming semiconductor device 1000 , the physical distance of the memory cells arranged adjacent to each other in the row direction is slightly longer than that of a commonly-used TCAM device. Thereby, semiconductor device 1000 can reduce the probability of occurrence of a multi bit error.

FIG. 14 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 1000 . In FIG. 14 , second layer metal interconnections M 202 to M 248 are arranged in the column direction.

P type diffusion region FL 362 forming sources of PMOS transistors P 3 and P 2 is connected to the first layer metal interconnection through contact hole CT 66 . This first layer metal interconnection is connected through a via 1 V 130 to second layer metal interconnection M 240 that forms power supply line VDD.

N type diffusion region FL 374 forming a source of NMOS transistor NA 2 is connected through a contact hole CT 82 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 132 to second layer metal interconnection M 242 that forms bit line BL 1 .

N type diffusion region FL 366 forming a source of NMOS transistor NA 3 is connected through a contact hole CT 74 to first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 134 to second layer metal interconnection M 244 that forms bit line /BL 1 .

N type diffusion region FL 370 forming sources of NMOS transistors ND 3 and ND 2 is connected through a contact hole CT 78 to the first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 136 to second layer metal interconnection M 246 that forms power supply line VSS.

The gate of NMOS transistor NA 3 and the gate of NMOS transistor NA 2 are connected through contact holes CT 84 and CT 86 , respectively, to different first layer metal interconnections. These first layer metal interconnections are connected through a via 1 V 138 and a via 1 V 140 , respectively, to the common second layer metal interconnection M 248 that forms word line WL 0 .

FIG. 15 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 1000 .

Second layer metal interconnection M 246 is connected through a via 2 V 275 and a via 2 V 280 to third layer metal interconnections M 310 and M 350 , respectively, that form power supply line VSS.

Second layer metal interconnection M 248 is connected through a via 2 V 285 to third layer metal interconnection M 330 that forms word line WL 0 .

By forming a layout as described above, a highly integrated TCAM memory array can be realized with layers up to the third layer metal interconnection layer. If the number of interconnection layers can be suppressed, the manufacturing cost can be reduced.

FIG. 16 is a diagram illustrating a metal interconnection pattern in a memory cell according to an embodiment. The alphabetical character “F” in the figure shows the direction of the metal interconnection pattern. By way of example, the direction of the metal interconnection pattern in memory cell MC 0 # 0 shown in each of FIGS. 13 to 15 is defined as “F”.

In this case, the metal interconnection pattern of memory cell MC 0 # 1 that is adjacent to memory cell MC 0 # 0 in the column direction represents an interconnection pattern obtained by arranging the interconnection pattern of memory cell MC 0 # 0 so as to be axisymmetrically in the row direction.

On the other hand, the metal interconnection pattern of memory cell MC 1 # 0 that is adjacent to memory cell MC 0 # 0 in the row direction represents an interconnection pattern that is the same as the interconnection pattern of memory cell MC 0 # 0 in an example shown in FIG. 16 . In another aspect, the metal interconnection pattern of memory cell MC 1 # 0 may be an interconnection pattern that is obtained by arranging the interconnection pattern of memory cell MC 0 # 0 so as to be axisymmetrically in the column direction.

(Modifications)

In semiconductor device 1000 as a TCAM device as described above, the transistor for data search is an NMOS transistor (NS 01 to NS 07 ). A TCAM device using a PMOS transistor as a transistor for data search will be hereinafter described.

FIG. 17 is a circuit diagram illustrating a configuration example of memory cell MC 0 # 0 as a TCAM cell according to another embodiment. In FIG. 17 , since the same elements as those in FIG. 11 are designated by the same reference characters, the description thereof will not be repeated.

Logical operation cell LCA 0 according to another embodiment includes PMOS transistors PS 0 , PS 1 , PS 2 , and PS 3 in place of NMOS transistors NS 0 , NS 1 , NS 2 , and NS 3 . Logical operation cell LCB 0 according to another embodiment includes PMOS transistors PS 4 , PS 5 , PS 6 , and PS 7 in place of NMOS transistors NS 4 , NS 5 , NS 6 , and NS 7 .

PMOS transistors PS 0 and PS 1 are connected in series between match line MLA 0 and power supply line VDD. Also, PMOS transistors PS 0 and PS 1 have gates to which search line SLA 0 and storage node m 1 are respectively connected. PMOS transistors PS 2 and PS 3 are connected in series between match line MLA 0 and power supply line VDD. Also, PMOS transistors PS 2 and PS 3 have gates to which search line /SLA 0 and storage node m 0 are respectively connected.

PMOS transistors PS 4 and PS 5 are connected in series between match line MLB 0 and power supply line VDD. Also, PMOS transistors PS 4 and PS 5 have gates to which search line SLB 0 and storage node m 1 are respectively connected. PMOS transistors PS 6 and PS 7 are connected in series between match line MLB 0 and power supply line VDD. Also, PMOS transistors PS 6 and PS 7 have gates to which search line /SLB 0 and storage node m 0 are respectively connected.

The relation between the data in memory cell MC 0 # 0 arranged in semiconductor device 1000 and the data held by each of data cell DC 0 and mask data cell MDC 0 is illustrated in FIG. 12 . In a certain aspect, the relation shown in FIG. 17 between the data in memory cell MC 0 # 0 and the data held by each of data cell DC 0 and mask data cell MDC 0 is different from the relation shown in FIG. 12 .

FIG. 18 is a diagram showing, in a table form, the correspondence relation between the data held by each of data cell DC 0 and mask data cell MDC 0 and the data in memory cell MC 0 # 0 in FIG. 17 .

Referring to FIG. 18 , when “1” is stored in storage node m 0 of data cell DC 0 and “0” is stored in storage node m 1 of mask data cell MDC 0 , “0” is assumed to be stored in memory cell MC 0 # 0 . When “0” is stored in storage node m 0 of data cell DC 0 and “1” is stored in storage node m 1 of mask data cell MDC 0 , “1” is assumed to be stored in memory cell MC 0 # 0 . When “1” is stored in storage node m 0 of data cell DC 0 and “1” is stored in storage node m 1 of mask data cell MDC 0 , “*” (don't care) is assumed to be stored in memory cell MC 0 # 0 . Memory cell MC 0 # 0 is configured such that “0” is not stored simultaneously in storage node m 0 of data cell DC 0 and in storage node m 1 of mask data cell MDC 0 . As described above, the TCAM cell (memory cell MC 0 # 0 ) employing a PMOS transistor as a transistor for data search may hold data in a manner opposite to the manner in which the TCAM cell employing an NMOS transistor holds data ( FIG. 12 ).

FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device 1900 according to another embodiment. In FIG. 19 , since the same elements as those in FIG. 10 are designated by the same reference characters, the description thereof will not be repeated.

Memory cells MC 0 # 0 to MC 1 # 1 arranged in semiconductor device 1900 includes a PMOS transistor as a transistor for data search, as illustrated in FIG. 17 .

Similar to semiconductor device 700 illustrated in FIG. 7 , semiconductor device 1900 includes search drivers 104 A, 104 B, 106 A, and 106 B each having an output terminal provided with an inverter Inv, and also includes pre-charging & encoding circuits 112 A and 112 B each having an input terminal provided with an inverter Inv. As a result, the level of each search line shows an electric potential at the inverted level of the signal output from the search driver connected thereto. Also, pre-charging & encoding circuits 112 A and 112 B each receive an input of the signal of an inverted level on each match line connected thereto. Also, due to the effect of inverter Inv, each match line is pre-charged to the inverted level of the signal output from the pre-charging & encoding circuit connected thereto. In a certain aspect, each match line is pre-charged to an “L” level.

The search operation of semiconductor device 1900 will be hereinafter described with reference to FIGS. 17 to 19 . When the data in memory cell MC 0 # 0 matches the search data, the level on the match line is maintained at the “L” level. On the other hand, when the data in memory cell MC 0 # 0 does not match the search data, the level on the match line becomes an “H” level.

The following is an explanation about the case where search data signal S 0 (A) is “1” by way of example. In this case, the level on search line SLA 0 is inverted by inverter Inv and becomes an “L” level. Thus, PMOS transistor PS 0 connected to search line SLA 0 is brought into an ON state. In the above-described case, when the data in memory cell MC 0 # 0 is “0”, that is, when the data in memory cell MC 0 # 0 does not match the search data, PMOS transistor PS 1 is brought into an ON state, and match line MLA 0 becomes an “H” level. On the other hand, when the data in memory cell MC 0 # 0 is “1”, that is, when the data in memory cell MC 0 # 0 matches the search data, PMOS transistor PS 1 is brought into an OFF state, and match line MLA 0 is maintained at the pre-charged “L” level.

According to the above description, due to the effect of inverter Inv, pre-charging & encoding circuit receives an input of the “H” level when the data held by each memory cell matches the corresponding search data, and receives an input of the “L” level when even one piece of data does not match the corresponding search data. This also applies to the pre-charging & encoding circuit included in semiconductor device 1000 as described above.

Therefore, merely by providing an inverter at the output terminal of each search drivers and at the input terminal of each pre-charging & encoding circuit, semiconductor device 1900 may use a memory cell including a PMOS transistor as a transistor for data search.

FIG. 20 is a plan view showing an arrangement of a well, a diffusion region DF, a polysilicon PO, a contact hole CT, and a first layer metal interconnection in memory cell MC 0 # 0 as a TCAM cell according to another embodiment. In FIG. 20 , since the same elements as those in FIGS. 8 and 13 are designated by the reference characters, the description thereof will not be repeated.

As shown in FIG. 20 , the layout of MC 0 # 0 according to another embodiment may have a configuration in which the layout of the BCAM cell shown in FIG. 8 additionally incorporates N well NW 1 , P well PW 2 and a configuration arranged on these wells that are provided in the layout of the TCAM cell shown in FIG. 13 . Since N well NW 0 shown in FIG. 8 and N well NW 1 shown in FIG. 13 are adjacent to each other, these N well NW 0 and N well NW 1 are represented as one N well NW 0 in FIG. 20 . Also, P well PW 2 shown in FIG. 13 corresponds to a P well PW 1 in FIG. 20 .

Since each of the memory cells forming semiconductor device 1900 does not have N well NW 1 and P well PW 2 , the number of wells in each of memory cells forming semiconductor device 1900 is less by two than the number of wells in each of memory cells forming semiconductor device 1000 . Accordingly, the memory cells forming semiconductor device 1900 can be reduced in size than the memory cells forming semiconductor device 1000 .

Since the interconnection patterns of the second layer metal interconnection and the third layer metal interconnection may be implemented by the same interconnection pattern as those in the examples shown in FIGS. 14 and 15 , the description thereof will not be repeated.

[Third Embodiment]

The data cell and the mask data cell forming the TCAM cell illustrated in the second embodiment are arranged adjacent to each other in the row direction, connected to the common word line, and connected to different bit line pairs. In the third embodiment, another configuration of the TCAM cell will be described. More specifically, the data cell and the mask data cell forming a TCAM cell are arranged adjacent in the column direction, connected to the common bit line pair, and connected to different word lines. The above-described configuration will be specifically described below.

FIG. 21 is a block diagram illustrating a configuration example of a semiconductor device 2100 according to an embodiment. In FIG. 21 , since the same elements as those in FIG. 10 are designated by the same reference characters, the description thereof will not be repeated.

Each of memory cells forming semiconductor device 2100 is connected to two word lines, one set of bit line pair, two sets of search line pairs, and two match lines. For example, memory cell MC 0 # 0 is connected to word lines WL 0 , WL 1 , bit line pair BL 0 , /BL 0 , search line pairs SLA 0 , /SLA 0 and SLB 0 , /SLB 0 , and match lines MLA 0 , MLB 0 .

(Circuit Configuration of Memory Cell)

FIG. 22 is a circuit diagram illustrating a configuration example of memory cell MC 0 # 0 in a semiconductor device 2100 . Referring to FIG. 22 , memory cell MC 0 # 0 includes a data cell DC 0 and a mask data cell MDC 0 , each of which is configured to be capable of holding 1-bit data. Data cell DC 0 and mask data cell MDC 0 are arranged adjacent to each other in the column direction.

Mask data cell MDC 0 is formed by NMOS transistors NA 0 , NA 1 , ND 0 , ND 1 and PMOS transistors P 0 , P 1 .

NMOS transistor NA 0 is connected between storage node m 1 and bit line BL 0 , and has a gate to which word line WL 0 is connected. NMOS transistor NA 1 is connected between storage node /m 1 and bit line /BL 0 , and has a gate to which word line WL 0 is connected. PMOS transistor P 0 is connected between power supply line VDD and storage node m 1 , and has a gate connected to storage node /m 1 . NMOS transistor ND 0 is connected between storage node m 1 and power supply line VSS, and has a gate connected to storage node /m 1 . PMOS transistor P 1 is connected between power supply line VDD and storage node /m 1 , and has a gate connected to storage node m 1 . NMOS transistor ND 1 is connected between storage node /m 1 and power supply line VSS, and has a gate connected to storage node m 1 .

NMOS transistor ND 0 and PMOS transistor P 0 form an inverter. NMOS transistor ND 1 and PMOS transistor P 1 also form an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop formed by NMOS transistors ND 0 and ND 1 and PMOS transistors P 0 and P 1 holds 1-bit information.

Data cell DC 0 is formed by NMOS transistors NA 2 , NA 3 , ND 2 , and ND 3 , and PMOS transistors P 2 and P 3 .

NMOS transistor NA 2 is connected between storage node m 0 and bit line BL 0 , and has a gate to which word line WL 1 is connected. NMOS transistor NA 3 is connected between storage node /m 0 and bit line /BL 0 , and has a gate to which word line WL 1 is connected. PMOS transistor P 2 is connected between power supply line VDD and storage node m 0 , and has a gate connected to storage node /m 0 . NMOS transistor ND 2 is connected between storage node m 0 and power supply line VSS, and has a gate connected to storage node /m 0 . PMOS transistor P 3 is connected between power supply line VDD and storage node /m 0 , and has a gate connected to storage node m 0 . NMOS transistor ND 3 is connected between storage node /m 0 and power supply line VSS, and has a gate connected to storage node m 0 .

NMOS transistor ND 2 and PMOS transistor P 2 form an inverter. NMOS transistor ND 3 and PMOS transistor P 3 also form an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop formed by NMOS transistors ND 2 and ND 3 and PMOS transistors P 2 and P 3 holds 1-bit information.

As described above, data cell DC 0 and mask data cell MDC 0 are connected to the common bit line pair BL 0 , /BL 0 . Furthermore, data cell DC 0 and mask data cell MDC 0 are connected to different word lines WL 0 and WL 1 , respectively.

Memory cell MC 0 # 0 has logical operation cells LCA 0 and LCB 0 between data cell DC 0 and mask data cell MDC 0 . Logical operation cells LCA 0 and LCB 0 are arranged adjacent to each other in the row direction.

Logical operation cell LCA 0 outputs the result to match line MLA 0 , the result being obtained based on the data held by each of data cell DC 0 and mask data cell MDC 0 , and on the A-port search data. Logical operation cell LCB 0 outputs the result to match line MLA 0 , the result being obtained based on the data held by each of data cell DC 0 and mask data cell MDC, and on the B-port search data.

Logical operation cell LCA 0 includes NMOS transistors NS 0 to NS 3 . Logical operation cell LCB 0 includes NMOS transistors NS 4 to NS 7 .

NMOS transistors NS 0 and NS 1 are connected in series between match line MLA 0 and power supply line VSS. Also, NMOS transistors NS 0 and NS 1 have gates to which search line SLA 0 and storage node m 1 are respectively connected. NMOS transistors NS 2 and NS 3 are connected in series between match line MLA 0 and power supply line VSS. Also, NMOS transistors NS 2 and NS 3 have gates to which search line /SLA 0 and storage node m 0 are respectively connected.

NMOS transistors NS 4 and NS 5 are connected in series between match line MLB 0 and power supply line VSS. Also, NMOS transistors NS 4 and NS 5 have gates to which search line SLB 0 and storage node m 1 are respectively connected. NMOS transistors NS 6 and NS 7 are connected in series between match line MLB 0 and power supply line VSS. Also, NMOS transistors NS 6 and NS 7 have gates to which search line /SLB 0 and storage node m 0 are respectively connected.

The data in memory cell MC 0 # 0 shown in FIG. 22 is assumed to be the same as the data in memory cell MC 0 # 0 shown in FIG. 12 . In other words, when storage node m 0 of data cell DC 0 is “0” and when storage node m 1 of mask data cell MDC 0 is “1”, “0” is assumed be stored in memory cell MC 0 # 0 . When storage node m 0 of data cell DC 0 is “1” and when storage node m 1 of mask data cell MDC 0 is “0”, “1” is assumed to be stored in memory cell MC 0 # 0 . When storage node m 0 of data cell DC 0 is “0” and when storage node m 1 of mask data cell MDC 0 is “0”, “*” (don't care) is assumed to be stored in memory cell MC 0 # 0 . Memory cell MC 0 # 0 is configured such that “1” is not stored simultaneously in storage node m 0 of data cell DC 0 and in storage node m 1 of mask data cell MDC 0 .

(Writing Operation)

The operation of writing data onto memory cell MC 0 # 0 shown in FIG. 22 will be hereinafter described. When data is written onto memory cell MC 0 # 0 , row decoder 102 first activates word line WL 0 to an “H” level, and deactivates other word lines (that is, word lines WL 1 to WL 3 ) to an “L” level. Then, read/write circuit 108 drives bit line BL 0 to the level corresponding to input data DIO 00 , and drives bit line /BL 0 to its inverted level. Thereby, semiconductor device 2100 writes data onto data cell DC 0 . When writing of data onto data cell DC 0 is completed, read/write circuit 108 sets the level of bit line pair BL 0 , /BL 0 at an “L” level.

Then, row decoder 102 activates word line WL 1 to an “H” level, and deactivates other word lines to an “L” level. Then, read/write circuit 108 drives bit line BL 0 to the level corresponding to input data DIO 01 , and drives bit line /BL 0 to its inverted level. Thereby, semiconductor device 2100 writes data onto mask data cell MDC 0 . When writing of data onto data cell DC 0 is completed, read/write circuit 108 sets the level of bit line pair BL 0 , /BL 0 at an “L” level. Semiconductor device 2100 performs this series of operations in two cycles. In another aspect, semiconductor device 2100 may perform writing of data onto mask data cell MDC 0 in the first one cycle, and may perform writing of data onto data cell DC 0 in the next one cycle.

(Search Operation)

Then, the search operation will be hereinafter described. According to the configuration of memory cell MC 0 # 0 as described above, when the A-port search data is “1” (that is, search line SLA 0 is “1” and search line /SLA 0 is “0”), and when the data in memory cell MC 0 # 0 is “0” (storage node m 0 is “0” and storage node m 1 is “1”), NMOS transistors NS 0 and NS 1 are brought into an ON state, so that the electric potential on pre-charged match line MLA 0 is extracted to a ground potential. When the A-port search data is “0” (that is, search line SLA 0 is “0” and search line /SLA 0 is “1”), and when the data in memory cell MC 0 # 0 is “1” (storage node m 0 is “1” and storage node m 1 is “0”), NMOS transistors NS 2 and NS 3 are brought into an ON state, so that the electric potential on pre-charged match line MLA 0 is extracted to a ground potential. In other words, when the A-port search data does not match the data in memory cell MC 0 # 0 , the electric potential on match line MLA 0 becomes an “L” level (ground potential).

On the other hand, when the A-port search data is “1” and the data in memory cell MC 0 # 0 is “1” or “*”, or when the A-port search data is “0” and the data in memory cell MC 0 # 0 is “0” or “*” (that is, the A-port search data matches the data in memory cell MC 0 # 0 ), the electric potential (“H” level) on pre-charged match line MLA 0 is maintained.

As described above, the electric charge stored in match line MLA 0 is extracted unless the data in each of the memory cells connected to match line MLA 0 (memory cells MC 0 # 0 and MC 1 # 0 ) matches the corresponding A-port search data.

Since the behavior of match line MLB 0 is the same as that of match line MLA 0 described above, the description thereof will not be repeated.

According to the above description, semiconductor device 2100 functioning as a TCAM device can simultaneously search for the A-port search data and the B-port search data in one cycle, as with semiconductor device 1000 described above. Thus, when there are a plurality of search targets, semiconductor device 2100 can implement the searching speed that is twice as high as that of a single-port search device (a TCAM device).

In addition, this semiconductor device 2100 searches for the A-port search data and the B-port search data using a common memory array. Thus, semiconductor device 2100 can be suppressed from being increased in size.

Furthermore, according to the conventional TCAM device, a clock signal has to be generated twice in order to search for two pieces of search data. On the other hand, according to this semiconductor device 2100 , a clock signal only has to be generated once in order to search for two pieces of search data. Thus, this semiconductor device 2100 can suppress power consumption as compared with the conventional device.

(Layout of Memory Cell)

The following is an explanation about memory cell MC 0 # 0 arranged in semiconductor device 2100 in the layout configuration divided in the stacking direction by way of example with reference to FIGS. 23 to 25 . Since the same elements as those in FIGS. 13 to 15 are designated by the same reference characters, the description thereof will not be repeated.

FIG. 23 is a plan view showing an arrangement of a well, a diffusion region DF, a polysilicon PO, a contact hole CT, and a first layer metal interconnection in memory cell MC 0 # 0 arranged in semiconductor device 2100 .

In memory cell MC 0 # 0 according to a certain embodiment, a P well PW 0 having a P type conductivity type, an N well NW 0 having an N type conductivity type, and a P well PW 1 are formed sequentially in this order in the row direction. In P well PW 0 , NMOS transistors NA 2 and ND 2 forming data cell DC 0 and NMOS transistors NA 0 and ND 0 forming mask data cell MDC 0 are arranged. In N well NW 0 , PMOS transistors P 0 and P 1 forming data cell DC 0 and PMOS transistors P 2 and P 3 forming mask data cell MDC 0 are arranged. In P well PW 1 , NMOS transistors NA 3 and ND 3 forming data cell DC 0 and NMOS transistors NA 1 and ND 1 forming mask data cell MDC 0 , and NMOS transistors NS 0 to NS 7 for data search are arranged.

NMOS transistor ND 2 has a source and a drain that are formed by one pair of N type diffusion regions FL 502 , FL 504 , and also has a polysilicon gate disposed therebetween. N type diffusion region FL 502 is electrically connected through a contact hole CT 406 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistor NA 2 has a source and a drain that are formed by one pair of N type diffusion regions FL 504 , FL 506 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 402 to word line WL 1 formed on the upper metal interconnection layer. N type diffusion region FL 506 is electrically connected through a contact hole CT 410 to bit line BL 0 formed on the upper metal interconnection layer.

NMOS transistor NA 0 has a source and a drain that are formed by one pair of N type diffusion regions FL 506 , FL 508 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 404 to word line WL 0 formed on the upper metal interconnection layer.

NMOS transistor ND 0 has a source and a drain that are formed by one pair of N type diffusion regions FL 508 , FL 510 , and also has a polysilicon gate disposed therebetween. N type diffusion region FL 510 is electrically connected through a contact hole CT 414 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistors ND 2 , NA 2 , NA 0 , and ND 0 are arranged in common N type diffusion layer DF.

PMOS transistor P 2 has a source and a drain that are formed by one pair of P type diffusion regions FL 512 , FL 514 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 514 and N type diffusion region FL 504 are connected through a contact hole CT 418 and a contact hole CT 408 , respectively, to the common first layer metal interconnection. Furthermore, contact hole CT 418 is provided also in the gate of PMOS transistor P 3 described later. Thus, P type diffusion region FL 514 , N type diffusion region FL 504 , and the gate of PMOS transistor P 3 are electrically connected to each other. P type diffusion region FL 512 is electrically connected through a contact hole CT 416 to power supply line VDD formed on the upper metal interconnection layer.

PMOS transistor P 0 has a source and a drain that are formed by one pair of P type diffusion regions FL 513 , FL 515 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 513 and N type diffusion region FL 508 are connected through a contact hole CT 420 and a contact hole CT 412 , respectively, to the common first layer metal interconnection. Furthermore, contact hole CT 420 is provided also in the gate of PMOS transistor P 1 described later. Thus, P type diffusion region FL 513 , N type diffusion region FL 508 and the gate of PMOS transistor P 1 are electrically connected to each other. P type diffusion region FL 515 is electrically connected through a contact hole CT 422 to power supply line VDD formed on the upper metal interconnection layer.

PMOS transistor P 3 has a source and a drain that are formed by one pair of P type diffusion regions FL 516 , FL 518 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 516 and the gate of PMOS transistor P 2 are electrically connected to each other through a common contact hole CT 424 . P type diffusion region FL 516 and N type diffusion region FL 524 that forms a drain of NMOS transistor NA 3 described later are connected through contact holes CT 424 and CT 432 , respectively, to the common first layer metal interconnection. Thus, P type diffusion region FL 516 , the gate of PMOS transistor P 2 and N type diffusion region FL 524 are electrically connected to each other. P type diffusion region FL 518 is electrically connected through a contact hole CT 426 to power supply line VDD formed on the upper metal interconnection layer.

PMOS transistor P 1 has a source and a drain that are formed by one pair of P type diffusion regions FL 518 , FL 520 , and also has a polysilicon gate disposed therebetween. P type diffusion region FL 520 and the gate of PMOS transistor P 0 are electrically connected to each other through a common contact hole CT 428 . P type diffusion region FL 520 and N type diffusion region FL 528 that forms a drain of NMOS transistor NA 1 described later are connected through contact holes CT 428 and CT 436 , respectively, to the common first layer metal interconnection. Thus, P type diffusion region FL 520 , the gate of PMOS transistor P 0 and N type diffusion region FL 528 are electrically connected to each other. PMOS transistors P 3 and P 1 are arranged in common P type diffusion layer DF.

NMOS transistor NA 3 has a source and a drain that are formed by one pair of N type diffusion regions FL 522 , FL 524 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 440 to word line WL 1 formed on the upper metal interconnection layer. N type diffusion region FL 522 is electrically connected through a contact hole CT 430 to bit line /BL 0 formed on the upper metal interconnection layer.

NMOS transistor ND 3 has a source and a drain that are formed by one pair of N type diffusion regions FL 524 , FL 526 , and also has a polysilicon gate disposed therebetween. N type diffusion region FL 526 is electrically connected through a contact hole CT 434 to power supply line VSS formed on the upper metal interconnection layer.

NMOS transistor ND 1 has a source and a drain that are formed by one pair of N type diffusion regions FL 526 , FL 528 , and also has a polysilicon gate disposed therebetween.

NMOS transistor NA 1 has a source and a drain that are formed by one pair of N type diffusion regions FL 528 , FL 530 , and also has a polysilicon gate disposed therebetween. This gate is electrically connected through a contact hole CT 442 to word line WL 0 formed on the upper metal interconnection layer. N type diffusion region FL 530 is electrically connected through a contact hole CT 438 to bit line /BL 0 formed on the upper metal interconnection layer.

As described above, since each of memory cells forming semiconductor device 2100 does not include N well NW 1 and P well PW 2 , the number of wells in each of memory cells forming semiconductor device 2100 is less by two than the number of wells in each of memory cells forming semiconductor device 1000 described with reference to FIG. 13 . Thus, the memory cells forming semiconductor device 2100 may be further reduced in size than the memory cells forming semiconductor device 1000 .

FIG. 24 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 2100 .

The gate of NMOS transistor NA 2 is connected through a contact hole CT 402 , the first layer metal interconnection and a via 1 V 150 to second layer metal interconnection M 260 forming word line WL 1 .

The gate of NMOS transistor NA 0 is connected through a contact hole CT 404 , the first layer metal interconnection and a via 1 V 152 to second layer metal interconnection M 262 forming word line WL 0 .

N type diffusion region FL 502 forming a source of NMOS transistor ND 2 and N type diffusion region FL 510 forming a source of NMOS transistor ND 0 are connected through contact holes CT 406 and CT 414 , respectively, to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 154 and a via 1 V 156 to second layer metal interconnection M 264 forming power supply line VSS.

N type diffusion region FL 506 forming sources of NMOS transistors NA 2 and NA 0 is connected through contact hole CT 410 , the first layer metal interconnection and a via 1 V 158 to second layer metal interconnection M 266 forming bit line BL 0 .

P type diffusion region FL 512 forming a source of PMOS transistor P 2 is connected through contact hole CT 416 , the first layer metal interconnection and a via 1 V 160 to second layer metal interconnection M 268 forming power supply line VDD. P type diffusion region FL 518 forming sources of PMOS transistors P 3 and P 1 is connected through contact hole CT 426 , the first layer metal interconnection and a via 1 V 161 to second layer metal interconnection M 268 . P type diffusion region FL 515 forming a source of PMOS transistor P 0 is connected through contact hole CT 422 , the first layer metal interconnection and a via 1 V 162 to second layer metal interconnection M 268 .

N type diffusion region FL 522 forming a source of NMOS transistor NA 3 and N type diffusion region FL 530 forming a source of NMOS transistor NA 1 are connected through contact hole CT 430 and contact hole CT 438 , respectively, to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 164 and a via 1 V 166 to second layer metal interconnection M 270 forming bit line BL 0 .

N type diffusion region FL 526 forming sources of NMOS transistors ND 3 and ND 1 is connected through contact hole CT 434 , the first layer metal interconnection and a via 1 V 168 to second layer metal interconnection M 272 forming power supply line VSS.

The gate of NMOS transistor NA 3 is connected through contact hole CT 440 , the first layer metal interconnection and a via 1 V 170 to second layer metal interconnection M 274 forming word line WL 1 .

The gate of NMOS transistor NA 1 is connected through contact hole CT 442 , the first layer metal interconnection and a via 1 V 172 to second layer metal interconnection M 276 forming word line WL 0 .

FIG. 25 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 2100 . In FIG. 25 , third layer metal interconnections M 360 to M 380 are arranged in the row direction.

Second layer metal interconnections M 260 and M 274 are connected through a via 2 V 215 and a via 2 V 255 , respectively, to common third layer metal interconnection M 360 forming word line WL 1 .

Second layer metal interconnection M 222 is connected through a via 2 V 292 to third layer metal interconnection M 365 forming match line MLB 0 .

Second layer metal interconnections M 264 , M 272 and M 218 are connected through a via 2 V 235 , a via 2 V 245 , and a via 2 V 282 , respectively, to common third layer metal interconnection M 370 forming a power supply node.

Second layer metal interconnection M 214 is connected through a via 2 V 272 to third layer metal interconnection M 375 forming match line MLA 0 .

Second layer metal interconnections M 262 and M 276 are connected through a via 2 V 225 and a via 2 V 265 , respectively, to common third layer metal interconnection M 380 forming word line WL 0 .

Since the interconnection pattern of the metal interconnection inside memory cell MC 1 # 0 that is adjacent to memory cell MC 0 # 0 in the row direction is the same as the interconnection pattern that is obtained by arranging the interconnection pattern of memory cell MC 0 # 0 so as to be axisymmetrically in the column direction, the description thereof will not be repeated. In addition, the interconnection pattern of the metal interconnection inside memory cell MC 0 # 1 that is adjacent to memory cell MC 0 # 0 in the column direction may be the same as the interconnection pattern obtained by arranging the interconnection pattern of memory cell MC 0 # 0 so as to be axisymmetrically in the row direction, or may be the same as the interconnection pattern of memory cell MC 0 # 0 .

By configuring the layout as described above, a highly integrated CAM memory array can be realized with layers up to the third layer metal interconnection layer. If the number of interconnection layers can be suppressed, the manufacturing cost can be reduced.

(Modifications)

In the above-described embodiments, the transistor for data search is an NMOS transistor (NS 01 to NS 07 ). In another embodiment, the semiconductor device employs a PMOS transistor as a transistor for data search.

FIG. 26 is a circuit diagram illustrating a configuration example of memory cell MC 0 # 0 according to a modification of the third embodiment. Since the elements having been described with reference to FIG. 22 among the elements shown in FIG. 26 are designated by the same reference characters, the description thereof will not be repeated.

Logical operation cell LCA 0 according to a modification includes PMOS transistors PS 0 , P 51 , PS 2 , and PS 3 in place of NMOS transistors NS 0 , NS 1 , NS 2 , and NS 3 . Logical operation cell LCB 0 according to the modification includes PMOS transistors PS 4 , PS 5 , PS 6 , and PS 7 in place of NMOS transistors NS 4 , NS 5 , NS 6 , and NS 7 .

PMOS transistors PS 0 and PS 1 are connected in series between a match line MLA 0 and a power supply line VDD. PMOS transistor PS 0 has a gate connected to a search line SLA 0 . PMOS transistor PS 1 has a gate connected to a storage node m 1 .

PMOS transistors PS 2 and PS 3 are connected in series between match line MLA 0 and power supply line VDD. PMOS transistor PS 2 has a gate connected to a search line /SLA 0 . PMOS transistor PS 3 has a gate connected to a storage node m 0 .

PMOS transistors PS 4 and PS 5 are connected in series between a match line MLB 0 and power supply line VDD. PMOS transistor PS 4 has a gate connected to a search line SLB 0 . PMOS transistor PS 5 has a gate connected to storage node m 1 .

PMOS transistors PS 6 and PS 7 are connected in series between match line MLB 0 and power supply line VDD. PMOS transistor PS 6 has a gate connected to a search line /SLB 0 . PMOS transistor PS 7 has a gate connected to storage node m 0 .

The data in memory cell MC 0 # 0 according to the modification is the same as the data in memory cell MC 0 # 0 shown in FIG. 18 .

FIG. 27 is a block diagram illustrating a configuration example of a semiconductor device 2700 according to a modification of the third embodiment. Since the elements having been described with reference to FIG. 21 among the elements shown in FIG. 27 are designated by the same reference characters, the description thereof will not be repeated.

Memory cells MC 0 # 0 to MC 1 # 1 arranged in semiconductor device 2700 each have a PMOS transistor as a transistor for data search, as shown in FIG. 26 .

Semiconductor device 2700 includes search drivers 104 A, 104 B, 106 A, and 106 B each having an output terminal provided with an inverter Inv, and also includes pre-charging & encoding circuits 112 A and 112 B each having an input terminal provided with an inverter Inv. As a result, the level of each search line becomes an electric potential at the inverted level of the signal output from the search driver connected thereto. Also, pre-charging & encoding circuits 112 A and 112 B each receive an input of the signal of an inverted level on each match line connected thereto. Also, due to the effect of inverter Inv, each match line is pre-charged to the inverted level of the signal output from the pre-charging & encoding circuit connected thereto. In a certain aspect, each match line is pre-charged to an “L” level.

The search operation of semiconductor device 2700 will be hereinafter described with reference to FIGS. 26 and 27 . When the data in memory cell MC 0 # 0 matches the search data, the level on the match line is maintained at an “L” level. On the other hand, when the data in memory cell MC 0 # 0 does not match the search data, the level on the match line becomes an “H” level.

The following is an explanation about the case where search data signal S 0 (A) is “1” by way of example. In this case, the level on search line SLA 0 is inverted by inverter Inv and thereby becomes an “L” level. Thus, PMOS transistor PS 0 connected to search line SLA 0 is brought into an ON state. In the above-described case, when the data in memory cell MC 0 # 0 is “0”, that is, when the data in memory cell MC 0 # 0 does not match the search data, PMOS transistor PS 1 is brought into an ON state, and match line MLA 0 becomes an “H” level. On the other hand, when the data in memory cell MC 0 # 0 is “1”, that is, when the data in memory cell MC 0 # 0 matches the search data, PMOS transistor PS 1 is brought into an OFF state, and match line MLA 0 is maintained at the pre-charged “L” level.

According to the above description, due to the effect of inverter Inv, pre-charging & encoding circuit receives an input of the “H” level when the data held by each memory cell matches the corresponding search data, and receives an input of the “L” level when even one piece of data does not match the corresponding search data.

FIG. 28 is a plan view showing an arrangement of a well, a diffusion region DF, a polysilicon PO, a contact hole CT, and a first layer metal interconnection in memory cell MC 0 # 0 according to a modification of the third embodiment.

The well configuration in memory cell MC 0 # 0 shown in FIG. 28 is different from the well configuration of memory cell MC 0 # 0 shown in FIG. 23 in that it further includes an N well NW 1 . The layout shown in FIG. 28 is the same as the layout shown in FIG. 23 in which the layout of NMOS transistors NS 0 to NS 7 for data search is replaced with the layout of PMOS transistors PS 0 to PS 7 for data search shown in FIG. 8 . Thus, the details of memory cell MC 0 # 0 shown in FIG. 28 will not be repeated.

FIG. 29 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 2700 . The layout shown in FIG. 29 is approximately the same as the layout shown in FIG. 24 . Thus, only different features will be hereinafter described.

P type diffusion region FL 340 forming a source of PMOS transistor PS 2 and P type diffusion region FL 350 forming a source of PMOS transistor PS 6 are connected through contact holes CT 48 and CT 54 , respectively, to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 121 to second layer metal interconnection M 910 that forms power supply line VDD.

P type diffusion region FL 348 forming a source of PMOS transistor PS 2 and P type diffusion region FL 358 forming a source of PMOS transistor PS 6 are connected through contact holes CT 52 and CT 58 , respectively, to the common first layer metal interconnection. This first layer metal interconnection is connected through a via 1 V 123 to second layer metal interconnection M 910 that forms power supply line VDD.

FIG. 30 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection layer, and a third layer metal interconnection layer in memory cell MC 0 # 0 arranged in semiconductor device 2700 . The layout shown in FIG. 30 is the same as the layout shown in FIG. 25 except that a via 2 V 282 is not provided in third layer metal interconnection M 370 .

Semiconductor device 2700 employing a PMOS transistor as a transistor for data search can also simultaneously search for the A-port search data and the B-port search data.

[Fourth Embodiment]

In the above-described embodiment, each transistor is a plane type (planar type) transistor and structured to have a single gate for a channel. The semiconductor device according to the present embodiment includes a multi-gate transistor having a plurality of gates for a channel.

(Structure of Transistor)

FIGS. 31A to 31C each are a diagram showing the structure of a transistor. FIG. 31A shows an example of the structure of a planar-type field effect transistor (hereinafter also referred to as a “planar FET”). FIG. 31B shows an example of the structure of a fin-type field effect transistor (hereinafter also referred to as a “FinFET”). FIG. 31C shows an example of the structure of a gate all around (GAA) type field effect transistor (hereinafter also referred to as a “GAAFET”).

Referring to FIG. 31A , in a planar FET, a source, a channel and a drain are formed on the same plane. Furthermore, the gate of the planar FET is formed on a channel with a gate insulating film interposed therebetween. Namely, the gate is formed so as to cover one surface of the channel.

The channel of the FinFET shown in FIG. 31B protrudes from a silicon substrate as compared with the channel of the planar FET. Also, the gate of the FinFET is formed so as to cover the side surface and the upper surface of the protruding channel.

A nanowire obtained by crystal growth is used in the channel of a GAAFET shown in FIG. 31C . Also, the gate of the GAAFET is formed so as to completely cover the circumference of the axis of the channel (nanowire).

In the planar FET shown in FIG. 31A , since the channel is a plane, the gate faces the channel only from one direction. In this case, a depletion layer is formed only on one plane of the channel, so that a leakage current is increased.

On the other hand, in the transistor shown in FIG. 31B or 31C , the gate faces the channel from a plurality of directions. Thereby, the current driving capacity of the channel is increased. Also, the channel is approximately depleted. As a result, these transistors can reduce a leakage current. Thus, the semiconductor device according to the fourth embodiment employs these multi-gate transistors. In addition, the schematic configuration of this semiconductor device is the same as the schematic configuration shown in FIG. 21 .

(Layout of Dual-Port TCAM Using FinFET)

The following is an explanation about the case where a FinFET is used as a transistor that forms memory cell MC 0 # 0 shown in FIG. 22 by way of example.

FIG. 32 is a plan view showing an arrangement of a well, a diffusion region DF, polysilicon PO, and a local interconnection (LIC) in memory cell MC 0 # 0 according to the fourth embodiment. The layout of memory cell MC 0 # 0 shown in FIG. 32 is different from the layout of memory cell MC 0 # 0 shown in FIG. 23 in that it includes a diffusion layer DF corresponding to a fin in the FinFET and that it includes a local interconnection. Thus, these different features will be hereinafter described.

In memory cell MC 0 # 0 according to the fourth embodiment, a P well PW 0 having a P type conductivity type, an N well NW 0 having an N type conductivity type, and P well PW 1 are formed sequentially in this order in the row direction.

Diffusion layer DF corresponding to a fin in the FinFET is formed in each well. More specifically, in P well PW 0 , two diffusion layers DF are formed, which correspond to the source and the drain in each of NMOS transistors NA 2 and ND 2 that form a data cell DC 0 and NMOS transistors NA 0 and ND 0 that form a mask data cell MDC 0 .

In N well NW 0 , one diffusion layer DF corresponding to PMOS transistors P 0 and P 1 that form data cell DC 0 , and one diffusion layer DF corresponding to PMOS transistors P 2 and P 3 that form a mask data cell MDC 0 are formed.

For example, NMOS transistor ND 2 has a source and a drain that are formed by one pair of N type diffusion regions FL 702 , FL 704 , and also has a polysilicon gate disposed therebetween. Each of N type diffusion regions FL 702 and FL 704 is formed by two common diffusion layers DF. Namely, the source and the drain of NMOS transistor ND 2 are formed by two diffusion layers DF.

In P well PW 1 , two diffusion layers DF corresponding to NMOS transistors NA 3 and ND 3 that form a data cell DC 0 , NMOS transistors NA 1 and ND 1 that form a mask data cell MDC 0 , two diffusion layers DF corresponding to NMOS transistors NS 0 to NS 3 for data search, and two diffusion layers DF corresponding to NMOS transistors NS 4 to NS 7 are formed.

As the number of fins (diffusion layers) for each transistor increases, the current driving capacity of each transistor is further improved. In the example shown in FIG. 32 , the number of fins corresponding to PMOS transistors P 0 to P 3 is one and the number of fins corresponding to other NMOS transistors is two, but the number of fins for each transistor is not limited thereto. For example, the number of fins for each transistor may be three or more.

The relation between the gate and the diffusion region (the source and the drain) forming each transistor shown in FIG. 32 is the same as the relation between the gate and the diffusion region forming each transistor shown in FIG. 23 , except that diffusion layer DF corresponds to a fin in the FinFET.

The arrangement of a local interconnection will be hereinafter described. The local interconnection is formed, for example, by single metal such as tungsten, and arranged so as to be in ohmic contact with the source, the drain or the gate of the transistor. Namely, the local interconnection functions as a source electrode, a drain electrode, or a gate electrode.

The local interconnection shown in FIG. 32 is arranged in place of each contact hole and the first layer metal interconnection that are shown in FIG. 23 . The local interconnection connected to a gate of each of (two diffusion layers DF forming) N type diffusion regions FL 702 , FL 706 , FL 710 , FL 712 , FL 718 , FL 722 , FL 740 , and FL 750 , and NMOS transistors NA 0 to NA 3 , NS 0 , NS 2 , NS 4 , and NS 6 is arranged in place of one contact hole and one first layer metal interconnection shown in FIG. 23 . Also, local interconnections are arranged independently in N type diffusion regions FL 736 , FL 744 , FL 746 , and FL 754 . Each of these local interconnections is connected to a corresponding one of the upper first layer metal interconnections through a via 0 . For example, the local interconnection connected to N type diffusion region FL 702 is connected to the upper first layer metal interconnection through a via 0 V 006 . Also, local interconnections for causing two fins (diffusion layers DF) to be equipotential are arranged independently in N type diffusion regions FL 738 , FL 742 , FL 748 , and FL 752 .

The local interconnection for connecting N type diffusion region FL 704 and the polysilicon that forms a gate in each of PMOS transistor P 3 and NMOS transistors ND 3 , NS 3 and NS 7 is arranged in place of two contact holes (CT 408 , CT 418 ) and one first layer metal interconnection. Similarly, the local interconnection for connecting the gate of PMOS transistor P 1 and N type diffusion region FL 708 , the local interconnection for connecting the gate of PMOS transistor P 2 and N type diffusion region FL 728 , and the local interconnection for connecting the gate of PMOS transistor P 0 and N type diffusion region FL 732 are also arranged in place of two contact holes and one first layer metal interconnection. These local interconnections are not connected to the upper first layer metal interconnection, but arranged so as to merely connect the drain of the NMOS transistor and the gate of the PMOS transistor.

FIG. 33 is a plan view showing an arrangement of a via 0 , a local interconnection, and a first layer metal interconnection layer in memory cell MC 0 # 0 according to the fourth embodiment. The layout of the first layer metal interconnection shown in FIG. 33 is approximately the same as the layout of the second layer metal interconnection shown in FIG. 24 .

Specifically, first layer metal interconnections M 660 , M 662 , M 664 , M 666 , M 668 , M 670 , M 672 , M 674 , M 676 , M 612 , M 616 , M 618 , M 620 , and M 624 shown in FIG. 33 correspond to second layer metal interconnections M 260 , M 262 , M 264 , M 266 , M 268 , M 270 , M 272 , M 274 , M 276 , M 212 , M 216 , M 218 , M 220 , and M 224 , respectively, shown in FIG. 24 . First layer metal interconnection M 618 functions as a dummy interconnection. In another embodiment, first layer metal interconnection M 618 does not have to be arranged.

N type diffusion region FL 736 forming a source of NMOS transistor NS 2 is connected through a local interconnection and a via 0 V 030 to first metal interconnection M 682 forming power supply line VSS.

N type diffusion region FL 740 forming sources of NMOS transistors NS 3 and NS 1 is connected through a local interconnection and a via 0 V 032 to first metal interconnection M 684 forming match line MLA 0 .

N type diffusion region FL 744 forming a source of NMOS transistor NS 0 is connected through a local interconnection and a via 0 V 034 to first metal interconnection M 686 forming power supply line VSS.

N type diffusion region FL 746 forming a source of NMOS transistor NS 6 is connected through a local interconnection and a via 0 V 040 to first metal interconnection M 688 forming power supply line VSS.

N type diffusion region FL 750 forming sources of NMOS transistors NS 7 and NS 5 is connected through a local interconnection and a via 0 V 042 to first metal interconnection M 692 forming match line MLB 0 .

N type diffusion region FL 754 forming a source of NMOS transistor NS 4 is connected through a local interconnection and a via 0 V 044 to first metal interconnection M 694 forming power supply line VSS.

FIG. 34 is a plan view showing an arrangement of a via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in memory cell MC 0 # 0 according to the fourth embodiment. In FIG. 34 , second layer metal interconnections M 710 to M 760 are arranged in the row direction.

First layer metal interconnections M 664 , M 672 , M 682 , and M 688 are connected through a via 1 V 177 , a via 1 V 179 , a via 1 V 183 , and a via 1 V 186 , respectively, to second layer metal interconnection M 710 forming power supply line VSS.

First layer metal interconnections M 660 and M 674 are connected through a via 1 V 175 and a via 1 V 181 , respectively, to second layer metal interconnection M 720 forming word line WL 1 .

First layer metal interconnection M 692 is connected through a via 1 V 187 to second layer metal interconnection M 730 forming match line MLB 0 .

First layer metal interconnection M 684 is connected through a via 1 V 184 to second layer metal interconnection M 740 forming match line MLA 0 .

First layer metal interconnections M 662 and M 676 are connected through a via 1 V 176 and a via 1 V 182 , respectively, to second layer metal interconnection M 750 forming word line WL 0 .

First layer metal interconnections M 664 , M 672 , M 686 , and M 694 are connected through a via 1 V 178 , a via 1 V 180 , a via 1 V 185 , and a via 1 V 188 , respectively, to second layer metal interconnection M 760 forming power supply line VSS.

As described above, in the semiconductor device according to the fourth embodiment, the number of metal interconnection layers can be reduced by using local interconnections. Specifically, in this semiconductor device, a layer corresponding to the first layer metal interconnection having been described with reference to FIG. 23 can be omitted. Namely, the semiconductor device according to the fourth embodiment can be reduced in size as compared with semiconductor device 2100 .

[Fifth Embodiment]

As shown in FIGS. 32 to 34 , memory cell MC 0 # 0 according to the fourth embodiment employs one common power supply line VSS as: power supply line VSS connected to the NMOS transistor for data search; and power supply line VSS connected to the transistors forming data cell DC 0 and mask data cell MDC 0 . In such a case, a prescribed amount of leakage current exists in the NMOS transistor for data search when the data is searched for (retrieved) and also when the data is not searched for.

A semiconductor device according to the fifth embodiment can solve the above-described problems. The following is an explanation about a specific configuration of the semiconductor device according to the fifth embodiment.

FIG. 35 is a circuit diagram illustrating a configuration example of memory cell MC 0 # 0 in the semiconductor device according to the fifth embodiment. The configuration of memory cell MC 0 # 0 shown in FIG. 35 is approximately the same as the configuration of memory cell MC 0 # 0 shown in FIG. 22 . Accordingly, only different elements will be hereinafter described.

NMOS transistors NS 0 and NS 1 are connected in series between match line MLA 0 and a power supply line VSSA 0 . Also, NMOS transistors NS 0 and NS 1 have gates to which search line /SLA 0 and storage node m 1 are respectively connected. NMOS transistors NS 2 and NS 3 are connected in series between match line MLA 0 and a power supply line VSSA 0 . Also, NMOS transistors NS 2 and NS 3 have gates to which search line /SLA 0 and storage node m 0 are respectively connected. Namely, power supply line VSSA 0 is connected to logical operation cell LCA 0 .

NMOS transistors NS 4 and NS 5 are connected in series between match line MLB 0 and a power supply line VSSB 0 . Also, NMOS transistors NS 4 and NS 5 have gates to which search line SLB 0 and storage node m 1 are respectively connected. NMOS transistors NS 6 and NS 7 are connected in series between match line MLB 0 and power supply line VSSB 0 . Also, NMOS transistors NS 6 and NS 7 have gates to which search line /SLB 0 and storage node m 0 are respectively connected. Namely, power supply line VSSB 0 is connected to logical operation cell LCB 0 .

As described above, power supply lines VSSA 0 and VSSB 0 connected to the transistors for data search and power supply line VSS connected to the transistors forming data cell DC 0 and mask data cell MDC 0 are electrically independent of each other.

The operation of writing onto memory cell MC 0 # 0 shown in FIG. 35 is the same as the operation of writing onto memory cell MC 0 # 0 having been described with reference to FIG. 22 .

(Search Operation)

FIG. 36 is a diagram illustrating a metal interconnection pattern in each memory cell forming a semiconductor device 3600 according to the fifth embodiment. The alphabetical character “F” in the figure shows the direction of the metal interconnection pattern. In the example shown in FIG. 36 , memory cells MC 0 # 0 , MC 0 # 1 , MC 1 # 0 , and MC 1 # 1 are set in the same interconnection pattern.

Memory cell MC 0 # 0 and memory cell MC 0 # 1 share power supply lines VSS, VSSA 0 , and VSSB 0 with each other. Also, a switch SWA 0 for connecting power supply line VSS and power supply line VSSA 0 is arranged, and a switch SWB 0 for connecting power supply line VSS and power supply line VSSB 0 is arranged.

Memory cell MC 1 # 0 and memory cell MC 1 # 1 share power supply lines VSS, VSSA 1 and VSSB 1 with each other. Also, a switch SWA 1 for connecting power supply line VSS and power supply line VSSA 1 is arranged, and a switch SWB 1 for connecting power supply line VSS and power supply line VSSB 1 is arranged.

The schematic configuration of semiconductor device 3600 is the same as the schematic configuration shown in FIG. 21 . By way of example, switches SWA 0 , SWB 0 , SWA 1 , and SWB 1 are connected to search drivers 104 A, 104 B, 106 A, and 106 B, respectively. Furthermore, search drivers 104 A to 106 B output control signals for controlling switches connected thereto to be turned on and off. For example, search driver 104 A outputs a control signal PGA 0 for controlling switch SWA 0 to be turned on and off.

When the data at the A port is searched for, that is, when an A-port search data signal S 0 (A) is input, search driver 104 A outputs a control signal PGA 0 for controlling switch SWA 0 to be turned on. On the other hand, when the data search is completed (when the data is not searched for), search driver 104 A outputs control signal PGA 0 for controlling switch SWA 0 to be turned off. As with search driver 104 A, other search drivers 104 B, 106 A and 106 B set the corresponding switches to be turned on when the data is searched for, and set the corresponding switches to be turned off when the data is not searched for.

According to the above description, when data is not searched for, semiconductor device 3600 can provide an electrical interruption between power supply line VSS connected to the transistor for holding data and the power supply line connected to the transistor for data search. As a result, semiconductor device 3600 can suppress a leakage current in the transistor for data search when the data is not searched for.

In the above-described example, semiconductor device 3600 is configured such that a switch is arranged for each column in a memory array. In other embodiments, however, semiconductor device 3600 may be configured such that a switch is arranged in each memory array. In this case, power supply lines VSSA 0 and VSSA 1 for A port arranged in each column are electrically connected. Also, power supply lines VSSB 0 and VSSB 1 for B port are also electrically connected. Thereby, in semiconductor device 3600 according to another embodiment, the number of switch elements can be reduced.

(Layout of Memory Cell)

The following is an explanation about memory cell MC 0 # 0 forming semiconductor device 3600 in the layout divided in the stacking direction with reference to FIGS. 37 to 41 .

FIG. 37 is a plan view showing an arrangement of a well, a diffusion region DF, polysilicon PO, and a local interconnection in memory cell MC 0 # 0 according to the fifth embodiment. The layout shown in FIG. 37 is the same as the layout shown in FIG. 32 . However, the local interconnection connected to the transistor for data search is connected to the power supply line arranged independently of power supply line VSS.

Specifically, N type diffusion region FL 736 forming a source of NMOS transistor NS 2 is connected to the local interconnection functioning as a power supply line VSSA 0 . N type diffusion region FL 744 forming a source of NMOS transistor NS 0 is connected to the local interconnection functioning as power supply line VSSA 0 . N type diffusion region FL 746 forming a source of NMOS transistor NS 6 is connected to the local interconnection functioning as a power supply line VSSB 0 . N type diffusion region FL 754 forming a source of NMOS transistor NS 4 is connected to the local interconnection functioning as power supply line VSSB 0 .

FIG. 38 is a plan view showing an arrangement of a via 0 , a local interconnection, and a first layer metal interconnection layer in memory cell MC 0 # 0 according to the fifth embodiment. The layout shown in FIG. 38 is the same as the layout shown in FIG. 33 .

It is to be noted that first layer metal interconnections M 682 and M 686 each function not as power supply line VSS but as power supply line VSSA 0 . Also, first layer metal interconnections M 688 and M 694 each function not as power supply line VSS but as power supply line VSSB 0 .

FIG. 39 is a plan view showing an arrangement of via 1 , a first layer metal interconnection layer, and a second layer metal interconnection layer in memory cell MC 0 # 0 according to the fifth embodiment. The layout shown in FIG. 39 is approximately the same as the layout shown in FIG. 34 . Accordingly, only different features will be hereinafter described.

In place of second layer metal interconnection M 710 , second layer metal interconnections M 715 , M 725 , and M 735 are arranged. Also, in place of second layer metal interconnection M 760 , second layer metal interconnections M 745 , M 755 , and M 765 are arranged.

First layer metal interconnections M 664 and M 672 are connected through a via 1 V 177 and a via 1 V 179 , respectively, to second layer metal interconnection M 715 forming power supply line VSS.

First layer metal interconnection M 682 is connected through a via 1 V 183 to second layer metal interconnection M 725 forming power supply line VSSA 0 .

First layer metal interconnection M 688 is connected through a via 1 V 186 to second layer metal interconnection M 735 forming power supply line VSSB 0 .

First layer metal interconnections M 664 and M 672 are connected through a via 1 V 178 and a via 1 V 180 , respectively, to second layer metal interconnection M 745 forming power supply line VSS.

First layer metal interconnection M 686 is connected through a via 1 V 185 to second layer metal interconnection M 755 forming power supply line VSSA 0 .

First layer metal interconnection M 694 is connected through a via 1 V 188 to second layer metal interconnection M 765 forming power supply line VSSB 0 .

FIG. 40 is a plan view showing an arrangement of a via 2 , a second layer metal interconnection, and a third layer metal interconnection in memory cell MC 0 # 0 according to the fifth embodiment. In FIG. 40 , third layer metal interconnections M 810 to M 880 are arranged in the column direction.

Third layer metal interconnections M 810 , M 820 , M 825 , M 830 , M 835 , M 845 , M 855 , M 865 , and M 875 function as dummy interconnections. In other embodiments, these third layer metal interconnections do not have to be arranged.

Second layer metal interconnection M 715 is connected through a via 2 V 212 and a via 2 V 216 to third layer metal interconnections M 815 and M 840 , respectively, that form power supply line VSS.

Second layer metal interconnection M 725 is connected through a via 2 V 222 and a via 2 V 226 to third layer metal interconnections M 850 and M 860 , respectively, that form power supply line VSSA 0 .

Second layer metal interconnection M 735 is connected through a via 2 V 232 and a via 2 V 236 to third layer metal interconnections M 870 and M 880 , respectively, that form power supply line VSSB 0 .

Second layer metal interconnection M 745 is connected through a via 2 V 214 and a via 2 V 218 to third layer metal interconnections M 815 and M 840 , respectively, that form power supply line VSS.

Second layer metal interconnection M 755 is connected through a via 2 V 224 and a via 2 V 228 to third layer metal interconnections M 850 and M 860 , respectively, that form power supply line VSSA 0 .

Second layer metal interconnection M 765 is connected through a via 2 V 234 and a via 2 V 238 to third layer metal interconnections M 870 and M 880 , respectively, that form power supply line VSSB 0 .

FIG. 41 is a plan view showing an arrangement of a via 3 , a third layer metal interconnection, and a fourth layer metal interconnection in memory cell MC 0 # 0 according to the fifth embodiment. In FIG. 41 , fourth layer metal interconnections M 920 to M 970 are arranged in the row direction.

Fourth layer metal interconnections M 930 and M 960 function as dummy interconnections. In other embodiments, these fourth layer metal interconnections do not have to be arranged.

Third layer metal interconnection M 815 is connected through a via 3 V 310 and a via 3 V 320 to fourth layer metal interconnections M 920 and M 970 , respectively, that form power supply line VSS.

Third layer metal interconnection M 840 is connected through a via 3 V 330 and a via 3 V 340 to fourth layer metal interconnections M 920 and M 970 , respectively, that form power supply line VSS.

Third layer metal interconnection M 850 is connected through a via 3 V 350 to fourth layer metal interconnection M 940 forming power supply line VSSA 0 .

Third layer metal interconnection M 860 is connected through a via 3 V 360 to fourth layer metal interconnection M 940 forming power supply line VSSA 0 .

Third layer metal interconnection M 870 is connected through a via 3 V 370 to fourth layer metal interconnection M 950 forming power supply line VSSB 0 .

Third layer metal interconnection M 880 is connected through a via 3 V 380 to fourth layer metal interconnection M 950 forming power supply line VSSB 0 .

By configuring the layout as described above, memory cell MC 0 # 0 according to the fifth embodiment can provide an electrical interruption between power supply line VSS connected to the transistor for holding data and the power supply line connected to the transistor for data search. As a result, each transistor for data search according to the fifth embodiment can suppress a leakage current at the time when data is not searched for.

(Other Configurations)

The circuit configuration and the layout of a dual-port CAM have been described in the above-described example. In another aspect, a CAM may be configured to have three or more ports. In this case, the CAM cell has the same numbers of match lines, search line pairs and logical operation cells as the number of ports. Thereby, the semiconductor device may further improve the searching speed (processing speed).

In still another aspect, each transistor described above may have a Silicon on Insulator (SOI) structure in which an embedded insulation film is provided below a gate, a source and a channel formed between the gate and the source. Thereby, each memory cell can minimize generation of a depletion layer in a PN junction. As a result, each transistor can implement reduced power consumption by reduced leakage current, and can improve the switching speed.

[Supplementary Notes]

(Supplementary Note 1)

A semiconductor device includes: a first cell (MDC 0 ) configured to be capable of holding 1-bit information; a second cell (DC 0 ) configured to be capable of holding 1-bit information and located adjacent to the first cell; a first match line and a second match line (MLA 0 , MLB 0 ) extending in a first direction; a first search line pair (SLA 0 , /SLA 0 ) extending in a second direction orthogonal to the first direction, first data being transmitted through the first search line pair when the first data is searched for; a second search line pair (SLB 0 , /SLB 0 ) extending in the second direction, second data being transmitted through the second search line pair when the second data is searched for; a first logical operation cell (LCA 0 ) connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by each of the first cell and the second cell and the first data transmitted through the first search line pair; and a second logical operation cell (LCB 0 ) connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by each of the first cell and the second cell and the second data transmitted through the second search line pair.

Thereby, the semiconductor device may function as a TCAM device capable of simultaneously searching for two pieces of search data in one cycle. Thus, when there are a plurality of search targets, this semiconductor device can improve the searching speed as compared with the conventional case. This semiconductor device also searches for two pieces of search data using a common memory array. Thus, this semiconductor device can be suppressed from being increased in size. In addition, this semiconductor device can search for two pieces of search data based on one clock signal, so that power consumption can be suppressed.

(Supplementary Note 2)

In (Supplementary Note 1), the second cell is located adjacent to the first cell in the first direction. The semiconductor device further includes: a first bit line pair (BL 1 , BL 1 ) extending in the second direction and connected to the first cell; a second bit line pair (BL 0 , /BL 0 ) extending in the second direction and connected to the second cell; and a word line (WL 0 ) extending in the first direction and connected to each of the first cell and the second cell.

Thereby, this semiconductor device can write or read data onto or from the second cell while writing or reading data onto or from the first cell.

(Supplementary Note 3)

In (Supplementary Note 1), the second cell is located adjacent to the first cell in the second direction. The semiconductor device further includes: a bit line pair (BL 0 , /BL 0 ) extending in the second direction and connected to each of the first and second cells; a first word line (WL 1 ) extending in the first direction and connected to the first cell; and a second word line (WL 0 ) extending in the first direction and connected to the second cell.

Thereby, this semiconductor device can use a common bit line pair shared between the first cell and the second cell, so that the device can be suppressed from being increased in size.

(Supplementary Note 4)

In (Supplementary Note 1), the first logical operation cell includes: a first logic unit connected between the first match line and a power supply line, and configured to drive, when the first data is searched for, the first match line based on a result of comparison between information (m 1 ) held by the first cell and information transmitted through one search line (SLA 0 ) of the first search line pair; and a second logic unit connected between the first match line and the power supply line, and configured to drive, when the first data is searched for, the first match line based on a result of comparison between information (m 0 ) held by the second cell and information transmitted through the other search line (/SLA 0 ) of the first search line pair. The second logical operation cell includes: a third logic unit connected between the second match line and the power supply line, and configured to drive, when the second data is searched for, the second match line based on a result of comparison between information held by the first cell and information transmitted through one search line (SLB 0 ) of the second search line pair; and a fourth logic unit connected between the second match line and the power supply line, and configured to drive, when the second data is searched for, the second match line based on a result of comparison between information held by the second cell and information transmitted through the other search line (/SLB 0 ) of the second search line pair.

(Supplementary Note 5)

In (Supplementary Note 4), the first logic unit includes a first transistor (NS 1 /PS 1 ) and a second transistor (NS 0 /PS 0 ) that are connected in series between the power supply line (VSS/VDD) and the first match line. The second logic unit includes a third transistor (NS 3 /PS 3 ) and a fourth transistor (NS 2 /PS 2 ) that are connected in series between the power supply line (VSS/VDD) and the first match line. The third logic unit includes a fifth transistor (NS 5 /PS 5 ) and a sixth transistor (NS 4 /PS 4 ) that are connected in series between the power supply line (VSS/VDD) and the second match line. The fourth logic unit includes a seventh transistor (NS 7 /PS 7 ) and an eighth transistor (NS 6 /PS 6 ) that are connected in series between the power supply line (VSS/VDD) and the second match line. The first transistor and the fifth transistor each have a gate connected to a node (m 1 ) at which the first cell holds information. The third transistor and the seventh transistor each have a gate connected to a node (m 0 ) at which the second cell holds information. The second transistor has a gate connected to one search line (SLA 0 ) of the first search line pair. The fourth transistor has a gate connected to the other search line (/SLA 0 ) of the first search line pair. The sixth transistor has a gate connected to one search line (SLB 0 ) of the second search line pair. The eighth transistor has a gate connected to the other search line (/SLB 0 ) of the second search line pair.

(Supplementary Note 6)

In (Supplementary Note 5), the second cell is located adjacent to the first cell in the first direction. The semiconductor device further includes: a first bit line pair (BL 1 , BL 1 ) extending in the second direction and connected to the first cell; a second bit line pair (BL 0 , BL 0 ) extending in the second direction and connected to the second cell; and a word line (WL 0 ) extending in the first direction and connected to each of the first and second cells. The first cell includes: a first inverter having an input connected to a first storage node (m 1 ) connected to the gate of each of the first transistor and the fifth transistor, and an output connected to a second storage node (/m 1 ); a second inverter having an input connected to the second storage node and an output connected to the first storage node; a ninth transistor (NA 0 ) having a first conductivity type, and having one end connected to the first storage node, the other end connected to one bit line of the first bit line pair, and a gate connected to the word line; and a tenth transistor (NA 1 ) having the first conductivity type, and having one end connected to the second storage node, the other end connected to the other bit line of the first bit line pair, and a gate connected to the word line. The second cell includes: a third inverter having an input connected to a third storage node (m 0 ) connected to the gate of each of the third transistor and the seventh transistor, and an output connected to a fourth storage node (/m 0 ); a fourth inverter having an input connected to the fourth storage node, and an output connected to the third storage node; an eleventh transistor (NA 2 ) having the first conductivity type, and having one end connected to the third storage node, the other end connected to one bit line of the second bit line pair, and a gate connected to the word line; and a twelfth transistor (NA 3 ) having the first conductivity type, and having one end connected to the fourth storage node, the other end connected to the other bit line of the second bit line pair, and a gate connected to the word line. A first region (PW 0 ) having a second conductivity type, a second region (NW 0 ) having the first conductivity type, a third region (PW 1 ) having the second conductivity type, a fourth region (NW 1 ) having the first conductivity type, and a fifth region (PW 2 ) having the second conductivity type are formed sequentially in a direction in which the word line extends. In the first region, the ninth and tenth transistors, the thirteenth transistor (ND 0 ) having the first conductivity type and forming the first inverter, and the fourteenth transistor (ND 1 ) having the first conductivity type and forming the second inverter are arranged. In the second region, a fifteenth transistor (P 0 ) having the second conductivity type and forming the first inverter, and a sixteenth transistor (P 1 ) having the second conductivity type and forming the second inverter are arranged. In the third region, the first transistor to the eighth transistor (NS 0 to NS 7 ) each having the first conductivity type are arranged. In the fourth region, a seventeenth transistor (P 2 ) having the second conductivity type and forming the third inverter, and an eighteenth transistor (P 3 ) having the second conductivity type and forming the fourth inverter are arranged. In the fifth region, the eleventh transistor, the twelfth transistor, a nineteenth transistor (ND 2 ) having the first conductivity type and forming the third inverter, and a twentieth transistor (ND 3 ) having the first conductivity type and forming the fourth inverter are arranged.

Thereby, the semiconductor device that may function as a TCAM device may simultaneously search for a plurality of pieces of search data using an NMOS transistor as a transistor for data search. Furthermore, this semiconductor device includes a greater number of transistors for data search than the number of transistors in the conventional semiconductor device. Accordingly, each well provided in this semiconductor device and having transistors arranged therein is wider than each well in the conventional semiconductor device. Thereby, this semiconductor device can reduce the probability of occurrence of a multi bit error.

(Supplementary Note 7)

In (Supplementary Note 5), the second cell is located adjacent to the first cell in the first direction. The semiconductor device further includes: a first bit line pair (BL 1 , BL 1 ) extending in the second direction and connected to the first cell; a second bit line pair (BL 0 , BL 0 ) extending in the second direction and connected to the second cell; and a word line (WL 0 ) extending in the first direction and connected to each of the first cell and the second cell. The first cell includes: a first inverter having an input connected to a first storage node (m 1 ) connected to the gate of each of the first transistor and the fifth transistor, and an output connected to a second storage node (/m 1 ); a second inverter having an input connected to the second storage node and an output connected to the first storage node; a ninth transistor (NA 0 ) having a first conductivity type, and having one end connected to the first storage node, the other end connected to one bit line of the first bit line pair, and a gate connected to the word line; and a tenth transistor (NA 1 ) having the first conductivity type, and having one end connected to the second storage node, the other end connected to the other bit line of the first bit line pair, and a gate connected to the word line. The second cell includes: a third inverter having an input connected to a third storage node (m 0 ) connected to the gate of each of the third transistor and the seventh transistor, and an output connected to a fourth storage node (/m 0 ); a fourth inverter having an input connected to the fourth storage node, and an output connected to the third storage node; an eleventh transistor (NA 2 ) having the first conductivity type, and having one end connected to the third storage node, the other end connected to one bit line of the second bit line pair, and a gate connected to the word line; and a twelfth transistor (NA 3 ) having the first conductivity type, and having one end connected to the fourth storage node, the other end connected to the other bit line of the second bit line pair, and a gate connected to the word line. A first region (PW 0 ) having a second conductivity type, a second region (NW 0 ) having the first conductivity type, and a third region (PW 1 ) having the second conductivity type are formed sequentially in a direction in which the word line extends. In the first region, the ninth and tenth transistors, a thirteenth transistor (ND 0 ) having the first conductivity type and forming the first inverter, and a fourteenth transistor (ND 1 ) having the first conductivity type and forming the second inverter are arranged. In the second region, a fifteenth transistor (P 0 ) having the second conductivity type and forming the first inverter, a sixteenth transistor (P 1 ) having the second conductivity type and forming the second inverter, the first transistor to the eighth transistor (PS 0 to PS 7 ) each having the second conductivity type, a seventeenth transistor (P 2 ) having the second conductivity type and forming the third inverter, and an eighteenth transistor (P 3 ) having the second conductivity type and forming the fourth inverter are arranged. In the third region, the eleventh and twelfth transistors, a nineteenth transistor (ND 2 ) having the first conductivity type and forming the third inverter, and a twentieth transistor (ND 3 ) having the first conductivity type and forming the fourth inverter are arranged.

Thereby, the semiconductor device that may function as a TCAM device can simultaneously search for a plurality of pieces of search data using a PMOS transistor as a transistor for data search. Furthermore, since this semiconductor device includes a relatively few number of wells each having transistors arranged therein, the device can be suppressed from being increased in size. Furthermore, since this semiconductor device includes a greater number of transistors for data search than the number of transistors in the conventional device, each well having transistors arranged therein is wider than each well in the conventional device. Thereby, this semiconductor device can reduce the probability of occurrence of a multi bit error. In another aspect, in the semiconductor device, a material such as silicon germanium that applies stress onto silicon of the channel portion is used in the source region and the drain region of the PMOS transistor for data search, so that the searching speed may be improved.

(Supplementary Note 8)

In (Supplementary Note 5), the second cell is located adjacent to the first cell in the second direction. The semiconductor device further includes: a bit line pair (BL 0 , BL 0 ) extending in the second direction and connected to each of the first cell and the second cell; a first word line (WL 1 ) extending in the first direction and connected to the first cell; and a second word line (WL 0 ) extending in the first direction and connected to the second cell. The first cell includes: a first inverter having an input connected to a first storage node (m 1 ) connected to the gate of each of the first transistor and the fifth transistor, and an output connected to a second storage node (/m 1 ); a second inverter having an input connected to the second storage node and an output connected to the first storage node; a ninth transistor (NA 0 ) having a first conductivity type, and having one end connected to the first storage node, the other end connected to one bit line of the bit line pair, and a gate connected to the first word line; and a tenth transistor (NA 1 ) having the first conductivity type, and having one end connected to the second storage node, the other end connected to the other bit line of the bit line pair, and a gate connected to the first word line. The second cell includes: a third inverter having an input connected to a third storage node (m 0 ) connected to the gate of each of the third transistor and the seventh transistor, and an output connected to a fourth storage node; a fourth inverter having an input connected to the fourth storage node (/m 0 ), and an output connected to the third storage node; an eleventh transistor (NA 2 ) having the first conductivity type, and having one end connected to the third storage node, the other end connected to one bit line of the bit line pair, and a gate connected to the second word line; and a twelfth transistor (NA 3 ) having the first conductivity type, and having one end connected to the fourth storage node, the other end connected to the other bit line of the bit line pair, and a gate connected to the second word line. A first region (PW 0 ) having a second conductivity type, a second region (NW 0 ) having the first conductivity type, and a third region (PW 1 ) having the second conductivity type are formed sequentially in a direction in which the first word line and the second word line extend. In the first region, the ninth and eleventh transistors, a thirteenth transistor (ND 0 ) having the first conductivity type and forming the first inverter, and a fourteenth transistor (ND 1 ) having the first conductivity type and forming the second inverter are arranged. In the second region, a fifteenth transistor (P 0 ) having the second conductivity type and forming the first inverter, the sixteenth transistor (P 1 ) having the second conductivity type and forming the second inverter, a seventeenth transistor (P 2 ) having the second conductivity type and forming the third inverter, and an eighteenth transistor (P 3 ) having the second conductivity type and forming the fourth inverter are arranged. In the third region, the first transistor to the eighth transistor (NS 0 to NS 7 ) each having the first conductivity type, the tenth and twelfth transistors, a nineteenth transistor (ND 2 ) having the first conductivity type and forming the third inverter, and a twentieth transistor (ND 3 ) having the first conductivity type and forming the fourth inverter are arranged.

Thereby, the semiconductor device that may function as a TCAM device may simultaneously search for a plurality of pieces of search data using an NMOS transistor as a transistor for data search. Furthermore, since this semiconductor device includes a relatively few number of wells each having transistors arranged therein, the device can be suppressed from being increased in size.

(Supplementary Note 9)

In (Supplementary Note 8), at least one transistor of the first to twentieth transistors is formed by a multi-gate transistor.

(Supplementary Note 10)

In (Supplementary Note 8), the semiconductor device further includes: a first local interconnection for connecting a diffusion layer (FL 704 ) shared between the eleventh transistor (NA 2 ) and the nineteenth transistor (ND 2 ) and a gate of the eighteenth transistor (P 3 ); a second local interconnection for connecting a diffusion layer (FL 708 ) shared between the ninth transistor (NA 0 ) and the thirteenth transistor (ND 0 ) and a gate of the sixteenth transistor (P 1 ); a third local interconnection for connecting a diffusion layer (FL 728 ) shared between the twelfth transistor (NA 3 ) and the twentieth transistor (ND 3 ) and a gate of the seventeenth transistor (P 2 ); and a fourth local interconnection for connecting a diffusion layer (FL 732 ) shared between the tenth transistor (NA 1 ) and the fourteenth transistor (ND 1 ) and a gate of the fifteenth transistor (P 0 ).

(Supplementary Note 11)

In (Supplementary Note 4), the semiconductor device further includes: a first power supply line (VSS) connected to the first cell and the second cell; a second power supply line (VSSA 0 ) connected to the first logic unit and the second logic unit; a third power supply line (VSSB 0 ) connected to the third logic unit and the fourth logic unit; a first switch (SWA 0 ) for connecting the first power supply line and the second power supply line; and a second switch (SWB 0 ) for connecting the first power supply line and the third power supply line. The first switch is turned on when the first data is searched for, and turned off when the first data is not searched for. The second switch is turned on when the second data is searched for, and turned off when the second data is not searched for.

(Supplementary Note 12)

The semiconductor device includes: a data cell (DC 0 ) configured to be capable of holding 1-bit information; a first match line and a second match line (MLA 0 , MLB 0 ) extending in a first direction; a first search line pair (SLA 0 , /SLA 0 ) extending in a second direction orthogonal to the first direction, first data being transmitted through the first search line pair when the first data is searched for; a second search line pair (SLB 0 , /SLB 0 ) extending in the second direction, second data being transmitted through the second search line pair when the second data is searched for; a first logical operation cell (LCA 0 ) connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the data cell and the first data transmitted through the first search line pair; and a second logical operation cell (LCB 0 ) connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the data cell and the second data transmitted through the second search line pair.

Thereby, a semiconductor device may function as a BCAM device capable of simultaneously searching for two pieces of search data in one cycle. Accordingly, when there are a plurality of search targets, this semiconductor device can improve the searching speed as compared with the conventional case. This semiconductor device also searches for two pieces of search data using a common memory array. Thus, this semiconductor device can be suppressed from being increased in size. In addition, this semiconductor device can search for two pieces of search data based on one clock signal, so that power consumption can be suppressed.

(Supplementary Note 13)

In (Supplementary Note 12), the semiconductor device further includes: a bit line pair (BL 0 , BL 0 ) extending in the first direction and connected to the data cell; and a word line (WL 0 ) extending in the first direction and connected to the data cell. The first logical operation cell includes: a first logic unit connected between the first match line and a power supply line (VSS), and configured to drive, when first data is searched for, the first match line based on a result of comparison between information held at a first storage node (A 0 ) of the data cell and information transmitted through one search line (SLA 0 ) of the first search line pair; and a second logic unit connected between the first match line and the power supply line, and configured to drive, when the first data is searched for, the first match line based on a result of comparison between information held at a second storage node (A 1 ) of the data cell and information transmitted through the other search line (/SLA 0 ) of the first search line pair. The second logical operation cell includes: a third logic unit connected between the second match line and the power supply line, and configured to drive, when second data is searched for, the second match line based on a result of comparison between information held at the first storage node and information transmitted through one search line (SLB 0 ) of the second search line pair; and a fourth logic unit connected between the second match line and the power supply line, and configured to drive, when the second data is searched for, the second match line based on a result of comparison between information held at the second storage node and information transmitted through the other search line (/SLB 0 ) of the second search line pair. The first logic unit includes a first transistor (NS 0 ) and a second transistor (NS 1 ) that are connected in series between the power supply line and the first match line. The second logic unit includes a third transistor (NS 3 ) and a fourth transistor (NS 2 ) that are connected in series between the power supply line and the first match line. The third logic unit includes a fifth transistor (NS 5 ) and a sixth transistor (NS 4 ) that are connected in series between the power supply line and the second match line. The fourth logic unit includes a seventh transistor (NS 7 ) and an eighth transistor (NS 6 ) that are connected in series between the power supply line and the second match line. The first transistor and the fifth transistor each have a gate connected to the first storage node. The third transistor and the seventh transistor each have a gate connected to the second storage node. The second transistor has a gate connected to one search line (SLA 0 ) of the first search line pair. The fourth transistor has a gate connected to the other search line (/SLA 0 ) of the first search line pair. The sixth transistor has a gate connected to one search line (SLB 0 ) of the second search line pair. The eighth transistor has a gate connected to the other search line (/SLB 0 ) of the second search line pair. The data cell includes: a first inverter having an input connected to the first storage node and an output connected to the second storage node; a second inverter having an input connected to the second storage node and an output connected to the first storage node; a ninth transistor (NA 0 ) having a first conductivity type, and having one end connected to the first storage node, the other end connected to one bit line of the bit line pair, and a gate connected to the word line; and a tenth transistor (NA 1 ) having the first conductivity type, and having one end connected to the second storage node, the other end connected to the other bit line of the bit line pair, and a gate connected to the word line. A first region (PW 0 ) having a second conductivity type, a second region (NW 0 ) having the first conductivity type, and a third region (PW 1 ) having the second conductivity type are formed sequentially in a direction in which the word line extends. In the first region, the ninth and tenth transistors, a thirteenth transistor (ND 0 ) having the first conductivity type and forming the first inverter, and a fourteenth transistor (ND 1 ) having the first conductivity type and forming the second inverter are arranged. In the second region, a fifteenth transistor (P 0 ) having the second conductivity type and forming the first inverter, and a sixteenth transistor (P 1 ) having the second conductivity type and forming the second inverter are arranged. In the third region, the first transistor to the eighth transistor (NS 0 to NS 7 ) each having the first conductivity type are arranged.

Thereby, the semiconductor device that may function as a BCAM device may simultaneously search for a plurality of pieces of search data using an NMOS transistor as a transistor for data search. Furthermore, since this semiconductor device includes a greater number of transistors for data search than the number of transistors in the conventional device. Accordingly, each well provided in this semiconductor device and having transistors arranged therein is wider than each well in the conventional device. Thereby, this semiconductor device can reduce the probability of occurrence of a multi bit error.

(Supplementary Note 14)

In (Supplementary Note 12), the semiconductor device further includes: a bit line pair (BL 0 , BL 0 ) extending in the first direction and connected to the data cell; and a word line (WL 0 ) extending in the first direction and connected to the data cell. The first logical operation cell includes: a first logic unit connected between the first match line and a power supply line (VDD), and configured to drive, when the first data is searched for, the first match line based on a result of comparison between information held at a first storage node (A 0 ) of the data cell and information transmitted through one search line (SLA 0 ) of the first search line pair; and a second logic unit connected between the first match line and the power supply line, and configured to drive, when the first data is searched for, the first match line based on a result of comparison between information held at a second storage node (A 1 ) of the data cell and information transmitted through the other search line (/SLA 0 ) of the first search line pair. The second logical operation cell includes: a third logic unit connected between the second match line and the power supply line, and configured to drive, when the second data is searched for, the second match line based on a result of comparison between information held at the first storage node and information transmitted through one search line (SLB 0 ) of the second search line pair; and a fourth logic unit connected between the second match line and the power supply line, and configured to drive, when the second data is searched for, the second match line based on a result of comparison between information held at the second storage node and information transmitted through the other search line (/SLB 0 ) of the second search line pair. The first logic unit includes a first transistor (PS 0 ) and a second transistor (PS 1 ) that are connected in series between the power supply line and the first match line. The second logic unit includes a third transistor (PS 3 ) and a fourth transistor (PS 2 ) that are connected in series between the power supply line and the first match line. The third logic unit includes a fifth transistor (PS 5 ) and a sixth transistor (PS 4 ) that are connected in series between the power supply line and the second match line. The fourth logic unit includes a seventh transistor (PS 7 ) and an eighth transistor (PS 6 ) that are connected in series between the power supply line and the second match line. The first transistor and the fifth transistor each have a gate connected to the first storage node. The third transistor and the seventh transistor each have a gate connected to the second storage node. The second transistor has a gate connected to one search line (SLA 0 ) of the first search line pair. The fourth transistor has a gate connected to the other search line (/SLA 0 ) of the first search line pair. The sixth transistor has a gate connected to one search line (SLB 0 ) of the second search line pair. The eighth transistor has a gate connected to the other search line (/SLB 0 ) of the second search line pair. The data cell includes: a first inverter having an input connected to the first storage node and an output connected to the second storage node; a second inverter having an input connected to the second storage node and an output connected to the first storage node; a ninth transistor (NA 0 ) having a first conductivity type, and having one end connected to the first storage node, the other end connected to one bit line of the bit line pair, and a gate connected to the word line; and a tenth transistor (NA 1 ) having the first conductivity type, and having one end connected to the second storage node, the other end connected to the other bit line of the bit line pair, and a gate connected to the word line. A first region (PW 0 ) having a second conductivity type and a second region (NW 0 ) having the first conductivity type are formed sequentially in a direction in which the word line extends. In the first region, the ninth and tenth transistors, a thirteenth transistor (ND 0 ) having the first conductivity type and forming the first inverter, and a fourteenth transistor (ND 1 ) having the first conductivity type and forming the second inverter are arranged. In the second region, a fifteenth transistor (P 0 ) having the second conductivity type and forming the first inverter, a sixteenth transistor (P 1 ) having the second conductivity type and forming the second inverter, and the first transistor to the eighth transistor (PS 0 to PS 7 ) each having the second conductivity type are arranged.

Thereby, the semiconductor device that may function as a BCAM device may simultaneously search for a plurality of pieces of search data using a PMOS transistor as a transistor for data search. Furthermore, since this semiconductor device includes a relatively few number of wells each having transistors arranged therein, the device can be suppressed from being increased in size. Furthermore, since this semiconductor device includes a greater number of transistors for data search than the number of transistors in the conventional device. Accordingly, each well provided in this semiconductor device and having transistors arranged therein is wider than each well in the conventional device. Thereby, this semiconductor device can reduce the probability of occurrence of a multi bit error. In another aspect, in the semiconductor device, a material such as silicon germanium that applies stress onto silicon of the channel portion is used in the source region and the drain region of the PMOS transistor for data search, so that the searching speed may be improved.

Although the embodiments of the present invention have been described as above, it should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the meaning and scope equivalent to the terms of the claims.