Sensing circuit, set of pre-amplifiers, and operating method thereof

The present disclosure relates to a sensing circuit, a set of pre-amplifiers, and an operating method thereof. More particularly, the present disclosure relates to a sensing circuit, a set of pre-amplifiers, and an operating method that is capable of amplifying the voltage difference between a first input terminal and a second input terminal of a sense amplifier of the sensing circuit.

A sense amplifier is part of the sensing circuit that is used for reading data from a memory device. The role of the sense amplifier is to sense the low power signals from a bit line that represents a data bit ( 1 or 0 ) stored in a memory cell of the memory device, and amplify the small voltage swing to recognizable logic levels so the data can be interpreted properly by logic outside the memory device. There is one sense amplifier for each column of memory cells, and hence a memory device may be disposed with numerous sense amplifiers based on the number of columns.

Sense amplifiers are applied in memory cells which are laid out in rows and columns on the chip. Each line is attached to each cell in the row. The lines which run along the rows are called word lines which are activated by putting a voltage on it. The lines which run along the columns are called bit lines, and two such complementary bit lines are attached to a sense amplifier at the edge of the array.

Conventionally, when the memory cell is light-loaded or has smaller resistance (e.g., MRAM or RRAM), the sensing yield of the sense amplifier will be low if the voltage difference between the two complementary bit lines is too small. Therefore, it is crucial to develop a mechanism to amplify the voltage difference between the two complementary bit lines for improving the sensing yield.

The present disclosure provides a set of pre-amplifiers of a sense amplifier. The set of pre-amplifiers includes a first pre-amplifier and a second pre-amplifier. The first pre-amplifier is coupled to a first input terminal of the sense amplifier. The second pre-amplifier is coupled to a second input terminal of the sense amplifier. The first pre-amplifier and the second pre-amplifier respectively performs a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage. One of the first pre-amplifier and the second pre-amplifier amplifies a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier.

The present disclosure provides a sensing circuit for sensing data of a memory cell. The sensing circuit includes a sense amplifier and a set of pre-amplifiers. The sense amplifier has a first input terminal and a second input terminal. The set of pre-amplifiers includes a first pre-amplifier and a second pre-amplifier. The first pre-amplifier is coupled to the first input terminal of the sense amplifier. The second pre-amplifier is coupled to the second input terminal of the sense amplifier. The first pre-amplifier and the second pre-amplifier respectively performs a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage. One of the first pre-amplifier and the second pre-amplifier amplifies a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier. The sense amplifier performs a sensing operation to sense the data of the memory cell based on the amplified voltage difference between the first input terminal and the second input terminal.

The present disclosure proposes an operating method of a set of pre-amplifiers having a first pre-amplifier and a second pre-amplifier respectively coupled to a first input terminal and a second input terminal of a sense amplifier. The operating method includes the following steps: respectively performing, by the first pre-amplifier and the second pre-amplifier, a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage; and amplifying, by one of the first pre-amplifier and the second pre-amplifier, a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier.

The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

FIG. 1A is a schematic diagram illustrating a sense amplifier;

FIG. 1B is a waveform graph of controlling the sense amplifier of FIG. 1A ;

FIG. 2 is a schematic diagram illustrating a set of pre-amplifiers according to an exemplary embodiment of the present disclosure;

FIG. 3 shows a flow chart of a method of operating the set of pre-amplifiers according to an exemplary embodiment of the present disclosure;

FIG. 4A is a schematic diagram of a sensing circuit for sensing data of a memory cell according to an exemplary embodiment of the present disclosure;

FIG. 4B is a waveform graph of controlling the sensing circuit of FIG. 4A ;

FIG. 5A is a schematic diagram of a sensing circuit for sensing data of a memory cell according to an exemplary embodiment of the present disclosure; and

FIG. 5B is a waveform graph of controlling the sensing circuit of FIG. 5A .

See FIG. 1A and FIG. 1B , wherein FIG. 1A is a schematic diagram illustrating a sense amplifier 100 , and FIG. 1B is a waveform graph of controlling the sense amplifier 100 of FIG. 1A . In a first phase P 1 , bit lines BL and BLB which are complementary to each other will be pre-charged to a reading voltage Vread in response to a pre-charge signal PRE, wherein the reading voltage Vread is lower than a predetermined voltage VDD but higher than a predetermined voltage VSS. In a second phase P 2 , a word line signal WL will be enabled, such that the bit lines BL and BLB will be discharged by the resistance of the memory cell connected to the sense amplifier 100 . As long as the voltage difference between the bit lines BL and BLB is large enough, the sense amplifier enabling signal SAEN will be enabled in a third phase P 3 for the sense amplifier 100 to sense the data of the correspondingly memory cell and output the amplified data via output nodes OUT and OUTB.

However, if the resistance of the memory cell is small, the discharging speeds of the bit lines BL and BLB may be similar to each other, such that the voltage difference between the bit lines BL and BLB may not be large enough. Under this situation, the performance of sensing and amplifying the data may be unacceptable.

In response thereto, the present disclosure proposes a set of pre-amplifiers that can be used to amplify the voltage difference between a first input terminal and a second input terminal (e.g., the terminals corresponding to the two complementary bit lines) of a sense amplifier, such that the sensing yield can be improved when, for example, the cell resistance is small or the load is light.

See FIG. 2 , which is a schematic diagram illustrating a set 200 of pre-amplifiers according to an exemplary embodiment of the present disclosure. In the present embodiment, the set 200 of pre-amplifiers includes a first pre-amplifier 210 and a second pre-amplifier 220 . The first pre-amplifier 210 is coupled to a first input terminal of a sense amplifier 230 , and the second pre-amplifier 220 is coupled to a second input terminal of the sense amplifier 230 . The sense amplifier 230 may be a conventional sense amplifier which regards its complementary bit lines as the first input terminal and the second input terminal, such as the sense amplifier 100 shown in FIG. 1A , but the present disclosure is not limited thereto.

As shown in FIG. 2 , the first pre amplifier 210 includes a first switch M 1 , a second switch M 2 , a third switch M 3 , and a first capacitor C 1 . The first switch M 1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch M 1 is coupled to the predetermined voltage VDD, the second terminal of the first switch M 1 (represented by a node n 1 ) is coupled to the first input terminal of the sense amplifier 230 , and the control terminal of the first switch M 1 receives the pre-charge signal PRE. The second switch M 2 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch M 2 is coupled to the second terminal of the first switch M 1 , and the control terminal of the second switch M 2 (represented by a node n 2 ) is coupled to the second input terminal of the sense amplifier 230 .

The third switch M 3 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch M 3 is coupled to the second terminal of the second switch M 2 , the second terminal of the third switch M 3 is coupled to a ground GND, and a control terminal of the third switch M 3 receives an initializing signal INI. The first capacitor C 1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C 1 (represented by a node x 1 ) is coupled to the second terminal of the second switch M 2 .

In the present embodiment, the second terminal of the first capacitor C 1 is coupled to a first data line DL of the sense amplifier 230 , but the second terminal of the first capacitor C 1 may be coupled with other elements, which will be discussed later.

On the other hand, the second pre-amplifier 220 includes a fourth switch M 4 , a fifth switch M 5 , a sixth switch M 6 , and a second capacitor C 2 . The fourth switch M 4 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth switch M 4 is coupled to the predetermined voltage VDD, the second terminal of the fourth switch M 4 (represented by the node n 2 ) is coupled to the second input terminal of the sense amplifier 230 , and the control terminal of the fourth switch M 4 receives the pre-charge signal PRE. The fifth switch M 5 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth switch M 5 is coupled to the second terminal of the fourth switch M 4 and the control terminal of the fifth switch M 5 (represented by the node n 1 ) is coupled to the first input terminal of the sense amplifier 230 .

The sixth switch M 6 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth switch M 6 is coupled to the second terminal of the fifth switch M 5 , the second terminal of the sixth switch M 6 is coupled to the ground GND, and a control terminal of the sixth switch M 6 receives the initializing signal INI. The second capacitor C 2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C 2 (represented by a node x 2 ) is coupled to the second terminal of the fifth switch M 5 .

Similar to the first capacitor C 1 , the second terminal of the second capacitor C 2 is coupled to a second data line DLB of the sense amplifier 230 , but the second terminal of the second capacitor C 2 may be coupled with other elements, which will be discussed later.

As shown in FIG. 2 , the second switch M 2 , the third switch M 3 , the fifth switch M 5 , and the sixth switch M 6 are n-type transistors, while the first switch M 1 and the fourth switch M 4 are p-type transistors, but the present disclosure is not limited thereto.

See FIG. 3 , which shows a flow chart of a method of operating the set 200 of pre-amplifiers according to an exemplary embodiment of the present disclosure. In step S 310 , the first pre-amplifier 210 and the second pre-amplifier 220 respectively performs a discharging operation to discharge the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ) of the sense amplifier 230 after the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ) of the sense amplifier 230 are charged to the predetermined voltage VDD.

Afterwards, in step S 320 , one of the first pre-amplifier 210 and the second pre-amplifier 220 amplifies a voltage difference between the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ) of the sense amplifier 230 by terminating the discharging operation of another of the first pre-amplifier 210 and the second pre-amplifier 220 .

In one embodiment, the one of the first pre-amplifier 210 and the second pre-amplifier 220 terminating the discharging operation of the other of the first pre-amplifier 210 and the second pre-amplifier 220 performs the discharging operation faster than the other of the first pre-amplifier 210 and the second pre-amplifier 220 .

Specifically, since the capacitances of the first capacitor C 1 and the second capacitor C 2 may be different from each other, the first pre-amplifier 210 and the second pre-amplifier 220 will perform the discharging operation at different speeds. More particularly, if the capacitance of the first capacitor C 1 is higher than the capacitance of the second capacitor C 2 , the speed of the first pre-amplifier 210 performing the discharging operation will be faster than the second pre-amplifier 220 , and vice versa. That is, the voltage level of the first input terminal (i.e., the node n 1 ) will drop faster than the voltage level of the second input terminal (i.e., the node n 2 ) if the capacitance of the first capacitor C 1 is higher than the capacitance of the second capacitor C 2 , otherwise the voltage level of the first input terminal (i.e., the node n 1 ) will drop slower than the voltage level of the second input terminal (i.e., the node n 2 ).

For example, the capacitance of the first capacitor C 1 is assumed to be higher than the capacitance of the second capacitor C 2 . Therefore, the first pre-amplifier 210 may amplify the voltage difference between the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ) of the sense amplifier 230 by terminating the discharging operation of the second pre-amplifier 220 .

Specifically, since the node n 1 will be discharged to the first data line DL faster than the node n 2 being discharged to the second data line DLB under the assumption, the fifth switch M 5 will be turned off when the voltage level of the node n 1 reaches a specific voltage that is capable of turning off the fifth switch M 5 . Therefore, the node n 2 will not be further discharged, such that the discharging operation of the second pre-amplifier 220 will be terminated. On the other hand, the voltage level of the node n 1 will be continuously discharged to be lower and lower, such that the voltage difference between the nodes n 1 and n 2 can be amplified. As a result, the sensing yield of the sensing amplifier 230 can be improved when performing a sensing operation to sense the data of the memory cell based on the amplified voltage difference between the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ).

See FIG. 4A and FIG. 4B for further discussion, wherein FIG. 4A is a schematic diagram of a sensing circuit 400 for sensing data of a memory cell according to an exemplary embodiment of the present disclosure, and FIG. 4B is a waveform graph of controlling the sensing circuit 400 of FIG. 4A . In the present embodiment, the sensing circuit 400 includes the sense amplifier 100 , the first pre-amplifier 210 , and the second pre-amplifier 220 , wherein the first pre-amplifier 210 and the second pre-amplifier 220 are coupled to the first input terminal and the second input terminal of the sense amplifier 100 via the nodes n 1 and n 2 , respectively. Specifically, the first input terminal and the second input terminal of the sense amplifier 100 may be the terminals that originally correspond to the two complementary bit lines BL and BLB, but the present disclosure is not limited thereto. The operations of each of the first pre-amplifier 210 and the second pre-amplifier 220 in phases P 1 ′, P 2 ′, P 3 ′, and P 4 ′ will be discussed in the following descriptions.

In the first phase P 1 ′, the voltage level at the second terminal of the second switch M 2 (i.e., the node x 1 ) and the second terminal of the fifth switch M 5 (i.e., the node x 2 ) are reset to zero in the first phase P 1 ′ after the pre-charge signal PRE turning off the first switch M 1 and the fourth switch M 4 and the initializing signal INI turning on the third switch M 3 and the sixth switch M 6 .

In the second phase P 2 ′, the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 is charged to the predetermined voltage VDD after the pre-charge signal PRE turning on the first switch M 1 and the fourth switch M 4 and the initializing signal INI turning off the third switch M 3 and the sixth switch M 6 . Meanwhile, the first data line DL and the second data line DLB are charged to the reading voltage Vread. In this case, the voltage level of the node x 1 becomes Vdd-Vth 2 , and the voltage level of the node x 2 becomes Vdd-Vth 5 , wherein Vdd is the value of the predetermined voltage VDD, Vth 2 is the threshold voltage of the second switch M 2 , and Vth 5 is the threshold voltage of the second switch M 5 . That is, the threshold voltages of the second switch M 2 and the fifth switch M 5 will be respectively sampled at the nodes x 1 and x 2 , and hence the manufacturing process variation of the first pre-amplifier 210 and the second pre-amplifier 220 can be suppressed during the sense amplifier 100 sensing and amplifying the data. Therefore, the sensing yield can be improved, and the first pre-amplifier 210 and the second pre-amplifier 220 may be suitable for advanced technology and high accuracy applications.

In the third phase P 3 ′ where the first pre-amplifier 210 and the second pre-amplifier 230 perform the discharging operation, the first input terminal and the second input terminal of the sense amplifier 100 are discharged after the pre-charge signal PRE turning off the first switch M 1 and the fourth switch M 4 and the initializing signal INI turning off the third switch M 3 and the sixth switch M 6 .

In this case, the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 is discharged slower than the first input terminal of the sense amplifier 100 , and hence the fifth switch M 5 is turned off by the voltage level at the first input terminal (i.e., the node n 1 ) of the sense amplifier 100 after the voltage level at the first input terminal (i.e., the node n 1 ) reaches the specific voltage that is capable of turning off the fifth switch M 5 to terminate the discharging operation of the second pre-amplifier 220 . Afterwards, the voltage level of the node n 1 will be continuously discharged to be lower and lower, such that the voltage difference between the nodes n 1 and n 2 can be amplified. As a result, the sensing yield of the sensing amplifier 100 can be improved when performing the sensing operation in the fourth phase P 4 ′ to sense the data of the memory cell based on the amplified voltage difference between the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ).

In other embodiments, the first input terminal (La, the node n 1 ) of the sense amplifier may be discharged slower than the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 if the capacitance of the first capacitor C 1 is smaller than the capacitance of the second capacitor C 2 , and hence the second switch M 2 is turned off by the voltage level at the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 after the voltage level at the second input terminal (i.e., the node n 2 ) reaches the specific voltage that is capable of turning off the second switch M 2 to terminate the discharging operation of the first pre-amplifier 210 . Afterwards, the voltage level of the node n 2 will be continuously discharged to be lower and lower, such that the voltage difference between the nodes n 1 and n 2 can be amplified. As a result, the sensing yield of the sensing amplifier 100 can be improved after performing the sensing operation to sense the data of the memory cell based on the amplified voltage difference between the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ).

As mentioned in the above, the second terminal of the first capacitor C 1 and the second terminal of the second capacitor C 2 may be coupled with other elements in other embodiments.

See FIG. 5A and FIG. 5B , wherein FIG. 5A is a schematic diagram of a sensing circuit 500 for sensing data of a memory cell according to an exemplary embodiment of the present disclosure, and FIG. 5B is a waveform graph of controlling the sensing circuit 500 of FIG. 5A . In the present embodiment, the sensing circuit 500 includes the sense amplifier 100 , a first pre-amplifier 210 ′, and a second pre-amplifier 220 ′.

As shown in FIG. 5A , other than including all elements of the first pre-amplifier 210 , the first pre-amplifier 210 ′ further includes a seventh switch M 7 and an eighth switch M 8 . The seventh switch M 7 has a first terminal and a second terminal, wherein the first terminal of the seventh switch M 7 is coupled to the second terminal of the first capacitor C 1 (represented by a node y 1 ), and the second terminal of the seventh switch M 7 is coupled to a first voltage V 1 . The eighth switch M 8 has a first terminal and a second terminal, wherein the first terminal of the eighth switch M 8 is coupled to the second terminal of the first capacitor C 1 (i.e., the node y 1 ), and the second terminal of the eighth switch M 8 is coupled to a reference voltage VC higher than the first voltage V 1 but lower than the predetermined voltage VDD.

The seventh switch M 7 may be controlled by a switch signal SW. Specifically, the seventh switch M 7 may be turned off before the first input terminal (i.e., the node n 1 ) of the sense amplifier 100 is charged to the predetermined voltage VDD and turned on when the first pre-amplifier 210 ′ performs the discharging operation. On the other hand, the eighth switch M 8 may be controlled by another switch signal complementary to the switch signal SW (not shown for brevity). That is, the eighth switch M 8 is turned on before the first input terminal (i.e., the node n 1 ) of the sense amplifier 100 is charged to the predetermined voltage VDD and turned off when the first pre-amplifier 210 ′ performs the discharging operation.

As for the second pre-amplifier 220 ′, other than including all elements of the second pre-amplifier 220 , the second pre-amplifier 220 ′ further includes a ninth switch M 9 and a tenth switch M 10 . The ninth switch M 9 has a first terminal and a second terminal, wherein the first terminal of the ninth switch M 9 is coupled to the second terminal of the second capacitor C 2 (represented by a node y 2 ), and the second terminal of the ninth switch M 9 is coupled to a second voltage V 2 . The tenth switch M 10 has a first terminal and a second terminal, wherein the first terminal of the tenth switch M 10 is coupled to the second terminal of the second capacitor C 2 (i.e., the node y 2 ), and the second terminal of the tenth switch M 10 is coupled to the reference voltage VC higher than the first voltage V 1 and the second voltage V 2 .

The ninth switch M 9 may be controlled by the switch signal SW. Specifically, the ninth switch M 9 may be turned off before the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 is charged to the predetermined voltage VDD, and the ninth switch M 9 may be turned on when the second pre-amplifier 220 ′ performs the discharging operation. On the other hand, the tenth switch M 10 may be controlled by the other switch signal complementary to the switch signal SW wherein the tenth switch M 10 is turned on before the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 is charged to the predetermined voltage VDD, and the tenth switch M 10 is turned off when the second pre-amplifier 220 ′ performs the discharging operation.

The operations of each of the first pre-amplifier 210 ′ and the second pre-amplifier 220 ′ in phases P 1 ″, P 2 ″, P 3 ″, and P 4 ″ will be discussed in the following descriptions.

In the first phase P 1 ″, the voltage level at the second terminal of the second switch M 2 (i.e., the node x 1 ) and the second terminal of the fifth switch M 5 (i.e., the node x 2 ) are reset to zero in the first phase P 1 ′ after the pre-charge signal PRE turning off the first switch M 1 and the fourth switch M 4 and the initializing signal INI turning on the third switch M 3 and the sixth switch M 6 . Meanwhile, the eighth switch M 8 and the tenth switch M 10 may be turned on to feed the reference voltage VC to the second terminal of the first capacitor C 1 (i.e., the node y 1 ) and the second terminal of the second capacitor C 2 (i.e., the node y 2 ), while the seventh switch M 7 and the ninth switch M 9 are turned off by the switch signal SW.

In the second phase P 2 ″, the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 is charged to the predetermined voltage VDD after the pre-charge signal PRE turning on the first switch M 1 and the fourth switch M 4 and the initializing signal INI turning off the third switch M 3 and the sixth switch M 6 . In this case, the voltage level of the node x 1 becomes Vdd-Vth 2 , and the voltage level of the node x 2 becomes Vdd-Vth 5 , wherein Vdd is the value of the predetermined voltage VDD, Vth 2 is the threshold voltage of the second switch M 2 , and Vth 5 is the threshold voltage of the second switch M 5 . That is, the threshold voltages of the second switch M 2 and the fifth switch M 5 will be respectively sampled at the nodes x 1 and x 2 , and hence the manufacturing process variation of the first pre-amplifier 210 ′ and the second pre-amplifier 220 ′ can be suppressed during the sense amplifier 100 sensing and amplifying the data. Therefore, the sensing yield can be improved.

In the third phase P 3 ″ where the first pre-amplifier 210 ′ and the second pre-amplifier 230 ′ perform the discharging operation, the first input terminal and the second input terminal of the sense amplifier 100 are discharged after the pre-charge signal PRE turning off the first switch M 1 and the fourth switch M 4 and the initializing signal INI turning off the third switch M 3 and the sixth switch M 6 . Meanwhile, the seventh switch M 7 and the ninth switch M 9 may be turned on by the switch signal SW to respectively feed the first voltage V 1 and the second voltage V 2 to the second terminal of the first capacitor C 1 (i.e., the node y 1 ) and the second terminal of the second capacitor C 2 (i.e., the node y 2 ), while the eighth switch M 8 and the tenth switch M 10 are turned off.

In this case, the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 is discharged slower than the first input terminal of the sense amplifier 100 , and hence the fifth switch M 5 is turned off by the voltage level at the first input terminal (i.e., the node n 1 ) of the sense amplifier 100 after the voltage level at the first input terminal (i.e., the node n 1 ) reaches the specific voltage that is capable of turning off the fifth switch M 5 to terminate the discharging operation of the second pre-amplifier 220 ′. Afterwards, the voltage level of the node n 1 will be continuously discharged to be lower and lower, such that the voltage difference between the nodes n 1 and n 2 can be amplified. As a result, the sensing yield of the sensing amplifier 100 can be improved when performing the sensing operation in the fourth phase P 4 ″ to sense the data of the memory cell based on the amplified voltage difference between the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ).

In other embodiments, the first input terminal (i.e., the node n 1 ) of the sense amplifier may be discharged slower than the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 if the capacitance of the first capacitor C 1 is smaller than the capacitance of the second capacitor C 2 , and hence the second switch M 2 is turned off by the voltage level at the second input terminal (i.e., the node n 2 ) of the sense amplifier 100 after the voltage level at the second input terminal (i.e., the node n 2 ) reaches the specific voltage that is capable of turning off the second switch M 2 to terminate the discharging operation of the first pre-amplifier 210 ′. Afterwards, the voltage level of the node n 2 will be continuously discharged to be lower and lower, such that the voltage difference between the nodes n 1 and n 2 can be amplified. As a result, the sensing yield of the sensing amplifier 100 can be improved when performing the sensing operation to sense the data of the memory cell based on the amplified voltage difference between the first input terminal (i.e., the node n 1 ) and the second input terminal (i.e., the node n 2 ).

To sum up, the present disclosure proposes a sensing circuit, a set of pre-amplifiers, and an operating method of the set of the pre-amplifiers, wherein the one of the pre-amplifiers which is discharged faster can terminate the discharging operation of the other of the pre-amplifiers, such that the one of the pre-amplifiers may be continuously discharged to amplify the voltage difference between the input terminals of the sense amplifier. Therefore, when the sensing amplifier performs a sensing operation to sense the data of the memory cell based on the amplified voltage difference, the sensing yield can be improved and the sensing time can be reduced.

Further, since the threshold voltages of switches may be sampled, the manufacturing process variation can be suppressed, such that the present disclosure may be suitable for advanced technology and high accuracy applications.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.