Power-on control circuit

The invention relates to a control circuit, and more particularly to a control circuit configured to control a pad.

With the ongoing development of various technologies, there has been a marked increase in the types and functions of electronic devices available on the market. Generally speaking, there are many integrated circuits (ICs) disposed in each electronic device. Each IC may receive many voltages, which are quite different from each other. When one of these voltages fails to reach a target value, the IC that runs on this voltage may start to work abnormally and generate errors.

In accordance with an embodiment, a power-on control circuit controls a first output switch and a second output switch and comprises a detecting circuit, a switching circuit, and a setting circuit. The detecting circuit detects a first voltage to generate a detection signal to a first node. The switching circuit receives the first voltage and a second voltage and transmits the first or second voltage to a second node according to the voltage level of the first node. The setting circuit is coupled to the first and second nodes, controls the first and second output switches, and generates a feedback signal to the first node according to a voltage level of the second node. When the first voltage reaches a first pre-determined value and the second voltage has not reached a second pre-determined value, the switching circuit transmits the second voltage to the second node according to the detection signal. When the first voltage reaches the first pre-determined value and the second voltage reaches the second pre-determined value, the switching circuit transmits the first voltage to the second node according to the feedback signal.

In accordance with another embodiment, a control circuit controls the voltage level of a pad and comprises a first output switch, a second output switch, a core circuit, and a power-on control circuit. The first output switch is configured to provide voltage from a first voltage source to the pad. The second output switch is configured to provide a ground voltage to the pad. The core circuit is coupled to the first voltage source and a second voltage source. During a normal period, the core circuit controls the first and second output switches. The power-on control circuit is coupled to the first and second voltage sources. During an initial period, the power-on control circuit controls the first and second output switches. The voltages provided by the first and second voltage sources are gradually increased during the initial period. The power-on control circuit comprises a detecting circuit, a switching circuit and a setting circuit. The detecting circuit detects the voltage provided by the first voltage source to generate a detection signal to a first node. The switching circuit is coupled to the first and second voltage sources and transmits the voltage provided by the first or second voltage sources to a second node according to the signal of the first node. The setting circuit is coupled to the first and second nodes, controls the first and second output switches according to a voltage level of the second node, and generates a feedback signal to the first node. When the voltage provided by the first voltage source reaches a first pre-determined value and the voltage provided by the second voltage source has not reached a second pre-determined value, the switching circuit transmits the voltage provided by the second voltage source to the second node according to the detection signal. When the voltage provided by the first voltage source reaches the first pre-determined value and the voltage provided by the second voltage source reaches the second pre-determined value, the switching circuit transmits the voltage provided by the first voltage source to the second node according to the feedback signal.

The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an exemplary embodiment of a control circuit, according to various aspects of the present disclosure.

FIG. 2 is a schematic diagram of an exemplary embodiment of a power-on control circuit, according to various aspects of the present disclosure.

FIG. 3A is a schematic diagram of an exemplary embodiment of a detecting circuit, according to various aspects of the present disclosure.

FIG. 3B is a schematic diagram of another exemplary embodiment of the detecting circuit, according to various aspects of the present disclosure.

FIG. 4A is a schematic diagram of an exemplary embodiment of a switching circuit, according to various aspects of the present disclosure.

FIG. 4B is a schematic diagram of another exemplary embodiment of the switching circuit, according to various aspects of the present disclosure.

FIG. 4C is a schematic diagram of another exemplary embodiment of the switching circuit, according to various aspects of the present disclosure.

FIG. 5 is a schematic diagram of another exemplary embodiment of a setting circuit, according to various aspects of the present disclosure.

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

FIG. 1 is a schematic diagram of an exemplary embodiment of a control circuit, according to various aspects of the present disclosure. The control circuit 110 is coupled to a pad 120 and controls the voltage level of the pad 120 . In this embodiment, the control circuit 110 comprises a core circuit 111 , a power-on control circuit 112 , control switches 113 and 114 , and output switches 115 and 116 .

The core circuit 111 is coupled to voltage sources 117 and 118 to receive voltages V 1 and V 2 . In a normal period, the voltage V 1 is greater than a first pre-determined value, and the voltage V 2 is greater than a second pre-determined value. At this period, the core circuit 111 generates control signals S C1 and S C2 according to the voltages V 1 and V 2 . The control signal S C1 is utilized to turn on or turn off the output switch 115 . The control signal S C2 is utilized to turn on or turn off the output switch 116 . In this embodiment, when the output switch 115 is turned, the output switch 116 is turned off. Therefore, the output switch 115 provides the voltage V 1 to the pad 120 . However, when the output switch 116 is turned on, the output switch 115 is turned off. At this time, the output switch 116 provides the ground level GND to the pad 120 .

However, during an initial period, the voltage source 117 starts providing the voltage V 1 , and the voltage source 118 starts providing the voltage V 2 . During the initial period, the voltages V 1 and V 2 are gradually increased from an initial level, such as 0V. When the voltage V 1 has not reached a first pre-determined value (e.g. 0.7V) and/or the voltage V 2 has not reached a second pre-determined value (e.g. 0.9V), if the core circuit 111 utilizes the voltages V 1 and V 2 to generate the control signals S C1 and S C2 , the core circuit 111 may turn on both the output switches 115 and 116 such that a leakage current passes through the output switches 115 and 116 . In this embodiment, during the initial period, the power-on control circuit 112 controls the output switches 115 and 116 to avoid that the output switches 115 and 116 are turned on simultaneously.

As shown in FIG. 1 , the power-on control circuit 112 generates control signals S C3 and S C4 to turn off the output switches 115 and 116 . In this embodiment, the power-on control circuit 112 turns off the output switches 115 and 116 via the control switches 113 and 114 , but the disclosure is not limited thereto. In other embodiments, the power-on control circuit 112 may directly control the output switches 115 and 116 to avoid the output switches 115 and 116 are turned on simultaneously.

However, when the voltage V 1 is greater than the first pre-determined value and the voltage V 2 is greater than the second pre-determined value, the core circuit 111 controls the output switches 115 and 116 . In this embodiment, the output switch 115 is coupled to the voltage source 117 to receive the voltage V 1 and provides the voltage V 1 to the pad 120 according to the control signal S C1 . Additionally, the output switch 116 receives the ground voltage GND and provides the ground voltage GND to the pad 120 according to the control signal S C2 .

In one embodiment, the output switch 115 is a P-type transistor P 11 . The gate of the P-type transistor P 11 receives the control signal S C1 and is coupled to the control switch 113 . The source of the P-type transistor P 11 is coupled to the voltage source 117 to receive the voltage V 1 . The drain of the P-type transistor P 11 is coupled to the pad 120 . In the disclosure, the circuit structure of the output switch 115 is not limited. Any circuit can serve as the output switch 115 , as long as the circuit is capable of providing a high level to the pad 120 according to the control signal S C1 . In other embodiments, the output switch 115 is an N-type transistor.

Furthermore, the output switch 116 is an N-type transistor N 11 . As shown in FIG. 1 , the gate of the N-type transistor N 11 receives the control signal S C2 and is coupled to the control switch 114 . The source of the N-type transistor N 11 receives the ground voltage GND. The drain of the N-type transistor N 11 is coupled to the pad 120 . In the disclosure, the circuit structure of the output switch 116 is not limited. Any circuit can serve as the output switch 116 , as long as the circuit is capable of providing a low level to the pad 120 according to the control signal S C2 . In other embodiments, the output switch 116 is a P-type transistor.

In this embodiment, the control switch 113 is a P-type transistor P 12 . The gate of the P-type transistor P 12 receives the control signal S C3 . The source of the P-type transistor P 12 is coupled to the voltage source 117 to receive the voltage V 1 . The drain of the P-type transistor P 12 is coupled to the gate of the P-type transistor P 11 . In the disclosure, the circuit structure of the control switch 113 is not limited. Any circuit can serve as the control switch 113 , as long as the circuit is capable of turning on or off the output switch 115 according to the control signal S C3 . In other embodiments, the control switch 113 is an N-type transistor.

In this embodiment, the control switch 114 is an N-type transistor N 12 . The gate of the N-type transistor N 12 receives the control signal S C4 . The source of the N-type transistor N 12 receives the ground voltage GND. The drain of the N-type transistor N 12 is coupled to the gate of the N-type transistor N 11 . In the disclosure, the circuit structure of the control switch 114 is not limited. Any circuit can serve as the control switch 114 , as long as the circuit is capable of turning on or off the output switch 116 according to the control signal S C4 . In other embodiments, the control switch 114 is a P-type transistor.

In an initial period, since the voltage V 1 is not greater than the first pre-determined value and/or voltage V 2 is not greater than the second pre-determined value, the power-on control circuit 112 turns on the control switches 113 and 114 to turn off the output switches 115 and 116 . In a normal period, voltage V 1 is greater than the first pre-determined value and the voltage V 2 is greater than the second pre-determined value, the core circuit 111 controls the output switches 115 and 116 . At this period, the power-on control circuit 112 may turn off the control switches 113 and 114 .

In one embodiment, during the normal period, the voltage source 117 continuously increases the voltage V 1 until the voltage V 1 reaches a first target value. During the normal period, the voltage source 118 continuously increases the voltage V 2 until the voltage V 2 reaches a second target value. When the voltage V 1 reaches the first target value, the voltage V 1 is provided as an input/output power. When the voltage V 2 reaches the second target value, the voltage V 2 is provided as a core power. In this embodiment, the first target value is higher than the second target value. In one embodiment, the first target value is approximately 3.3V, and the second target value is approximately 1.8V.

FIG. 2 is a schematic diagram of an exemplary embodiment of a power-on control circuit, according to various aspects of the present disclosure. As shown in FIG. 2 , the power-on control circuit 200 comprises a detecting circuit 210 , a switching circuit 220 and a setting circuit 230 . In this embodiment, the detecting circuit 210 is coupled to the node ND 2 and detects the voltage V 1 provided by the voltage source 117 to generate a detection signal S DT to the node ND 1 . For example, during the initial period, the voltage source 117 gradually increases the voltage V 1 . When the voltage V 1 reaches a first pre-determined value (e.g. 0.7V), the detecting circuit 210 transmits the voltage V 1 to the node ND 1 . At this time, the node ND 1 may have a high level. On the contrary, when the voltage V 1 has not reached the first pre-determined value, the detecting circuit 210 does not transmit the voltage V 1 to the node ND 1 . In the present disclosure, the circuit structure of the detecting circuit 210 is not limited thereto. Any circuit can serve as the detecting circuit 210 , as long as the circuit is capable of detecting the voltage V 1 .

The switching circuit 220 is coupled to the voltage sources 117 and 118 to receive the voltages V 1 and V 2 . The switching circuit 220 transmits the voltage V 1 or V 2 to the node ND 2 according to the signal of the node ND 1 . In this embodiment, when the node ND 1 has a high level, the switching circuit 220 transmits the voltage V 2 to the node ND 2 . However, when the node ND 1 has a low level, the switching circuit 220 transmits the voltage V 1 to the node ND 2 . The circuit structure of the switching circuit 220 is not limited in the invention. Any circuit can serve as the switching circuit 220 , as long as the circuit is capable of providing the voltage V 1 or V 2 to the node ND 2 according to the voltage level of the node ND 1 .

The setting circuit 230 is coupled to the nodes ND 1 and ND 2 and generates a feedback signal S FB to the node ND 1 according to the voltage level of the node ND 2 . In this embodiment, when the switching circuit 220 transmits the voltage V 2 to the node ND 2 , since the voltage V 2 has not reached a second pre-determined value (e.g. 0.9V), the voltage level of the node ND 2 is a low level. At this time, the setting circuit 230 outputs the feedback signal S FB which as a high level to the node ND 1 . In one embodiment, the voltage level of the ND 2 is opposite to the voltage level of the feedback signal S FB . For example, when the voltage level of the ND 2 is a high level, the feedback signal S FB is at a low level. When the voltage level of the ND 2 is a low level, the feedback signal S FB is at a high level.

Since the node ND 1 has a high level, the switching circuit 220 still outputs the voltage V 2 to the node ND 2 . However, when the voltage V 2 reaches a second pre-determined value, the voltage level of the node ND 2 is changed from a low level to a high level. Therefore, the setting circuit 230 outputs the feedback signal S FB which has a low level to the node ND 1 . Since the voltage level of the node ND 1 is the low level, the switching circuit 220 outputs the voltage V 1 to the node ND 2 . Therefore, the voltage level of the node ND 2 is still at the high level such that the voltage level of the node ND 1 is the low level.

In this embodiment, when the voltage level of the node ND 2 is the low level, the setting circuit 230 outputs the control signal S C3 which has a low level and the control signal S C4 which has a high level. Therefore, the control switches 113 and 114 shown in FIG. 1 are turned on such that the output switches 115 and 116 are turned off. However, when the voltage level of the node ND 2 is the high level, the setting circuit 230 outputs the control signal S C3 which has a high level and the control signal S C4 which has a low level. Therefore, the control switches 113 and 114 shown in FIG. 1 are turned off. At this time, the output switches 115 and 116 are controlled by the core circuit 111 .

In another embodiment, the power-on control circuit 200 further comprises a setting circuit 240 . The setting circuit 240 is configured to set an initial level of the node ND 2 . In one embodiment, the setting circuit 240 is a capacitor C. The capacitor C is coupled to the node ND 2 to set the initial level of the node ND 2 at a low level. In this embodiment, the initial level of the node ND 2 is equal to the ground voltage GND.

FIG. 3A is a schematic diagram of an exemplary embodiment of a detecting circuit, according to various aspects of the present disclosure. In this embodiment, the detecting circuit 210 is a P-type transistor Pdet. The source of the P-type transistor Pdet is coupled to the voltage source 117 to receive the voltage V 1 . The drain of the P-type transistor Pdet outputs the detection signal S DT and is coupled to the node ND 1 . The gate of the P-type transistor Pdet is coupled to the node ND 2 . When the voltage level of the node ND 2 is a low level and the voltage V 2 provided by the voltage source 117 reaches the first pre-determined value, the P-type transistor Pdet is turned on to transmit the voltage V 1 generated by the voltage source 117 to the node ND 1 . At this time, the voltage level of the node ND 1 is a high level.

FIG. 3B is a schematic diagram of another exemplary embodiment of the detecting circuit, according to various aspects of the present disclosure. In this embodiment, the detecting circuit 210 comprises an N-type transistor Ndet and an inverter 300 . The drain of the N-type transistor Ndet is coupled to the voltage source 117 to receive the voltage V 1 . The source of the N-type transistor Ndet is coupled to the node ND 1 . The gate of the N-type transistor Ndet is coupled to the output terminal of the inverter 300 .

The input terminal of the inverter 300 is coupled to the node ND 2 . The output terminal of the inverter 300 is coupled to the gate of the N-type transistor Ndet. In this embodiment, the inverter 300 comprises a P-type transistor 310 and an N-type transistor 320 . The gate of the P-type transistor 310 is coupled to the gate of the N-type transistor 320 to serve as the input terminal of the inverter 300 . The source of the P-type transistor 310 receives the voltage V 1 of the voltage source 117 . The drain of the P-type transistor 310 is coupled to the drain of the N-type transistor 320 and the gate of the N-type transistor Ndet. The source of the N-type transistor 320 receives the ground voltage GND.

When the voltage level of the node ND 2 is a low level, the P-type transistor 310 is turned on to turn on the N-type transistor Ndet. Therefore, the voltage level of the node ND 1 is equal to the voltage V 1 of the voltage source 117 . When the voltage level of the node ND 2 is a high level, the N-type transistor 320 is turned on to turn off the N-type transistor Ndet. Therefore, the N-type transistor Ndet does not transmit the voltage V 1 provided by the voltage source 117 to the node ND 1 .

FIG. 4A is a schematic diagram of an exemplary embodiment of a switching circuit, according to various aspects of the present disclosure. In this embodiment, the switching circuit 220 comprises switches 411 and 412 . The switch 411 is coupled to the voltage source 118 to receive the voltage V 2 and transmits the voltage V 2 to the node ND 2 according to the voltage level of the node ND 1 . For example, when the voltage level of the node ND 1 is a low level, the switch 411 does not transmit the voltage V 2 to the node ND 2 . When voltage level of the node ND 1 is a high level, the switch 411 transmits the voltage V 2 to the node ND 2 . In this embodiment, the switch 411 is an N-type transistor N 41 . The drain of the N-type transistor N 41 is coupled to the voltage source 118 to receive the voltage V 2 . The source of the N-type transistor N 41 is coupled to the node ND 2 . The gate of the N-type transistor N 41 is coupled to the node ND 1 .

The switch 412 is coupled to the voltage source 117 to receive the voltage V 1 and transmits the voltage V 1 to the node ND 2 according to the voltage level of the node ND 1 . For example, when the voltage level of the node ND 1 is a low level, the switch 412 transmits the voltage V 1 to the node ND 2 . When voltage level of the node ND 1 is a high level, the switch 412 does not transmit the voltage V 1 to the node ND 2 . In this embodiment, the switch 412 is a P-type transistor P 41 . The source of the P-type transistor P 41 receives the voltage V 1 of the voltage source 117 . The drain of the P-type transistor P 41 is coupled to the node ND 2 . The gate of the P-type transistor P 41 is coupled to the node ND 1 .

FIG. 4B is a schematic diagram of another exemplary embodiment of the switching circuit, according to various aspects of the present disclosure. In this embodiment, the switching circuit 220 comprises switches 421 and 422 . The switch 421 receives the voltage V 2 provided by the voltage source 118 and outputs the voltage V 2 provided by the voltage source 118 to the node ND 2 . For example, when the voltage level of the node ND 1 is a low level, the switch 421 does not output the voltage V 2 provided by the voltage source 118 to the node. When the voltage level of the node ND 1 is a high level, the switch 421 outputs the voltage V 2 provided by the voltage source 118 to the node ND 2 .

As shown in FIG. 4B , the switch 421 comprises a P-type transistor P 42 and an inverter 423 . The source of the P-type transistor P 42 is coupled to the voltage source 118 to receive the voltage V 2 . The drain of the P-type transistor P 42 is coupled to the node ND 2 . The gate of the P-type transistor P 42 is coupled to the output terminal of the inverter 423 . The input terminal of the inverter 423 is coupled to the node ND 1 . In this embodiment, the inverter 423 comprises a P-type transistor P 43 and an N-type transistor N 42 . The source of the P-type transistor P 43 receives the voltage V 1 of the voltage source 117 . The drain of the P-type transistor P 43 is coupled to the gate of the P-type transistor P 42 . The gate of the P-type transistor P 43 is coupled to the node ND 1 . The drain of the N-type transistor N 42 is coupled to the gate of the P-type transistor P 42 . The source of the N-type transistor N 42 receives the ground voltage GND. The gate of the N-type transistor N 42 is coupled to the node ND 1 .

In this embodiment, the switch 422 receives the voltage V 1 generated by the voltage source 117 and transmits the voltage V 1 to the node ND 2 according to the voltage level of the node ND 1 . For example, when the voltage level of the node ND 1 is a low level, the switch 422 transmits the voltage V 1 to the node ND 2 . When the voltage level of the node ND 1 is a high level, the switch 422 does not transmit the voltage V 1 to the node ND 2 . In one embodiment, the switch 422 is a P-type transistor P 44 . The source of the P-type transistor P 44 is coupled to the voltage source 117 to receive the voltage V 1 . The drain of the P-type transistor P 44 is coupled to the node ND 2 . The gate of the P-type transistor P 44 is coupled to the node ND 1 .

FIG. 4C is a schematic diagram of another exemplary embodiment of the switching circuit, according to various aspects of the present disclosure. In this embodiment, the switching circuit 220 comprises switches 431 and 432 . The switch 431 receives the voltage V 2 generated by the voltage source 118 and transmits the voltage V 2 to the node ND 2 according to the voltage level of the node ND 1 . For example, when the voltage level of the node ND 1 is a low level, the switch 431 does not transmit the voltage V 2 to the node ND 2 . When the voltage level of the node ND 1 is a high level, the switch 431 transmits the voltage V 2 to the node ND 2 . In this embodiment, the switch 431 comprises an N-type transistor N 43 . The drain of the N-type transistor N 43 receives the voltage V 2 generated by the voltage source 118 . The source of the N-type transistor N 43 is coupled to the node ND 2 . The gate of the N-type transistor N 43 is coupled to the node ND 1 .

In this embodiment, the switch 432 receives the voltage V 1 of the voltage source 117 and transmits the voltage V 1 of the voltage source 117 to the node ND 2 according to the voltage level of the node ND 1 . For example, when the voltage level of the node ND 1 is a low level, the switch 432 transmits the voltage V 1 of the voltage source 117 to the node ND 2 . When the voltage level of the node ND 1 is a high level, the switch 432 does not transmit the voltage V 1 of the voltage source 117 to the node ND 2 . As shown in FIG. 4C , the switch 432 comprises an N-type transistor N 44 and an inverter 433 .

The drain of the N-type transistor N 44 receives the voltage V 1 of the voltage source 117 . The source of the N-type transistor N 44 is coupled to the node ND 2 . The gate of the N-type transistor N 44 is coupled to the output terminal of the inverter 432 . The input terminal of the inverter 432 is coupled to the node ND 1 . In this embodiment, the inverter 432 comprises a P-type transistor P 45 and an N-type transistor N 45 . The source of the P-type transistor P 45 receives the voltage V 1 of the voltage source 117 . The drain of the P-type transistor P 45 is coupled to the gate of the N-type transistor N 44 . The gate of the P-type transistor P 45 is coupled to the node ND 1 . The drain of the N-type transistor N 45 is coupled to the gate of the N-type transistor N 44 . The source of the N-type transistor N 45 receives the ground voltage GND. The gate of the N-type transistor N 45 is coupled to the node ND 1 .

FIG. 5 is a schematic diagram of another exemplary embodiment of a setting circuit, according to various aspects of the present disclosure. The setting circuit 230 generates the feedback signal S FB to the node ND 1 according to the voltage level of the node ND 2 and generates the control signals S C3 and S C4 . For example, when the voltage level of the node ND 2 is a low level, the setting circuit 230 generates the control signal S C3 which has a low level and the setting circuit 230 generates the control signal S C4 which has a high level. At this time, the feedback signal S FB is at a high level. When the voltage level of the node ND 2 is a high level, the setting circuit 230 generates the control signal S C3 which has a high level and the setting circuit 230 generates the control signal S C4 which has a low level. At this time, the feedback signal S FB is at a low level.

In this embodiment, the setting circuit 230 comprises a buffer 510 and inverters 520 and 530 . The buffer 510 is coupled to the node ND 2 and outputs the control signals S C3 and S C4 to control the output switches 115 and 116 shown in FIG. 1 . In the present disclosure, the circuit structure of the buffer 510 is not limited. In one embodiment, the buffer 510 comprises inverters 511 and 512 . The input terminal of the inverter 511 is coupled to the node ND 2 . The output terminal of the inverter 511 is coupled to the input terminal of the inverter 512 . The output terminal of the inverter 512 is coupled to the input terminals of the inverters 520 and 530 and outputs the control signal S C3 . In this embodiment, the inverter 511 comprises a P-type transistor P 53 and an N-type transistor N 53 . Furthermore, the inverter 512 comprises a P-type transistor P 54 and an N-type transistor N 54 .

The source of the P-type transistor P 53 receives the voltage V 1 provided by the voltage source 117 . The drain of the P-type transistor P 53 is coupled to the input terminal of the inverter 512 . The gate of the P-type transistor P 53 is coupled to the node ND 2 . The drain of the N-type transistor N 53 is coupled to the drain of the P-type transistor P 53 . The source of the N-type transistor N 53 receives the ground voltage GND. The gate of the N-type transistor N 53 is coupled to the gate of the P-type transistor P 53 . The source of the P-type transistor P 54 receives the voltage V 1 of the voltage source 117 . The drain of the P-type transistor P 54 is coupled to the input terminals of the inverters 520 and 530 . The gate of the P-type transistor P 54 is coupled to the drains of the P-type transistor P 53 and the N-type transistor N 53 . The drain of the N-type transistor N 54 is coupled to the drain of the P-type transistor P 54 . The source of the N-type transistor N 54 receives the ground voltage GND. The gate of the N-type transistor N 54 is coupled to the gate of the P-type transistor P 54 .

The input terminal of the inverter 520 receives the control signal S C3 . The output terminal of the inverter 520 outputs the control signal S C4 . The inverter 520 generates the control signal S C4 according to the control signal S C3 to control the output switch 116 shown in FIG. 1 . In this embodiment, when the voltage level of the control signal S C3 is a high level, the voltage level of the control signal S C4 is a low level. When the voltage level of the control signal S C3 is a low level, the voltage level of the control signal S C4 is a high level. The circuit structure of the inverter 520 is not limited in the present invention. In one embodiment, the inverter 520 comprises a P-type transistor P 52 and an N-type transistor N 52 . The source of the P-type transistor P 52 receives the voltage V 1 generated by the voltage source 117 . The drain of the P-type transistor P 52 is coupled to the drain of the N-type transistor N 52 to output the control signal S C4 . The gate of the P-type transistor P 52 is coupled to the gate of the N-type transistor N 52 and the drain of the P-type transistor P 54 . The source of the N-type transistor N 52 receives the ground voltage GND.

The input terminal of the inverter 530 receives the control signal S C3 . The output terminal of the inverter 530 outputs the feedback signal S FB . In this embodiment, when the control signal S C3 is at a high level, the feedback signal S FB is at a low level. When the control signal S C3 is at a low level, the feedback signal S FB is at a high level. As shown in FIG. 5 , the inverter 530 comprises a P-type transistor P 51 and an N-type transistor N 51 . The source of the P-type transistor P 51 receives the voltage V 1 provided by the voltage source 117 . The drain of the P-type transistor P 51 is coupled to the node ND 1 . The gate of the P-type transistor P 51 is coupled to the gate of the P-type transistor P 52 . The drain of the N-type transistor N 51 is coupled to the node ND 1 . The source of the N-type transistor N 51 receives the ground voltage GND. The gate of the N-type transistor N 51 is coupled to the gate of the P-type transistor P 51 .

When the voltage V 2 provided by the voltage source 118 has not reached a second pre-determined value, the level of the node ND 2 is a low level. Therefore, the setting circuit 230 outputs the feedback signal S FB , which has a high level. At this time, the control signal S C3 is at a low level and the control signal S C4 is at a high level. However, when the voltage V 2 provided by the voltage source 118 reaches the second pre-determined value, the level of the node ND 2 is a high level. Therefore, the setting circuit 230 outputs the feedback signal S FB having a low level. At this time, the control signal S C3 is at a high level, and the control signal S C4 is at a low level.

Taking FIG. 1 as an example, when the voltage V 2 provided by the voltage source 118 has not reached a second pre-determined value, the power-on control circuit 112 utilizes the control signals S C3 and S C4 to turn off the output switches 115 and 116 to avoid a leakage current passing through the output switches 115 and 116 . When the voltage V 2 provided by the voltage source 118 reaches the second pre-determined value, the power-on control circuit 112 does not control the output switches 115 and 116 . At this time, the voltage V 1 provided by the voltage source 117 and the voltage V 2 provided by the voltage source 118 are enough to make the core circuit 111 work normally. Therefore, the core circuit 111 controls the output switches 115 and 116 to adjust the voltage level of the pad 120 .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). For example, it should be understood that the system, device and method may be realized in software, hardware, firmware, or any combination thereof. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.