Memory cell with a read selection transistor and a program selection transistor

1. Field of the Invention

The present invention is related to a memory cell, especially related to a memory cell having a read selection transistor and a program selection transistor.

2. Description of the Prior Art

Non-volatile memories (NVM) are capable of storing the information even when no power is supplied to the memory blocks. Due to the special characteristics, non-volatile memories are widely used in many kinds of applications. Programmable read-only memory (ROM) is a non-volatile memory commonly used by the field. In prior art, the programmable read-only memory includes rows of fuses, and the fuses can be burnt down by applying electricity to program the data to be stored. However, once the fuse is burnt down, it cannot be recovered. Therefore, after the programmable read-only memory is programmed the first time, it cannot be programmed again, and can only be read by other circuits.

Presently, the programmable read-only memory usually adopts anti-fuse capacitors to replace the fuses. By applying a high voltage to rupture the anti-fuse capacitor, the resistance of the anti-fuse capacitor would be altered and the data can be programmed. With the anti-fuse capacitor, the efficiency of the chip probe (CP) test and the final test (FT) can be improved, resulting in a higher yield rate of the programmable read-only memory. In addition, to control each memory cell of the programmable read-only memory, the programmable read-only memory has to be able to perform program operations and read operations to the desired memory cells. Therefore, to layout the memory cells efficiently while maintaining the flexibility of operations can be challenging.

One embodiment discloses a memory cell. The memory cell includes a read selection transistor, a program selection transistor, and an anti-fuse capacitor.

The read selection transistor has a first terminal coupled to a bit line, a second terminal, and a control terminal coupled to a read word line. The program selection transistor has a first terminal coupled to the second terminal of the read selection transistor, a second terminal coupled to a high voltage control line, and a control terminal coupled to a program word line. The anti-fuse capacitor has a first terminal coupled to the second terminal of the read selection transistor, and a second terminal coupled to a low voltage control line.

Another embodiment discloses a memory array. The memory array includes a plurality of bit lines, a plurality of read word lines, a plurality of program word lines, a plurality of high voltage control lines, a plurality of low voltage control lines, and a plurality of rows of memory cells.

Each memory cell includes a read selection transistor, a program selection transistor, and an anti-fuse capacitor. The read selection transistor has a first terminal coupled to a corresponding bit line, a second terminal, and a control terminal coupled to a corresponding read word line. The program selection transistor has a first terminal coupled to the second terminal of the read selection transistor, a second terminal coupled to a corresponding high voltage control line, and a control terminal coupled to a corresponding program word line. The anti-fuse capacitor has a first terminal coupled to the second terminal of the read selection transistor, and a second terminal coupled to a corresponding low voltage control line.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 shows a memory cell according to one embodiment of the present invention.

FIG. 2 shows signal voltages received by memory cell in FIG. 1 during the program operation.

FIG. 3 shows signal voltages received by memory cell in FIG. 1 during the read operation.

FIG. 4 shows a memory array according to one embodiment of the present invention.

FIG. 5 shows signal voltages received by the memory array in FIG. 4 during the program operation of a memory cell.

FIG. 6 shows signal voltages received by the memory array in FIG. 4 during the read operation of a memory cell.

FIG. 1 shows a memory cell 100 according to one embodiment of the present invention. The memory cell 100 includes a read selection transistor 110 , a program selection transistor 120 , and an anti-fuse capacitor 130 .

The read selection transistor 110 has a first terminal, a second terminal, and a control terminal. The first terminal of the read selection transistor 110 is coupled to a bit line BL, and the control terminal of the read selection transistor 110 is coupled to a read word line RWL. The program selection transistor 120 has a first terminal, a second terminal, and a control terminal. The first terminal of the program selection transistor 120 is coupled to the second terminal of the read selection transistor 110 , the second terminal of the program selection transistor 120 is coupled to a high voltage control line HVL, and the control terminal of the program selection transistor 120 is coupled to a program word line PWL. The anti-fuse capacitor 130 has a first terminal and a second terminal. The first terminal of the anti-fuse capacitor 130 is coupled to the second terminal of the read selection transistor 110 , and the second terminal of the anti-fuse capacitor 130 is coupled to a low voltage control line LVL.

In FIG. 1 , the read selection transistor 110 can be an N-type transistor, and the program selection transistor 120 can be a P-type transistor. Consequently, when the program selection transistor 120 is turned on to pass the high voltage on the high voltage control line HVL to the anti-fuse capacitor 130 , the program selection transistor 120 can be turned on by a low voltage, which can help to simplify the power design of the memory cell.

In addition, the anti-fuse capacitor 130 can be implemented by an N-type transistor. For example, the first terminal of the anti-fuse capacitor 130 can be the gate structure of the N-type transistor, and the second terminal of the anti-fuse capacitor 130 can be the N-type doped region.

FIG. 2 shows the signal voltages received by the memory cell 100 during the program operation. During the program operation of the memory cell 100 , the bit line BL, the read word line RWL, and the program word line PWL are all at the first voltage V 1 , the high voltage control line HVL is at the second voltage V 2 , and the low voltage control line LVL is at the third voltage V 3 . In some embodiments, the second voltage V 2 can be higher than the first voltage V 1 , and the first voltage V 1 can be higher than the third voltage V 3 . For example, the second voltage V 2 can be 4V, the first voltage V 1 can be 0V, and the third voltage V 3 can be −2V.

During the program operation, the read selection transistor 110 can be turned off, and the program selection transistor 120 can be turned on. Therefore, the first terminal of the anti-fuse capacitor 130 would receive the second voltage V 2 on the high voltage control line HVL through the program selection transistor 120 , and the second terminal of the anti-fuse capacitor 130 would receive the third voltage V 3 on the low voltage control line LVL. In this case, the big voltage gap between the second voltage V 2 and the third voltage V 3 can rupture the anti-fuse capacitor 130 , so the data can be stored in the memory cell 100 .

FIG. 3 shows the signal voltages received by memory cell 100 during the read operation. During the read operation of the memory cell 100 , the read word line RWL, the program word line PWL, and the low voltage control line LVL are all at the fourth voltage V 4 , and the high voltage control line HVL is at the first voltage V 1 . In some embodiments, the fourth voltage V 4 can be higher than the first voltage V 1 , and the fourth voltage V 4 should be high enough to turn on the read selection transistor 110 and turn off the program selection transistor 120 . In addition, the fourth voltage V 4 can be lower than the second voltage V 2 . For example, the second voltage V 2 can be 4V, the first voltage V 1 can be 0V, and the fourth voltage V 4 can be 1.2V.

During the read operation, the read selection transistor 110 can be turned on, and the program selection transistor 120 can be turned off. In this case, the second terminal of the anti-fuse capacitor 130 can receive the fourth voltage V 4 on the low voltage control line LVL. Since the anti-fuse capacitor 130 may have different characteristics before and after being ruptured, the bit line BL would be at different voltages according to the situations. For example, if the anti-fuse capacitor 130 has been ruptured, that is, if the memory cell 100 has been programmed, the bit line BL would be charged to a voltage close to the fourth voltage V 4 through the read selection transistor 110 . In contrast, if the anti-fuse capacitor 130 has not been ruptured, that is, if the memory cell 100 has not been programmed, then the bit line BL would be at the first voltage V 1 . Therefore, by identifying the voltage on the bit line BL, the data stored in the memory cell 100 can be identified.

FIG. 4 shows a memory array 10 according to one embodiment of the present invention. The memory array 10 includes M bit lines BL 1 to BLM, N read word lines RWL 1 to RWLN, M program word lines PWL 1 to PLWM, K high voltage control lines HVL 1 to HVLK, N low voltage control lines LVL 1 to LVLN, and a plurality of memory cells 100 ( 1 , 1 ) to 100 (M, N). N and M are positive even number, and K can be half of N.

The memory cells 100 ( 1 , 1 ) to 100 (M, N) can be implemented by the memory cell 10 shown in FIG. 1 , that is, each of the memory cells 100 ( 1 , 1 ) to 100 (M, N) may include a read selection transistor 110 , a program selection transistor 120 , and an anti-fuse capacitor 130 , and can be coupled to a corresponding bit line, a corresponding read word line, a corresponding program word line, a corresponding high voltage control line, and a corresponding low voltage control line.

In FIG. 4 , the memory cells 100 ( 1 , 1 ) to 100 (M, N) can be disposed in rows, for example, the memory cells 100 ( 1 , 1 ) to 100 (M, 1 ) can be disposed in the same row, and the memory cells 100 ( 1 , N) to 100 (M, N) can be disposed in the same row. In this case, memory cells disposed in the same row can be coupled to the same read word line, the same low voltage control line, and the same high voltage control line. Also, memory cells disposed in the same row can be coupled to different program word lines and different bit lines.

For example, the memory cells 100 ( 1 , 1 ) to 100 (M, 1 ) can be coupled to the read word line RWL 1 , the low voltage control line LVL 1 , and the high voltage control line HVL 1 . Also, the memory cell 100 ( 1 , 1 ) is coupled to the program word line PWL 1 and the bit line BL 1 , while the memory cell 100 (M, 1 ) is coupled to the program word line PWLM and the bit line BLM.

In addition, memory cells disposed in the same column can be coupled to the same program word line and the same bit line. For example, the memory cells 100 ( 1 , 1 ) and 100 ( 1 , N) are disposed in the same column, and the memory cells 100 (M, 1 ) and 100 (M, N) are disposed in the same column. The memory cells 100 ( 1 , 1 ) and 100 ( 1 , N) can be coupled to the program word line PWL 1 and the bit line BL 1 , while the memory cells 100 (M, 1 ) and 100 (M, N) can be coupled to the program word line PWLM and the bit line BLM.

In FIG. 4 , adjacent memory cells in the same column may be coupled with each other for further reducing the layout area and simplifying the routing. For example, the adjacent memory cells 100 ( 1 , 1 ) and 100 ( 1 , 2 ) are disposed in the same column, and the second terminal of the program selection transistor 120 of the memory cell 100 ( 1 , 1 ) can be coupled to the second terminal of the program selection transistor 120 of the memory cell 100 ( 1 , 2 ). In this case, the program selection transistors 120 of the memory cell 100 ( 1 , 1 ) and the program selection transistors 120 of the memory cell 100 ( 1 , 2 ) would be coupled to the same high voltage control line HVL 1 .

In addition, the adjacent memory cells 100 ( 1 , 3 ) and 100 ( 1 , 2 ) are also disposed in the same column, and the first terminal of the read selection transistor 110 of the memory cell 100 ( 1 , 3 ) can be coupled to the first terminal of the read selection transistor 110 of the memory cell 100 ( 1 , 2 ).

Consequently, in the memory array 10 , two adjacent rows of memory cells can be coupled to the same high voltage control line or can be coupled to the corresponding bit line with the same connection node, reducing the layout area and simplifying the routing. In some embodiments, the designer can also arrange each row of memory cells independently, and set up the required high voltage control lines and the connection nodes for bit lines according to the system requirement.

FIG. 5 shows the signal voltages received by the memory array 10 during the program operation of the memory cell 100 ( 1 , 1 ). During the program operation of the memory cell 100 ( 1 , 1 ), the bit line BL 1 , the read word line RWL 1 , and the program word line PWL 1 are at the first voltage V 1 , the high voltage control line HVL 1 is at the second voltage V 2 , and the low voltage control line LVL 1 is at the third voltage V 3 .

In this case, the read selection transistor 110 of the memory cell 100 ( 1 , 1 ) can be turned off, and the program selection transistor 110 of the memory cell 100 ( 1 , 1 ) can be turned on. Therefore, the first terminal of the anti-fuse capacitor 130 of the memory cell 100 ( 1 , 1 ) would receive the second voltage V 2 through the program selection transistor 120 , while the second terminal of the anti-fuse capacitor 130 of the memory cell 100 ( 1 , 1 ) would receive the third voltage V 3 from the low voltage control line LVL 1 . Consequently, the big voltage gap between the second voltage V 2 and the third voltage V 3 can rupture the anti-fuse capacitor 130 , so the data can be programmed into the memory cell 100 ( 1 , 1 ).

Furthermore, during the program operation of the memory cell 100 ( 1 , 1 ), other memory cells should not be programmed. Therefore, during the program operation of the memory cell 100 ( 1 , 1 ), the read word line RWL 2 would be at the first voltage V 1 , and the low voltage control line LVL 2 would be at the fifth voltage V 5 . The fifth voltage V 5 can be lower than the second voltage V 2 and higher than the first voltage V 1 . For example, the second voltage V 2 can be 4V, and the fifth voltage 5V can be 2.5V. Consequently, although the memory cells 100 ( 1 , 1 ) and 100 ( 1 , 2 ) are coupled to the same high voltage control line HVL 1 and the same program word line PWL 1 , the memory cell 100 ( 1 , 2 ) would receive the fifth voltage V 5 from the low voltage control line LVL 2 . Since the voltage gap between the second voltage V 2 and the fifth voltage V 5 is not big enough to rupture the anti-fuse capacitor 130 of the memory cell 100 ( 1 , 2 ), the memory cell 100 ( 1 , 2 ) will not be programmed.

In addition, for the memory cells not being coupled to the same high voltage control line HVL 1 as the memory cell 100 ( 1 , 1 ), the high voltage control lines can be at a lower voltage, preventing the memory cells from being programmed during the program operation of the memory cell 100 ( 1 , 1 ) and saving the power for outputting high voltages.

For example, during the program operation of the memory cell 100 ( 1 , 1 ), the high voltage control line HVL 2 coupled to the memory cell ( 1 , 3 ) would be at the first voltage V 1 , the read word line RWL 2 coupled to the memory cell 100 ( 1 , 3 ) would be at the first voltage V 1 , and the low voltage control line LVL 2 coupled to the memory cell 100 ( 1 , 3 ) would be at the first voltage V 1 . Therefore, the memory cell 100 ( 1 , 3 ) will not be programmed during the program operation of the memory cell 100 ( 1 , 1 ).

In addition, during the program operation of the memory cell 100 ( 1 , 1 ), the memory cells 100 ( 1 , 2 ) to 100 ( 1 , M) disposed in the same row as the memory cell 100 ( 1 , 1 ) would be coupled to the program word lines PLW 2 to PLWN, and the program word lines PLW 2 to PLWN can be at the fifth voltage V 5 . Therefore, during the program operation of the memory cell 100 ( 1 , 1 ), the program selection transistors 120 of the memory cells 100 ( 1 , 2 ) to 100 ( 1 , M) can be turned off, so the anti-fuse capacitors 130 of the memory cells 100 ( 1 , 2 ) to 100 ( 1 , M) will not receive the high voltage on the high voltage control line HVL 1 , and will not be programmed.

FIG. 6 shows the signal voltages received by the memory array 10 during the read operation of the memory cell 100 ( 1 , 1 ). During the read operation of the memory cell 100 ( 1 , 1 ), the program word line PWL 1 , the bit line BL 1 , the read word line RWL 1 , and the low voltage control line LVL 1 are all at the fourth voltage V 4 , and the high voltage control line HVL 1 is at the first voltage V 1 .

Consequently, the read selection transistor 110 of the memory cell 100 ( 1 , 1 ) can be turned on, and the program selection transistor 120 of the memory cell 100 ( 1 , 1 ) can be turned off. In this case, the second terminal of the anti-fuse capacitor 130 of the memory cell 100 ( 1 , 1 ) would receive the fourth voltage V 4 from the low voltage control line LVL 1 . Since the anti-fuse capacitor 130 has different characteristics before and after being ruptured, the bit line BL 1 would be at different voltages according to the situations. Therefore, by identifying the voltage on the bit line BL 1 , the data stored in the memory cell 100 ( 1 , 1 ) can be identified.

In addition, in FIG. 6 , memory cells 100 ( 2 , 1 ) to 100 (M, 1 ) disposed in the same row as the memory cell 100 ( 1 , 1 ) are coupled to the same read word line RWL 1 and the same low voltage control line LVL 1 . Therefore, in some embodiments, the users can read the data stored in the memory cells 100 ( 1 , 1 ) to 100 (M, 1 ) simultaneously. However, in some other embodiments, the users may adopt buffer elements to read the data stored in the memory cells 100 ( 1 , 1 ) to 100 (M, 1 ) sequentially.

Moreover, during the read operation of the memory cell 100 ( 1 , 1 ), the memory cells disposed in different rows from the memory cell 100 ( 1 , 1 ) should not output voltages. For example, for memory cell 100 ( 1 , 2 ), the read word line RWL 2 and the low voltage control line LVL 2 coupled to the memory cell 100 ( 1 , 2 ) can be at the first voltage V 1 . Therefore, the read selection transistor 110 of the memory cell 100 ( 1 , 2 ) will be turned off, and the anti-fuse capacitor 130 of the memory cell 100 ( 1 , 2 ) will not generate current.

In summary, the memory cells and the memory arrays provided by the embodiments of the present invention can use the read selection transistors and the program selection transistors for program operations and read operations. Also, different memory cells may be coupled together or coupled to the same high voltage control line, supporting flexible operations, efficient layout, and simple routing.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.