Controller and control method for dynamic random access memory

This Application claims priority of China Patent Application No. 201710083491.4, filed on Feb. 16, 2017, the entirety of which is incorporated by reference herein.

The present invention relates to a schedule for refreshing a dynamic random access memory (DRAM).

A dynamic random access memory (DRAM) is a semiconductor memory, storing binary data, 1 or 0, by controlling the electrons contained in the capacitors. To cope with leakage current from the capacitors, a refresh mechanism is required for DRAM to guarantee data reliability.

A refresh schedule for dynamic random access memory (DRAM) is disclosed in the disclosure.

A dynamic random access memory controller in accordance with an exemplary embodiment of the disclosure comprises a command queue and a microcontroller. Access commands waiting to be transmitted to a dynamic random access memory are queued in the command queue. First-rank bank-refresh time points within a refresh inspection interval are provided for the microcontroller to refresh a plurality of banks of a first rank of the dynamic random access memory bank-by-bank based on the status of the command queue. Second-rank bank-refresh time points within the refresh inspection interval are provided for the microcontroller to refresh a plurality of banks of a second rank of the dynamic random access memory bank-by-bank based on the status of the command queue. The first-rank bank-refresh time points and the second-rank bank-refresh time points are arranged alternately. In this manner, the computing resources of the dynamic random access memory controller are not excessively focused on the refresh of the dynamic random access memory.

A dynamic random access memory control method in accordance with an exemplary embodiment of the disclosure comprises the following steps: providing a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory; arranging first-rank bank-refresh time points within a refresh inspection interval for refreshing a plurality of banks of a first rank of the dynamic random access memory bank-by-bank based on the status of the command queue; and arranging second-rank bank-refresh time points within a refresh inspection interval for refreshing a plurality of banks of a second rank of the dynamic random access memory bank-by-bank based on the status of the command queue. The first-rank bank-refresh time points and the second-rank bank-refresh time points are arranged alternately.

According to the disclosed DRAM controller and control method, different ranks of a DRAM are refreshed alternately bank-by-bank. The system resources are not excessively focused on the refresh of the DRAM. The access commands for operating the DRAM, therefore, are executed fluently.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a block diagram depicting a dynamic random access memory (DRAM) 100 and a DRAM controller 102 ;

FIG. 2 is a timing diagram depicting how to schedule a refresh inspection interval tREFI in accordance with an exemplary embodiment of the disclosure;

FIG. 3A and FIG. 3B depict a procedure for scheduling the refresh operations of the rank rank 1 by the microcontroller 106 , which should be performed once every refresh inspection interval tREFI; and

FIG. 4A and FIG. 4B depict a flowchart for scheduling the access commands to the rank rank 1 by the microcontroller 106 .

The following description shows exemplary embodiments carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 is a block diagram depicting a dynamic random access memory (DRAM) 100 and a DRAM controller 102 . The DRAM controller 102 comprises a command queue 104 and a microcontroller 106 . The access commands waiting to be transmitted to the DRAM 100 are queued in the command queue 104 . The microcontroller 106 runs to optimize the refresh of the DRAM to avoid hampering the access commands waiting in the command queue 104 . The microcontroller 106 may include a computing circuit and computing code. The exemplary embodiment shown in FIG. 1 implements the DRAM controller 102 within a chipset 108 . In cases where the chipset 108 and a central processing unit (not shown) are integrated in an SoC (System on a Chip), the DRAM controller 102 is fabricated within the SoC. In cases where the chipset 108 contains separate south and north bridges, the DRAM controller 102 , specifically, is fabricated in the north bridge of the chipset 108 but it is not intended to be limited thereto.

The memory cells of the DRAM 100 may be accessed via two channels. Each channel is provided to access multiple memory modules, e.g., DIMMs (Dual In-line Memory Modules). Each memory module may include multiple memory chips. The memory chips controlled by the same chip select (CS) signal are regarded as one rank. Referring to FIG. 1 , the storage space includes two ranks, rank 1 and rank 2 . The same rank is further divided into a plurality of banks. Each bank is controlled by one set of word lines and bit lines. As shown, the storage space of the rank rank 1 includes eight banks bank 11 to bank 18 , and the storage space of the rank rank 2 includes eight banks bank 21 to bank 28 .

The DRAM 100 may be refreshed per rank or per bank. One rank may be wholly refreshed by one per-rank refresh operation or by a series of per-bank refresh operations. The time required for one per-rank refresh operation is labeled tRFCpr. During the time interval tRFCpr, the whole rank should be protected from being accessed. The time required for one per-bank refresh operation is labeled tRFCpb. During one time interval tRFCpb, only the bank that is being refreshed should be protected from being accessed. The time interval tRFCpr is generally much longer than the time interval tRFCpb. In an exemplary embodiment, the time interval tRFCpr is up to 210 ns and the time interval tRFCpb is up to 90 ns. A refresh inspection interval (labeled tREFI) is introduced to schedule the refresh operations of the DRAM 100 . One rank, ideally, should be wholly refreshed (no matter whether it be by one per-rank refresh operation or by a series of per-bank refresh operations) once during every refresh inspection interval tREFI. In this disclosure, however, the per-rank refresh operation may be repeated several times first and then be ignored in the following refresh inspection intervals. For example, a rank refreshed by repeating the per-rank refresh operation eight times during one refresh inspection interval may not be refreshed in the later eight refresh inspection intervals. In another exemplary embodiment, the per-rank refresh operation may be halted first and then be repeated several times in a later refresh inspection interval. For example, a rank that has not been refreshed for eight continuous refresh inspection intervals may be refreshed by repeating the per-rank refresh operation eight times in the ninth refresh inspection interval. In an exemplary embodiment, the refresh inspection interval tREFI may be 7.8 us or 3.9 us long, much longer than the time intervals tRFCpr and tRFCpb.

FIG. 2 is a timing diagram depicting how to schedule a refresh inspection interval tREFI in accordance with an exemplary embodiment of the disclosure. As shown, during one refresh inspection interval tREFI, there are first-rank bank-refresh time points t 11 to t 18 and second-rank bank-refresh time points t 21 to t 28 which are arranged alternately as t 11 →t 21 →t 12 →t 22 →t 13 →t 23 →t 14 →t 24 →t 15 →t 25 →t 16 →t 26 →t 17 →t 27 →t 18 →t 28 . The first-rank bank-refresh time points t 11 to t 18 correspond to the banks bank 11 to bank 18 of the rank rank 1 . The second-rank bank-refresh time points t 21 to t 28 correspond to the banks bank 21 to bank 28 of the rank rank 2 . Considering the content queued in the command queue 104 , the microcontroller 106 may refresh the banks bank 11 to bank 18 of the rank rank 1 bank-by-bank respectively from the first-rank bank-refresh time points t 11 to t 18 to entirely refresh the rank rank 1 . Considering the content queued in the command queue 104 , the microcontroller 106 may refresh the banks bank 21 to bank 28 of the rank rank 2 bank-by-bank respectively from the second-rank bank-refresh time points t 21 to t 28 to entirely refresh the rank rank 2 . According to the forgoing concept, the different ranks are refreshed alternately bank-by-bank during one refresh inspection interval tREFI. In addition to the aforementioned double rank structure, a memory with four or more ranks can be also refreshed based on a similar concept.

As shown, the first-rank bank-refresh time points t 11 to t 18 for the rank rank 1 may be equally separated (e.g. equally separated by a first time interval) and the second-rank bank-refresh time points t 21 to t 28 for the rank rank 2 may be equally separated (e.g. equally separated by a second time interval). The first-rank bank-refresh time point t 11 may be arranged at the beginning of each refresh inspection interval tREFI as shown. The first-rank bank-refresh time point t 18 within the current refresh inspection interval may be distant from the first-rank bank-refresh time point t 11 in the following refresh inspection interval by the first time interval. The second-rank bank-refresh time point t 28 within the current refresh inspection interval may be distant from the second-rank bank-refresh time point t 21 in the following refresh inspection interval by the second time interval. In the exemplary embodiment depicted in FIG. 2 , the length of the first time interval equals the length of the second time interval. The first-rank bank-refresh time point t 11 is distant from the second-rank bank-refresh time point t 21 by an identical time interval as that separating the second-rank bank-refresh time point t 21 and the first-rank bank-refresh time point t 12 . According to the forgoing concept, one refresh inspection interval tREFI is equally divided to all banks of the different ranks, rank 1 and rank 2 . A similar concept may be used in a memory having four or more ranks.

As for the per-rank refresh operation, it is preferably being repeatedly performed on the rank(s) idling (without access commands waiting in the command queue 104 ) in the current refresh inspection interval tREFI. The rank that has been wholly refreshed repeatedly do not require further refresh operations in the later refresh inspection intervals (e.g. in the following Nx(tREFI) time length) and computing resources therefore are not occupied by the refresh operations of the rank. As shown in FIG. 2 , the first per-rank refresh operation for the rank rank 1 may start from time point T 1 _ 1 and, after the time interval tRFCpr, the second per-rank refresh operation for the rank rank 1 is repeated from time point T 1 _ 2 . In an exemplary embodiment, the starting point for the repeated per-rank refresh operations of the same rank may be aligned to the time point allocated for starting refreshing the rank bank-by-bank. As shown, the first per-rank refresh operation for the rank rank 2 may start from time point T 2 _ 1 and, after the time interval tRFCpr, the second per-rank refresh operation for the rank rank 2 is repeated from time point T 2 _ 2 . The time point T 2 _ 2 is aligned to the second-rank bank-refresh time point t 21 .

For simplicity, only the refresh schedule for the rank rank 1 is discussed in the following paragraphs.

FIG. 3A and FIG. 3B depict a procedure for scheduling the refresh operations of the rank rank 1 by the microcontroller 106 , which should be performed once every refresh inspection interval tREFI. The microcontroller 106 uses a counter (hereinafter Cnt 1 ) to count how many times the rank rank 1 is entirely refreshed (no matter whether it be by one per-rank refresh operation or by a series of per-bank refresh operations). The counter Cnt 1 is decreased by 1 in step S 302 at the beginning of every refresh inspection interval tREFI. It is determined in step S 304 whether any access command for the rank rank 1 is waiting in the command queue 104 . When no access command for the rank rank 1 is waiting in the command queue 104 , step S 306 is performed to check whether the counter Cnt 1 has reached an upper limit (e.g., 8, the number of the banks bank 11 to bank 18 contained in the rank rank 1 ). When the counter Cnt 1 has not reached 8, step S 310 is performed, in which the per-rank refresh operation is performed on the rank rank 1 and the counter Cnt 1 increases by 1. In step S 312 , a timer counts a time interval tRFCpr and thereby the single per-rank refresh operation of step S 310 is guaranteed finished. Steps S 314 and S 316 are performed to check the status of the command queue 104 and the counter Cnt 1 . When it still shows that no access command for the rank rank 1 is waiting in the command queue 104 and the counter Cnt 1 is still less than 8, step S 318 is performed to repeat the per-rank refresh operation on the rank rank 1 and the counter Cnt 1 is again increased by 1. The per-rank refresh operation based on the status of the command queue 104 and the counter Cnt 1 will be repeated until it is determined in step S 316 that the counter Cnt 1 reaches 8. According to step S 320 , the rank rank 1 is no longer refreshed in the rest of the current refresh inspection interval tREFI. Step S 308 is designed based on a similar concept.

When it is determined in step S 304 that there is an access command for the rank rank 1 waiting in the command queue 104 , step S 322 checks whether the counter Cnt 1 is 0 and thereby determines whether there is an urgent need to refresh the rank rank 1 during the current refresh inspection interval tREFI. When the counter Cnt 1 is greater than 0, it is not urgent to refresh the rank rank 1 , and a time interval (e.g. tRFCpr provided in step S 312 or others) for execution of the access command queued in the command queue 104 for the rank rank 1 is counted. In such cases, the access command queued in the command queue 104 for the rank rank 1 is ranked to have the higher priority than the refresh of the rank rank 1 . When step S 314 ensures that no access command for the rank rank 1 is waiting in the command queue 104 , the free computing resources may be also used in repeatedly performing the per-rank operation on the rank rank 1 until step S 316 detects that the counter Cnt 1 reaches 8.

When it is determined in step S 322 that the counter Cnt 1 is 0, there is an urgent need to refresh the rank rank 1 during the current refresh inspection interval tREFI. In step S 324 , the banks bank 11 to bank 18 of the rank rank 1 are refreshed one by one by a series of per-bank refresh operations. After wholly refreshing the rank rank 1 bank-by-bank, the counter Cnt 1 is increased by 1. In this situation, the banks not being refreshed are allowed to be accessed. The access commands queued in the command queue 104 for the rank rank 1 , therefore, are not excessively postponed due to the refresh operations on the rank rank 1 . In an exemplary embodiment, the per-bank refresh operations in step S 324 may be performed to refresh the banks bank 11 to bank 18 of the rank rank 1 bank-by-bank according to the first-rank bank-refresh time points t 11 to t 18 .

The other rank of the DRAM 100 may be refreshed based on the same concept mentioned in FIGS. 3A and 3B . For example, the microcontroller 106 may provide another counter (hereinafter Cnt 2 ) for the rank rank 2 to implement a procedure similar to that described in FIGS. 3A and 3B . The counter Cnt 2 may be decreased by 1 at the second-rank bank-refresh time point t 21 shown in FIG. 2 .

FIG. 4A and FIG. 4B depict a flowchart for scheduling the access commands to the rank rank 1 by the microcontroller 106 , which is provided based on the refresh schedule mentioned in FIGS. 3A and 3B and should be performed corresponding to every refresh inspection interval tREFI. The transmission of the request for the per-rank refresh operation is checked in step S 402 at the beginning of every refresh inspection interval tREFI. When a per-rank refresh operation is performed in the current refresh inspection interval tREFI, step S 404 is performed to count the time interval tRFCpr. In cases where the per-rank refresh operation is performed repeatedly, step S 404 is performed to count a multiple of the time interval tRFCpr. Before satisfying the time limit, step S 406 is performed by the microcontroller 106 to decrease the priority of the access commands queued in the command queue 104 for the rank rank 1 . Thus, for the rank rank 1 that is being refreshed, the corresponding access commands are prohibited from redundantly gaining the computing resources and thereby the whole system is not halted by the refresh of the rank rank 1 . The access commands for the other ranks, therefore, can be executed fluently without being delayed. When step S 404 counts up to the time limit, it means that the per-rank refresh operation has been finished. The microcontroller 106 performs step S 408 and the priority of the access commands queued in the command queue 104 for the rank rank 1 is raised back.

When it is determined in step S 402 that the rank rank 1 is not refreshed by the per-rank refresh operation during the current refresh inspection interval tREFI, step S 410 is performed to monitor the per-bank refresh operations for the banks bank 11 to bank 18 of the rank rank 1 . For the bank bank 1 i that is currently being refreshed, step S 412 is performed to increase the priority of the access commands queued in the command queue 104 for the banks of the rank rank 1 except for the bank bank 1 i . Step S 414 is performed to count a time interval tRFCpb. Before satisfying the time limit, step S 416 is performed by the microcontroller 106 to decrease the priority of the access commands queued in the command queue 104 for the bank bank 1 i . Thus, for the bank bank 1 i that is currently being refreshed, the corresponding access commands are prohibited from redundantly gaining the computing resources and thereby the whole system is not halted by the refresh of the bank bank 1 i . The access commands not accessing the bank bank 1 i can timely gain the priority to use the computing resources and are not postponed by the refresh of the bank bank 1 i . When step S 414 counts the time interval tRFCpb, it means that the per-bank refresh operation on the bank bank 1 i has been finished. The microcontroller 106 performs step S 418 and the priority of the access commands queued in the command queue 104 are restored (no matter whether they be those raised before or those suppressed before). When it is determined in step S 410 the banks bank 1 i to bank 18 have all been refreshed by the corresponding per-bank refresh operations (e.g. after the time point t 18 or finishing the current refresh inspection interval tREFI), the procedure ends.

Control methods for DRAM are also disclosed in the disclosure. Any control method applied on a DRAM based on the forgoing concept should be regarded as being within the scope of the invention. According to the disclosed DRAM controller and DRAM control method, refresh operations for a rank (no matter whether it be rank 1 or rank 2 ) are dynamically scheduled considering whether the rank is idle. Specifically, instead of being refreshed by the per-rank refresh operation every refresh inspection interval tREFI, an idle rank is repeatedly refreshed during an earlier refresh inspection interval by repeating the per-rank refresh operation. The rank that has been repeatedly refreshed during the earlier refresh inspection interval tREFI does not need to be refreshed in the later N refresh inspection intervals (NxtREFI). The access commands to the rank, therefore, can be timely executed without being delayed by a conventional refresh routine. In another aspect, when refreshing a specific bank of a specific rank, priority of the access commands to the different banks of the specific rank is further dynamically adjusted. The access commands corresponding to the banks that are not being refreshed at present are given the higher priority to gain the system resources. Access commands for the specific rank, therefore, are not excessively delayed in the command queue.

There are different DRAM types. LPDDR3 and LPDDR4 support the per-bank refresh operation. DDR3 and DDR4 supporting the per-rank refresh operation, however, do not support the per-bank refresh operation. For DDR3 and DDR4, step S 324 is modified to perform one per-rank refresh operation on the rank rank 1 . Step S 324 is provided to give the refresh of the rank rank 1 higher priority than the access commands to the rank rank 1 . The zero count Cnt 1 means that it is urgent to refresh the rank rank 1 even though access commands corresponding to the rank rank 1 are waiting. The procedure depicted in FIG. 4B for inspection of the per-bank refresh operations is not required for DDR3 and DDR4.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.