Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths

Aspects of the present disclosure relate generally to latch circuits, and in particular, to an apparatus and method for latching data including a AND-NOR gate or OR-NAND gate and a pair of feedback paths.

A latch circuit is configured to receive data during a first half of a clock cycle, and latch the data during a second half of the clock cycle. The maximum frequency of a clock signal driving the latch circuit depends on the propagation delay between an input and output of the latch circuit. Reducing such delay would allow for the latch circuit to be operated at higher frequencies.

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

An aspect of the disclosure relates to an apparatus including a AND-NOR gate configured to generate an output data signal at an output based on an input data signal, wherein the AND-NOR gate includes a first AND-input configured to receive the input data signal; a NAND gate including a first input coupled to the output of the AND-NOR gate, a second input configured to receive a clock signal, and an output coupled to a second AND-input of the AND-NOR gate; and a NOR gate including a first input coupled to the output of the AND-NOR gate, a second input configured to receive a complementary clock signal, and an output coupled to a NOR-input of the AND-NOR gate.

Another aspect of the disclosure relates to a method including logically ANDing an input data signal with a first signal to generate an intermediate data signal; logically NORing the intermediate data signal with a second signal to generate an output data signal; logically NANDing the output data signal with a clock signal to generate the first signal; and logically NORing the output data signal with a complementary clock signal to generate the second signal.

Another aspect of the disclosure relates to an apparatus including a OR-NAND gate configured to generate an output data signal at an output based on an input data signal, wherein the OR-NAND gate includes a first OR-input configured to receive the input data signal; a NAND gate including a first input coupled to the output of the OR-NAND gate, a second input configured to receive a clock signal, and an output coupled to a NAND-input of the OR-NAND gate; and a NOR gate including a first input coupled to the output of the OR-NAND gate, a second input configured to receive a complementary clock signal, and an output coupled to a second OR-input of the OR-NAND gate.

Another aspect of the disclosure relates to a method including logically ORing an input data signal with a first signal to generate an intermediate data signal; logically NANDing the intermediate data signal with a second signal to generate an output data signal; logically NANDing the output data signal with a clock signal to generate the second signal; and logically NORing the output data signal with a complementary clock signal to generate the first signal.

To the accomplishment of the foregoing and related ends, the one or more embodiments include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the description embodiments are intended to include all such aspects and their equivalents.

FIG. 1A illustrates a schematic diagram of an exemplary latch circuit in accordance with an aspect of the disclosure.

FIG. 1B illustrates a timing diagram of a set of exemplary signals related to an operation of the latch circuit of FIG. 1A in accordance with another aspect of the disclosure.

FIG. 2A illustrates a schematic diagram of another exemplary latch circuit in accordance with an aspect of the disclosure.

FIG. 2B illustrates a timing diagram of another set of exemplary signals related to an operation of the latch circuit of FIG. 2A in accordance with another aspect of the disclosure.

FIG. 3A illustrates a schematic diagram of another exemplary latch circuit in accordance with an aspect of the disclosure.

FIG. 3B illustrates a timing diagram of another set of exemplary signals related to an operation of the latch circuit of FIG. 3A in accordance with another aspect of the disclosure.

FIG. 4 illustrates a schematic diagram of an exemplary AND-NOR gate in accordance with another aspect of the disclosure.

FIG. 5 illustrates a schematic diagram of an exemplary OR-NAND gate in accordance with another aspect of the disclosure.

FIG. 6 illustrates a flow diagram of an exemplary method of latching data in accordance with another aspect of the disclosure.

FIG. 7 illustrates a flow diagram of another exemplary method of latching data in accordance with another aspect of the disclosure.

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

FIG. 1A illustrates a schematic diagram of an exemplary latch circuit 100 in accordance with an aspect of the disclosure. The latch circuit 100 includes a first inverter I 1 , a second inverter I 2 , a pass gate (PG), and cross-coupled inverters I 3 and I 4 , all coupled in series between an input configured to receive an input data signal Din, and an output configured to produce an output data signal Dout.

The pass gate PG includes a control input configured to receive a complementary clock signal clk and a complementary control input configured to receive a clock signal. The inverter I 4 includes a complementary control input configured to receive the complementary clock signal clk , and a control input configured to receive the clock signal clk.

FIG. 1B illustrates a timing diagram of a set of exemplary signals related to an operation of the latch circuit 100 in accordance with another aspect of the disclosure. The timing diagram includes four (4) rows for depicting the clock signal clk, complementary clock signal clk , input data signal Din, and output data signal Dout logic state variation over time, respectively.

Prior to time t 4 , the clock signal clk is at a low logic voltage and the complementary clock signal clk is at a high logic voltage. As a result, the pass gate PG is turned on and the fourth inverter I 4 is disabled or tristated. In this configuration, three (3) inverters I 1 , I 2 , and I 3 separate the input from the output of the latch circuit 100 . Accordingly, the output data signal Dout tracks (albeit, inversely) the input data signal Din. For instance, at time t 1 , when the input data signal Din is at a low logic voltage, the output data signal Dout is at a high logic voltage. At time t 2 , when the input data signal Din transitions from a low to a high logic voltage, the output data signal Dout responsively transitions from a high to a low logic voltage at time t 3 (e.g., after three (3) gate delays from time t 2 due to the inverters I 1 , I 2 , and I 3 ).

At times t 4 and t 5 , the clock signal clk transitions from a low to a high logic voltage and the complementary clock signal clk responsively transitions from a high to a low logic voltage, respectively. As a result, the pass gate PG is turned off and the fourth inverter I 4 is enabled. The pass gate PG, being turned off, prevents signal and/or noise at the input from affecting the latching of the output data signal Dout by the cross-coupled inverters I 3 and I 4 . The fourth inverter I 4 , being turned on, causes the cross-coupled inverters I 3 and I 4 to latch the output data signal Dout. As long as the clock signal clk is high and the complementary clock signal clk is low, as indicated between times t 5 and t 7 , the output data signal Dout is kept latched by the cross-coupled inverters I 3 and I 4 , even though the input data signal Din changes states as indicated at time t 6 .

At times t 7 and t 8 , the clock signal clk transitions from a high to a low logic voltage and the complementary clock signal clk responsively transitions from a low to a high logic voltage, respectively. As a result, the pass gate PG turns on and the fourth inverter I 4 becomes disabled or tristated. In this configuration, the latch circuit 100 is configured to receive new input data. Accordingly, at time t 8 , the input data signal Din is at a low logic voltage. In response to the clock signal changing states, the output data signal Dout transitions from a low to a high logic voltage at time t 9 .

At time t 10 , the input data signal Din transitions from a low to a high logic voltage. At time t 11 , after a three (3) gate delay caused by inverters I 1 , I 2 , and I 3 , the output data signal Dout transitions from a high to a low logic voltage. Between times t 12 and t 13 , when the clock signal clk is high and the complementary clock signal clk is low, the output data signal Dout, at a low logic voltage, is latched by the cross-coupled inverters I 3 and I 4 .

An issue with the latch circuit 100 is that the delay between the input and output is three (3) gate delays, i.e., the delays of the first inverter I 1 , second inverter I 2 , and third inverter I 3 . Because of such delay, the frequency of the clock signal clk needs to be set in order to accommodate that delay. For instance, there should be sufficient margin between time t 3 (when the input data signal Din has propagated to the output) and time t 4 (when the clock signal clk transitions from a low to a high logic voltage) to reliably latch the data without setup and/or hold timing violations. Thus, such delay impacts the performance of the latch circuit 100 .

FIG. 2A illustrates a schematic diagram of another exemplary latch circuit 200 in accordance with another aspect of the disclosure. The latch circuit 200 includes an AND-NOR gate 210 , a NOR gate 220 , a NAND gate 230 , and an inverter 240 . Although, symbolically, the AND-NOR gate 210 is shown to include two gates, the AND-NOR gate operates as a single gate, as discussed further herein with reference to an exemplary detailed embodiment.

The AND-NOR gate 210 includes a first AND-input configured to receive an input data signal Din. The AND-NOR gate 210 includes a second AND-input coupled to an output of NAND gate 230 . The AND-NOR gate 210 includes a NOR-input coupled to an output of the NOR gate 220 . Operationally, the output of the AND portion of the AND-NOR gate 210 is internally coupled to another an input of the NOR portion of the AND-NOR gate 210 . The output of the AND-NOR gate 210 , which produces an output data signal Dout, is coupled to respective first inputs of the NOR gate 220 and the NAND gate 230 .

The NAND gate 230 includes a second input configured to receive a clock signal clk. The NOR gate 220 includes a second input configured to receive a complementary clock signal clk generated by the inverter 240 in response to the clock signal clk.

FIG. 2B illustrates a timing diagram of a set of exemplary signals related to an operation of the latch circuit 200 in accordance with another aspect of the disclosure.

Prior to time t 4 , when the clock signal clk is at a low logic voltage and the complementary clock signal clk is at a high logic voltage, the output data signal Dout tracks (albeit, inversely) the input data signal Din. The clock signal clk being low causes the NAND gate 230 to generate a signal “A” at a high logic voltage to enable the AND portion of the AND-NOR gate 210 . The complementary clock signal clk , being at a high logic voltage, causes the NOR gate 220 to generate a signal “B” at a low logic voltage to enable the NOR portion of the AND-NOR gate 210 . Thus, the AND-NOR gate 210 passes the input data signal Din (albeit, inversely) to generate the output data signal Dout.

This can be seen in the timing diagram where at time t 1 , the input data signal Din is at a low logic voltage and the output data signal Dout is at a high logic voltage. Similarly, at time t 2 , when the input data signal Din transitions from a low to a high logic voltage, the output data signal Dout responsively transitions from a high to a low logic voltage at time t 3 (after a one (1) gate delay from time t 2 ). This is because there is a single gate (e.g., the OR-NAND gate 210 ) between the input and output of the latch circuit 200 . Compared to latch circuit 100 , the latch circuit 200 is able to latch data much faster with a one (1) gate propagation delay as compared to the latch circuit 100 with a three (3) gate propagation delay.

At times t 4 and t 5 , the clock signal clk transitions from a low to a high logic voltage and the complementary clock signal clk responsively transitions from a high to a low logic voltage, respectively. The complementary clock signal clk being low enables the NOR gate 220 to invert the output data signal Dout to generate signal “B” at a high logic voltage at time t 6 . Thus, in this configuration, the AND-NOR gate 210 and the NOR gate 220 operate as two cross-coupled inverters to latch the output data signal Dout. This can be seen in the timing diagram where between times t 6 and t 8 , the output data signal Dout is latched at a low logic voltage even though the input data signal Din transitions from high to low at time t 7 .

At times t 8 -t 9 , the clock signal clk transitions from a high to a low logic voltage, and the complementary clock signal clk responsively transitions from a low to a high logic voltage, respectively. The complementary clock signal clk , being at a high logic voltage, causes the NOR gate 220 to generate signal “B” at a low logic voltage at time t 10 . The clock signal clk, being at a low logic voltage, causes the NAND gate 230 to continue generating signal “A” at a high logic voltage. The signal “A” being high and the signal “B” being low enable the AND-NOR 210 gate to pass and invert the input data signal Din to generate the output data signal Dout. Since, at time t 10 , the input data signal is at a low logic voltage, the output data signal Dout transitions from a low a high logic voltage at time t 11 (one (1) gate delay from time t 10 ).

Similarly, at times t 12 and t 13 , the clock signal clk transitions from a low to a high logic voltage, and the complementary clock signal clk responsively transitions from a high to a low logic voltage, respectively. The clock signal clk and the output data signal Dout both being high causes the NAND gate 230 to generate signal “A” at a low logic voltage. The complementary clock signal clk being low enables the NOR gate 220 to invert the output data signal Dout to continue generating signal B at a low logic voltage at time t 13 . The signal “A” being low causes the AND portion to output a low intermediate signal. Thus, both inputs to the NOR portion is low, causing the AND-NOR gate 210 to generate the output data signal Dout at a high logic voltage.

In this configuration, the AND-NOR gate 210 and the NOR gate 220 operate as two cross-coupled inverters to latch the output data signal Dout. This can be seen in the timing diagram where between times t 13 and t 15 , the output data signal Dout is latched at a high logic voltage even though the input data signal Din transitions from low to a high logic voltage at time t 14 .

FIG. 3A illustrates a schematic diagram of another exemplary latch circuit 300 in accordance with another aspect of the disclosure. The latch circuit 300 is a variation of latch 200 .

In particular, the latch circuit 300 includes an OR-NAND gate 310 , a NAND gate 320 , a NOR gate 330 , and an inverter 340 . Although, symbolically, the OR-NAND gate 310 is shown to include two gates, the OR-NAND gate 310 operates as a single gate, as discussed further herein with reference to an exemplary detailed embodiment.

The OR-NAND gate 310 includes a first OR-input configured to receive an input data signal Din. The OR-NAND gate 310 further includes a second OR-input coupled to an output of NOR gate 330 . The OR-NAND gate 310 also includes a NAND-input coupled to an output of the NAND gate 320 . The output of the OR-NAND gate 310 , which produces an output data signal Dout, is coupled to respective first inputs of the NAND gate 320 and the NOR gate 330 .

The NAND gate 320 includes a second input configured to receive a clock signal clk. The NOR gate 330 includes a second input configured to receive a complementary clock signal clk generated by the inverter 340 in response to the clock signal clk.

FIG. 3B illustrates a timing diagram of a set of exemplary signals related to an operation of the latch circuit 300 in accordance with another aspect of the disclosure.

Prior to time t 4 , when the clock signal clk is at a low logic voltage and the complementary clock signal clk is at a high logic voltage, the output data signal Dout tracks (albeit inversely) the input data signal Din. The complementary clock signal clk being high causes the NOR gate 330 to generate a signal “A” at a low logic voltage to enable the OR portion of the OR-NAND gate 310 . The clock signal clk, being at a low logic voltage, causes the NAND gate 320 to generate a signal “B” at a high logic voltage to enable the NAND portion of the OR-NAND gate 310 . Thus, the OR-NAND gate 310 passes the input data signal Din (albeit, inversely) to generate the output data signal Dout.

This can be seen in the timing diagram where at time t 1 , the input data signal Din is at a low logic voltage and the output data signal Dout is at a high logic voltage. Similarly, at time t 2 , when the input data signal Din transitions from a low to a high logic voltage, the output data signal Dout responsively transitions from a high to a low logic voltage at time t 3 (after a one (1) gate delay from time t 2 ). This is because there is a single gate (e.g., the OR-NAND gate 310 ) between the input and output in the latch circuit 300 . Compared to latch circuit 100 , the latch circuit 300 is able to latch data much faster with a one (1) gate propagation delay as compared to the latch circuit 100 with a three (3) gate propagation delay.

At times t 4 and t 5 , the clock signal clk transitions from a low to a high logic voltage and the complementary clock signal clk responsively transitions from a high to a low logic voltage, respectively. The clock signal clk being high enables the NAND gate 320 to invert the low output data signal Dout to continue generating signal “B” at a high logic voltage at time t 6 . The complementary clock signal clk being low enables the NOR gate 330 to generate signal “A” at a high logic voltage at time t 6 . The signal “A” being high causes the OR portion to output a high intermediate signal. Thus, both inputs to the NAND portion are high, causing the OR-NAND gate 310 to generate the output data signal Dout at a low logic voltage.

Thus, in this configuration, the OR-NAND gate 310 and the NAND gate 320 operate as two cross-coupled inverters to latch the output data signal Dout. This can be seen in the timing diagram where between times t 6 and t 8 , the output data signal Dout is latched at a low logic voltage even though the input data signal Din transitions from high to low at time t 7 .

At times t 8 -t 9 , the clock signal clk transitions from a high to a low logic voltage, and the complementary clock signal clk responsively transitions from a low to a high logic voltage, respectively. The clock signal clk, being at a low logic voltage, causes the NAND gate 320 to continue to generate signal “B” at a high logic voltage. The complementary clock signal clk , being at a high logic voltage, causes the NOR gate 330 to generate signal “A” at a low logic voltage at time t 10 . The signal “A” being low and the signal “B” being high enable the OR-NAND gate 310 to pass the input data signal Din (albeit, inversely) to generate the output data signal Dout. Since, at time t 10 , the input data signal Din is at a low logic voltage, the output data signal Dout transitions from a low a high logic voltage at time t 11 (one (1) gate delay from time t 10 ).

Similarly, at times t 12 and t 13 , the clock signal clk transitions from a low to a high logic voltage, and the complementary clock signal clk responsively transitions from a high to a low logic voltage, respectively. The clock signal clk being high enables the NAND gate 320 to invert the output data signal Dout to generating signal “B” at a low logic voltage at time t 13 . In this configuration, the OR-NAND gate 310 and the NAND gate 320 operate as two cross-coupled inverters to latch the output data signal Dout. This can be seen in the timing diagram where between times t 14 and t 16 , the output data signal Dout is latched at a high logic voltage even though the input data signal Din transitions from low to a high logic voltage at time t 15 .

FIG. 4 illustrates a schematic diagram of an exemplary AND-NOR gate 400 in accordance with another aspect of the disclosure. The AND-NOR gate 400 may be an exemplary detailed implementation of the AND-NOR gate 210 previously discussed. Also depicted in FIG. 4 is a truth table for the AND-NOR gate 400 .

In particular, the AND-NOR gate 400 includes a p-channel metal oxide semiconductor (PMOS) field effect transistor (FETs) M 41 , M 42 , and M 43 , and n-channel metal oxide semiconductor (NMOS) FETs M 44 , M 45 , and M 46 . The PMOS FET M 41 includes a source coupled to an upper voltage rail (Vdd), a gate configured to receive signal “B”, and a drain coupled to the sources of PMOS FETs M 42 and M 43 . The PMOS FETs M 42 and M 43 include gates configured to receive an input data signal Din and signal “A”, respectively. The drains of the PMOS FETs M 42 and M 43 are coupled together to form an output of the AND-NOR gate 400 , whereat an output data signal Dout is produced.

The NMOS FETs M 44 and M 46 include drains coupled to the output of the AND-NOR gate 400 . The NMOS FET M 44 includes a gate configured to receive the input data signal Din. The NMOS FET M 46 includes a gate configured to receive signal “B”. The NMOS FET M 44 includes a source coupled to a drain of NMOS FET M 45 . The NMOS FET M 46 includes a source coupled to a lower voltage rail (Vss). The NMOS FET M 45 includes a gate configured to receive the “A” signal, and a source coupled to the lower voltage rail (Vss).

In operation, with reference to the truth table, when signal “B” is at a high logic voltage (H) (e.g., substantially Vdd) (as indicated in rows 2, 4, 6, and 8 of the truth table), the PMOS FET M 41 if turned off and the NMOS FET M 46 is turned on. The turned-off PMOS FET M 41 isolates the output from the upper voltage rail (Vdd) and the turned-on NMOS FET M 46 couples the output to the lower voltage rail (Vss). As a result, the output data signal Dout is at a low logic voltage regardless of the states of the input data signal Din and the “A” signal. With reference to FIG. 2B , this condition (B is high) occurs when the latch circuit 200 has latched a logic low output data signal Dout, as indicated between times t 6 and t 8 .

When signal “B” is at a low logic voltage (L) (e.g., substantially Vss) (as indicated in rows 1, 3, 5, and 7 of the truth table), the PMOS FET M 41 if turned on and the NMOS FET M 46 is turned off. Under this condition, the state of the output data signal Dout is determined by the states of the input data signal Din and signal “A”.

For instance, if the input data signal Din and signal “A” are both at low logic voltages (L) (as indicated in row 1 of the truth table), PMOS FETs M 42 and M 43 are turned on and NMOS FETs M 44 and M 45 are turned off. As a result, the output is coupled to the upper voltage rail (Vdd) via the turned-on PMOS FETs M 41 , M 42 , and M 43 , and isolated from the lower voltage rail (Vss) via the turned-off NMOS FETs M 44 , M 45 , and M 46 . As a result, the output data signal Dout is at a high logic voltage. With reference to FIG. 2B , this condition (Din, A, and B are low) occurs during an interval when the latch circuit 200 has latched a logic high output data signal Dout, as indicated between time t 13 and time t 14 .

Considering again the case when signal “B” is low, if the input data signal Din is at a low logic voltage (L) and signal “A” is at a high logic voltage (H) (as indicated in row 3 of the truth table), PMOS FETs M 42 and NMOS FET M 45 are turned on and PMOS FET M 43 and NMOS FET M 44 are turned off. As a result, the output is coupled to the upper voltage rail (Vdd) via the turned-on PMOS FETs M 41 and M 42 , and isolated from the lower voltage rail (Vss) via the turned-off NMOS FETs M 44 and M 46 . As a result, the output data signal Dout is at a high logic voltage. With reference to FIG. 2B , this condition (Din and B are low, and A is high) occurs during an interval when the latch circuit 200 is in an unlatched state and the input data signal Din is at a low logic voltage, as indicated between times t 11 and t 12 .

Considering again the case when signal “B” is low, if the input data signal Din is at a high logic voltage (H) and signal “A” is at a low logic voltage (L) (as indicated in row 5 of the truth table), PMOS FETs M 43 and NMOS FET M 44 are turned on and PMOS FET M 42 and NMOS FET M 45 are turned off. As a result, the output is coupled to the upper voltage rail (Vdd) via the turned-on PMOS FETs M 41 and M 43 , and isolated from the lower voltage rail (Vss) via the turned-off NMOS FETs M 45 and M 46 . As a result, the output data signal Dout is at a high logic voltage. With reference to FIG. 2B , this condition (A and B are low, and Din is high) occurs during an interval when the latch circuit 200 has latched a logic high output data signal Dout, as indicated between times t 14 and t 15 .

Considering again the case when signal “B” is low, if the input data signal Din and signal “A” are both at high logic voltages (H) (as indicated in row 7 of the truth table), PMOS FETs M 43 and M 44 are turned off and NMOS FETs M 44 and M 45 are turned on. As a result, the output is isolated from the upper voltage rail (Vdd) via the turned-off PMOS FETs M 42 and M 43 , and coupled to the lower voltage rail (Vss) via the turned-on NMOS FETs M 44 and M 45 . As a result, the output data signal Dout is at a low logic voltage. With reference to FIG. 2B , this condition (Din and A are high, and B is low) occurs during an interval when the latch circuit 200 is in an unlatched state and the input data signal Din is at a high logic voltage, as indicated between times t 3 and t 4 .

FIG. 5 illustrates a schematic diagram of an exemplary OR-NAND gate 500 in accordance with another aspect of the disclosure. The OR-NAND gate 500 may be an exemplary detailed implementation of the OR-NAND gate 310 previously discussed. Also depicted in FIG. 5 is a truth table for the OR-NAND gate 500 .

In particular, the OR-NAND gate 500 includes PMOS FETs M 51 , M 52 , and M 53 , and NMOS FETs M 54 , M 55 , and M 56 . The PMOS FET M 51 includes a source coupled to an upper voltage rail (Vdd), a gate configured to receive signal “A”, and a drain coupled to the source of PMOS FET M 52 . The PMOS FETs M 52 includes a gate configured to receive the input data signal Din and a drain coupled to an output of the OR-NAND gate 500 , whereat the output data signal Dout is produced. The PMOS FET M 53 includes a source coupled to the upper voltage rail (Vdd), a gate configured to receive signal “B”, and a drain coupled to the output of the OR-NAND gate 500 .

The NMOS FETs M 54 and M 55 include drains coupled to the output of the OR-NAND gate 500 . The NMOS FET M 54 includes a gate configured to receive the input data signal Din. The NMOS FET M 55 includes a gate configured to receive signal “A”. The NMOS FETs M 54 and M 55 include sources coupled to a drain of NMOS FET M 56 . The NMOS FET M 56 includes a gate configured to receive signal “B”, and a source coupled to the lower voltage rail (Vss).

In operation, with reference to the truth table, when signal “B” is at a low logic voltage (L) (e.g., substantially Vss) (as indicated in rows 1, 3, 5, and 7 of the truth table), the PMOS FET M 53 if turned on and the NMOS FET M 56 is turned off. The turned-on PMOS FET M 53 couples the output to the upper voltage rail (Vdd) and the turned-off NMOS FET M 56 isolates the output from the lower voltage rail (Vss). As a result, the output data signal Dout is at a high logic voltage regardless of the states of the input data signal Din and signal “A”. With reference to FIG. 3B , this condition (B is low) occurs when the latch circuit 300 has latched a logic high output data signal Dout, as indicated between times t 14 and t 16 .

When signal “B” is at a high logic voltage (H) (e.g., substantially Vdd) (as indicated in rows 2, 4, 6, and 8 of the truth table), the PMOS FET M 53 if turned off and the NMOS FET M 56 is turned on. Under this condition, the state of the output data signal Dout is determined by the states of the input data signal Din and the “A” signal.

For instance, if the input data signal Din and signal “A” are both at low logic voltages (L) (as indicated in row 2 of the truth table), PMOS FETs MM and M 52 are turned on and NMOS FETs M 54 and M 55 are turned off. As a result, the output is coupled to the upper voltage rail (Vdd) via the turned-on PMOS FETs M 51 and M 52 , and isolated from the lower voltage rail (Vss) via the turned-off NMOS FETs M 54 and M 55 . As a result, the output data signal Dout is at a high logic voltage. With reference to FIG. 3B , this condition (Din and A are low, and B is high) occurs during an interval when the latch circuit 300 is in an unlatched state and the input data signal Din is at a low logic state, as indicated between times t 11 and time t 12 .

Considering again the case when signal “B” is high, if the input data signal Din is at a low logic voltage (L) and signal “A” is at a high logic voltage (H) (as indicated in row 4 of the truth table), PMOS FETs M 51 is turned off and NMOS FET M 55 is turned on. As a result, the output is isolated from the upper voltage rail (Vdd) via the turned-off PMOS FETs M 51 , and coupled to the lower voltage rail (Vss) via the turned-on NMOS FETs M 55 and M 56 . As a result, the output data signal Dout is at a low logic voltage. With reference to FIG. 3B , this condition (Din is low, and A and B are high) occurs during an interval when the latch circuit 300 has latched a logic low output data signal Dout, as indicated between times t 7 and t 8 .

Considering again the case when signal “B” is high, if the input data signal Din is at a high logic voltage (H) and signal “A” is at a low logic voltage (L) (as indicated in row 6 of the truth table), PMOS FETs M 52 is turned off and NMOS FET M 54 is turned on. As a result, the output is isolated from the upper voltage rail (Vdd) via the turned-off PMOS FETs M 52 , and coupled to the lower voltage rail (Vss) via the turned-on NMOS FETs M 54 and M 56 . As a result, the output data signal Dout is at a low logic voltage. With reference to FIG. 3B , this condition (A is low, and Din and B are high) occurs during an interval when the latch circuit 300 is in an unlatched state and the input data signal Din is at a low logic voltage, as indicated between times t 3 and t 4 .

Considering again the case when signal “B” is high, if the input data signal Din and signal “A” are both at high logic voltages (H) (as indicated in row 8 of the truth table), PMOS FETs MM and M 52 are turned off and NMOS FETs M 54 and M 55 are turned on. As a result, the output is isolated from the upper voltage rail (Vdd) via the turned-off PMOS FETs MM and M 52 , and coupled to the lower voltage rail (Vss) via the turned-on NMOS FETs M 54 and M 55 . As a result, the output data signal Dout is at a low logic voltage. With reference to FIG. 3B , this condition (Din, A, and B are high) occurs during an interval when the latch circuit 300 has latched a logic low output data signal Dout, as indicated between times t 6 and t 7 .

FIG. 6 illustrates a flow diagram of an exemplary method 600 of latching data in accordance with another aspect of the disclosure.

The method 600 includes logically ANDing an input data signal with a first signal to generate an intermediate data signal (block 610 ). An example of a means for logically ANDing an input data signal with a first signal to generate an intermediate data signal includes the AND-NOR gate 210 previously described.

The method 600 further includes logically NORing the intermediate data signal with a second signal to generate an output data signal (block 620 ). An example of a means for logically NORing the intermediate data signal with a second signal to generate an output data signal includes the AND-NOR gate 210 .

The method 600 also includes logically NANDing the output data signal with a clock signal to generate the first signal (block 630 ). An example of a means for logically NANDing the output data signal with a clock signal to generate the first signal includes the NAND gate 230 previously described.

Additionally, the method 600 includes logically NORing the output data signal with a complementary clock signal to generate the second signal (block 640 ). An example of a means for logically NORing the output data signal with a complementary clock signal to generate the second signal includes the NOR gate 220 previously described.

FIG. 7 illustrates a flow diagram of an exemplary method 700 of latching data in accordance with another aspect of the disclosure.

The method 700 includes logically ORing an input data signal with a first signal to generate an intermediate data signal (block 710 ). An example of a means for logically ORing an input data signal with a first signal to generate an intermediate data signal includes the OR-NAND gate 310 previously described.

The method 700 further includes logically NANDing the intermediate data signal with a second signal to generate an output data signal (block 720 ). An example of a means for logically NANDing the intermediate data signal with a second signal to generate an output data signal includes the OR-NAND gate 310 .

The method 700 also includes logically NANDing the output data signal with a clock signal to generate the second signal (block 730 ). An example of a means for logically NANDing the output data signal with a clock signal to generate the second signal includes the NAND gate 320 previously described.

Additionally, the method 700 includes logically NORing the output data signal with a complementary clock signal to generate the first signal (block 740 ). An example of a means for logically NORing the output data signal with a complementary clock signal to generate the first signal includes the NOR gate 330 previously described.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.