Reading method for preventing read disturbance and memory using the same

The disclosure relates in general to a reading method and a memory using the same, and more particularly to a reading method for preventing a read disturbance and a memory using the same.

Along with the development of storage technology, various memories are invented. Digital data can be written/programmed into the memory and then those digital data can be read out.

The reading method of the memory may cause nearby cells in the same memory block to change over time. This is known as read disturb (or read disturbance). To avoid the read disturbance problem, the controller may typically count the total number of reads to a block since the last erase. When the total number of reads exceeds a target limit, the data stored in the affected block will be copied to a new block, and then the affected block is erased. The affected block is as good as new after the erasing. However, it costs time to copy the data of the affect block and some of the data may be lost before the total number of reads exceeds the target limit.

The disclosure is directed to a reading method and a memory using the same. When reading a selected cell, only one of a plurality of ground select lines is selected to be applied a predetermined ground select voltage. The voltage difference between the gate and the channel in each unselected cell can be reduced. As such, the read disturbance can be prevented.

According to one embodiment, a reading method of a memory for preventing a read disturbance is provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.

According to another embodiment, a memory is provided. The memory includes a plurality of string select lines and a plurality of ground select lines. At least one of the string select lines is selected by a decoder, and a predetermined string select voltage is applied to the selected string select line. Only one of the ground select lines is selected by the decoder, and a predetermined ground select voltage is applied to the selected ground select line.

FIG. 1 shows a memory according to an embodiment.

FIG. 2 shows a waveform during a forward read operation of the memory.

FIG. 3 shows the channel potential in the memory.

FIG. 4 shows a waveform during an all bit lines sensing operation of the memory.

FIG. 5 shows a memory according to another embodiment.

FIG. 6 shows several strings of the memory.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

Please refer to FIG. 1 , which shows a memory 100 according to an embodiment. The memory 100 may be a 3D VNAND Flash memory. The memory 100 includes a plurality of strings. Each string includes a plurality of memory cells. The memory 100 includes a plurality of even bit lines BL 1 _even, a plurality of odd bit lines BL 1 _odd, a plurality of word lines WL 1 _ n , WL 1 _ n +1, . . . , a plurality of string select lines SSL 1 _ n , SSL 1 _ n +1, SSL 1 _ n +2, . . . , a plurality of ground select lines GSL 1 _ n , GSL 1 _ n +1, GSL 1 _ n +2, . . . , and a common source line CSL 1 . One end of each string is connected to the common source line CSL 1 , and the other end of each string is connected to the even bit lines BL 1 _even or the odd bit lines BL 1 _odd.

The string select lines SSL 1 _ n , SSL 1 _ n +1, SSL 1 _ n +2, . . . are used to turn on or turn off SSL devices SD 1 _ n , SD 1 _ n +1, SD 1 _ n +2, . . . respectively. The SSL devices SD 1 _ n are controlled by the string select line SSL 1 _ n , the SSL devices SD 1 _ n +1 are controlled by the string select line SSL 1 _ n +1, the SSL devices SD 1 _ n +2 are controlled by the string select line SSL 1 _ n +2, and so on. For example, if the SSL devices SD 1 _ n are turned on, the voltage provided from the even bit lines BL 1 _even (or the odd bit lines BL 1 _odd) can be applied into the strings connected the SSL devices SD 1 _ n.

The ground select lines GSL 1 _ n , GSL 1 _ n +1, GSL 1 _ n +2, . . . are used to turn on or turn off GSL devices GD 1 _ n , GD 1 _ n +1, GD 1 _ n +2, . . . respectively. The GSL devices GD 1 _ n , GD 1 _ n +1, GD 1 _ n +2, . . . are not controlled by the same ground select line. Instead, the GSL devices GD 1 _ n are controlled by the ground select line GSL 1 _ n , the GSL devices GD 1 _ n +1 are controlled by the ground select line GSL 1 _ n +1, the GSL devices GD 1 _ n +2 are controlled by the ground select line GSL 1 _ n +2, and so on. For example, if the GSL devices GD 1 _ n are turned on, the voltage provided from the common source line CSL 1 can be applied into the strings connected the GSL devices GD 1 _ n.

The word lines WL 1 _ n , WL 1 _ n +1, . . . are respectively connected to the memory cells in each string.

In this embodiment, the string select lines SSL 1 _ n , SSL 1 _ n +1, SSL 1 _ n +2, . . . respectively correspond to the ground select lines GSL 1 _ n , GSL 1 _ n +1, GSL 1 _ n +2, . . . . One of the string select lines SSL 1 _ n , SSL 1 _ n +1, SSL 1 _ n +2, . . . and one of the ground select lines GSL 1 _ n , GSL 1 _ n +1, GSL 1 _ n +2, . . . can be selected by a decoder 110 . In one embodiment, the ground select lines GSL 1 _ n , GSL 1 _ n +1, GSL 1 _ n +2, . . . can be decoded separately. For example, switch SW 1 can be turned off and switch SW 2 can be turned on to apply a predetermined string select voltage Vssl to the string select line SSL 1 _ n ; and switch SW 3 can be turned on and switch SW 4 can be turned off to apply 0 voltage to the string select line SSL 1 _ n +1. Switch SW 5 can be turned off and switch SW 6 can be tumed on to apply the predetermined ground select voltage Vgsl to the ground select line GSL 1 _ n , and switch SW 7 can be turned on and switch SW 8 can be turned off to apply 0 voltage to the ground select line GSL 1 _ n +1.

Please refer to FIG. 2 , which shows a waveform during a forward read operation of the memory 100 . The read operation includes a pre-on setup stage ST 1 and a sense developing stage ST 2 . In the sense developing stage ST 2 , the reading method of the memory 100 includes the following steps. Those steps may be substantially performed at the same time.

One of the word lines WL 1 _ n , WL 1 _ n +1, . . . is selected. The selected word line is applied a varied read voltage Vread, and the unselected word line is applied a pass voltage Vpass.

One of the string select lines SSL 1 _ n , SSL 1 _ n +1, SSL 1 _ n +2, . . . is selected. The selected string select line is applied the predetermined string select voltage Vssl; the unselected string select line is applied 0 voltage.

One of the ground select lines GSL 1 _ n , GSL 1 _ n +1, GSL 1 _ n +2, . . . is selected. The selected ground select line is applied the predetermined ground select voltage Vgsl; the unselected ground select line is applied 0 voltage.

The common source line CSL 1 is applied 0 voltage. The even bit lines BL 1 _even or the odd bit lines BL 1 _odd are selected. The selected bit lines are applied a predetermined bit line voltage Vbl; the unselected bit lines are applied 0 voltage.

In this embodiment, not all of the ground select lines GSL 1 _ n , GSL 1 _ n +1, GSL 1 _ n +2, . . . are applied the predetermined ground select voltage Vgsl. Therefore, not all of the GSL devices GD 1 _ n , GD 1 _ n +1, GD 1 _ n +2 are tumed on and not all of the strings are applied 0 voltage provided from the common source line CSL 1 .

Please refer to FIG. 3 , which shows the channel potential in the memory 100 . In FIG. 3 , the strings S 11 , S 12 are selected to be read, and the strings S 13 , S 14 , S 15 , S 16 , . . . are unselected. The unselected strings S 13 , S 14 , S 15 , S 16 are floating. A channel potential of each of the strings S 13 , S 14 , S 15 , S 16 , . . . is boosted to be a predetermined voltage level Vch. Therefore, the voltage difference between the gate and the channel in each unselected cell in the strings S 13 , S 14 , S 15 , S 16 can be reduced from “the difference between the pass voltage Vpass and 0 V” to “the difference between the pass voltage Vpass and the predetermined voltage level Vch.” Because the voltage difference in the unselected cell is reduced, the read disturbance can be prevented.

Please refer to FIG. 4 , which shows a waveform during an all bit lines sensing operation of the memory 100 . In another embodiment, all of the even bit lines BL 1 _even and the odd bit lines BL 1 _odd can be selected to apply the predetermined bit line voltage Vbl. In this embodiment, the channel potential is similar to FIG. 3 . The voltage difference between the gate and the channel in each unselected cell in the strings S 13 , S 14 , S 15 , S 16 can also be reduced from “the difference between the pass voltage Vpass and 0 V” to “the difference between the pass voltage Vpass and the predetermined voltage level Vch.” Because the voltage difference in the unselected cell is reduced, the read disturbance can be prevented.

Please refer to FIG. 5 , which shows a memory 200 according to another embodiment. The memory 200 may be a 3D SGVC memory. The memory 200 includes a plurality of strings. Each string includes a plurality of memory cells. The memory 200 includes a plurality of even bit lines BL 2 _even, a plurality of odd bit lines BL 2 _odd, a plurality of word lines, a plurality of string select lines SSL 2 _ n , SSL 2 _ n +1, SSL 2 _ n +2, SSL 2 _ n +3, a plurality of ground select lines GSL 2 _ n , GSL 2 _ n +1, GSL 2 _ n +2, GSL 2 _ n +3, and a common source line CSL 2 .

Please refer to FIG. 6 , which shows several strings S 21 to S 28 of the memory 200 . One end of each of the strings S 21 to S 28 is connected to the common source line CSL 2 , and the other end of each of the strings S 21 to S 28 is connected to the even bit lines BL 2 _even or the odd bit lines BL 2 _odd.

The string select lines SSL 2 _ n , SSL 2 _ n +1, SSL 2 _ n +2, SSL 2 _ n +3 are used to turn on or turn off SSL devices SD 2 _ n , SD 2 _ n +1, SD 2 _ n +2, SD 2 _ n +3 respectively. The SSL devices SD 2 _ n are controlled by the string select line SSL 2 _ n , the SSL devices SD 2 _ n +1 are controlled by the string select line SSL 2 _ n +1, the SSL devices SD 2 _ n +2 are controlled by the string select line SSL 2 _ n +2, and the SSL devices SD 2 _ n +3 are controlled by the string select line SSL 2 _ n +3. For example, if the SSL devices SD 2 _ n are tumed on, the voltage provided from the odd bit lines BL 2 _odd (or the even bit lines BL 1 _even) can be applied into the string S 21 (or the string S 25 ) connected the SSL devices SD 2 _ n.

The ground select lines GSL 2 _ n , GSL 2 _ n +1, GSL 2 _ n +2, GSL 2 _ n +3 are used to turn on or turn off GSL devices GD 2 _ n , GD 2 _ n +1, GD 2 _ n +2, GSL 2 _ n +3 respectively. The GSL devices GD 2 _ n , GD 2 _ n +1, GD 2 _ n +2, GSL 2 _ n +3 are not controlled by the same ground select line.

Instead, the GSL devices GD 2 _ n are controlled by the ground select line GSL 2 _ n , the GSL devices GD 2 _ n +1 are controlled by the ground select line GSL 2 _ n +1, the GSL devices GD 2 _ n +2 are controlled by the ground select line GSL 2 _ n +2, and the GSL devices GD 2 _ n +3 are controlled by the ground select line GSL 2 _ n +3. For example, if the GSL devices GD 2 _ n are turned on, the voltage provided from the common source line CSL 2 can be applied into the strings S 22 , S 25 connected the GSL devices GD 2 _ n.

In the all bit lines sensing scheme embodiment, the strings S 22 , S 25 are regarded as one page, the strings S 23 , S 26 are regarded as one page, and the strings S 24 , S 27 are regarded as one page, and the strings S 21 , S 28 are regarded as one page.

In FIG. 6 , the strings S 22 , S 25 are read. The strings S 23 , S 24 , S 27 , S 28 are floating. A channel potential of each of the strings S 23 , S 24 , S 27 , S 28 is boosted to be the predetermined voltage level Vch. Therefore, the voltage difference between the gate and the channel in each unselected cell in the strings S 23 , S 24 , S 27 , S 28 can be reduced from “the difference between the pass voltage Vpass and 0 V” to “the difference between the pass voltage Vpass and the predetermined voltage level Vch.” Furthermore, the SSL device SD 2 _ n is turned on by the string select line SSL 2 _ n , so the channel potential of the string S 21 is induced to be the predetermined bit line voltage Vbl provided from the odd bit line BL 2 _odd. And the SSL device SD 2 _ n +1 is turned on by the string select line SSL 2 _ n +1, so the channel potential of the string S 26 is induced to be the predetermined bit line voltage Vbl provided from the even bit line BL 2 _even. Therefore, the voltage difference between the gate and the channel in each unselected cell in the strings S 21 , S 26 can be reduced from “the difference between the pass voltage Vpass and 0 V” to “the difference between the pass voltage Vpass and the predetermined bit line voltage Vbl.” As such, the voltage difference in each of the unselected cells is reduced, and then the read disturbance can be prevented.

Please refer to table I, which shows the read operation for reading the page consisting of the strings S 22 , S 25 . In table I, the string select lines SSL 2 _ n , SSL 2 _ n +1 are selected to be applied the predetermined string select voltage Vssl; the unselected string select lines SSL 2 _ n +2, SSL 2 _ n +3 are applied 0 voltage. The ground select line GSL 2 _ n is selected to be applied the predetermined ground select voltage Vgsl; the unselected ground select lines GSL 2 _ n +1, GSL 2 _ n +2, GSL 2 _ n +3 are applied 0 voltage. The common source line CSL 2 is applied 0 voltage. The even bit lines BL 2 _even and the odd bit lines BL 2 _odd are all selected to be applied the predetermined voltage Vbl.

Please refer to table II, which shows the read operation for reading the page 1 . In table II, the string select lines SSL 2 _ n +1, SSL 2 _ n +2 are selected to be applied the predetermined string select voltage Vssl; the unselected string select lines SSL 2 _ n , SSL 2 _ n +3 are applied 0 voltage. The ground select line GSL 2 _ n +1 is selected to be applied the predetermined ground select voltage Vgsl; the unselected ground select lines GSL 2 _ n , GSL 2 _ n +2, GSL 2 _ n +3 are applied 0 voltage. The common source line CSL 2 is applied 0 voltage. The even bit lines BL 2 _even and the odd bit lines BL 2 _odd are all selected to be applied the predetermined voltage Vbl.

Please refer to table III, which shows the read operation for reading the page 2 . In table III, the string select lines SSL 2 _ n +2, SSL 2 _ n +3 are selected to be applied the predetermined string select voltage Vssl; the unselected string select lines SSL 2 _ n , SSL 2 _ n +1 are applied 0 voltage. The ground select line GSL 2 _ n +2 is selected to be applied the predetermined ground select voltage Vgsl; the unselected ground select lines GSL 2 _ n , GSL 2 _ n +1, GSL 2 _ n +3 are applied 0 voltage. The common source line CSL 2 is applied 0 voltage. The even bit lines BL 2 _even and the odd bit lines BL 2 _odd are all selected to be applied the predetermined voltage Vbl.

Please refer to table IV, which shows the read operation for reading the page 3 . In table IV, the string select lines SSL 2 _ n +3, SSL 2 _ n are selected to be applied the predetermined string select voltage Vssl; the unselected string select lines SSL 2 _ n +1, SSL 2 _ n +2 are applied 0 voltage. The ground select line GSL 2 _ n +3 is selected to be applied the predetermined ground select voltage Vgsl; the unselected ground select lines GSL 2 _ n , GSL 2 _ n +1, GSL 2 _ n +2 are applied 0 voltage. The common source line CSL 2 is applied 0 voltage. The even bit lines BL 2 _even and the odd bit lines BL 2 _odd are all selected to be applied the predetermined voltage Vbl.

Base on above, during the all bit lines sensing scheme, the voltage difference between the gate and the channel in each unselected cell can be reduced to be “the difference between the pass voltage Vpass and the predetermined voltage level Vch” or “the difference between the pass voltage Vpass and the predetermined bit line voltage Vbl.” As such, the read disturbance can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.