Inventor

Hang-Ting Lue

Inventor

Hsinchu, TW

Overview

2005–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 204 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices29%

H10DInorganic electric semiconductor devices24%

G11CStatic stores22%

H01LSemiconductor devices13%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

G06FElectric digital data processing1%

B82YSpecific uses or applications of nanostructures1%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices0%

H10NElectric solid-state devices not otherwise provided for0%

PatentTitleYear

11,011,234Non-volatile memory and operating method thereof2021 10,978,485Vertical-channel ferroelectric flash memory2021 10,916,3083D flash memory module and healing and operating methods of 3D flash memory2021 10,910,399Three dimensional memory device and method for fabricating the same2021 10,891,077Flash memory device and controlling method thereof2021 10,847,523Stacked memory and ASIC device2020 10,847,535Three dimensional memory device and method for fabricating the same2020 10,790,028AND type flash memory2020 10,777,5663D array arranged for memory and in-memory sum-of-products operations2020 10,741,2473D memory array device and method for multiply-accumulate2020 10,727,243Three dimensional memory device fabricating method and applications thereof2020 10,664,746Neural network system2020 10,629,6083D vertical channel tri-gate NAND memory with tilted hemi-cylindrical structure2020 10,566,348Tilted hemi-cylindrical 3D NAND array having bottom reference conductor2020 10,535,673High-density flash memory device and method of manufacturing the same2020 10,403,637Discrete charge trapping elements for 3D NAND architecture2019 10,388,720Capacitor with 3D NAND memory2019 10,381,0943D memory with staged-level multibit programming2019 10,276,250Programming NAND flash with improved robustness against dummy WL disturbance2019 RE047311Silicon on insulator and thin film transistor bandgap engineered split gate memory2019 10,211,218U-shaped vertical thin-channel memory2019 10,141,328Three dimensional memory device and method for fabricating the same2018 9,922,989'Memory device having interchangeable gate/channel transistor and manufacturing method of the same'2018 9,831,257SGVC 3D architecture with floating gate device in lateral recesses on sides of conductive strips and insulating strips2017 9,761,319'Reading method for preventing read disturbance and memory using the same'2017 RE046522'Memory device, manufacturing method and operating method of the same'2017 9,698,156'Vertical thin-channel memory'2017 9,672,920'Electronic device, non-volatile memorty device, and programming method'2017 9,620,217'Sub-block erase'2017 9,530,503'And-type SGVC architecture for 3D NAND flash'2016 9,524,980'U-shaped vertical thin-channel memory'2016 9,520,485'3D independent double gate flash memory on bounded conductor layer'2016 9,490,017'Forced-bias method in sub-block erase'2016 9,490,249'Antenna effect discharge circuit and manufacturing method'2016 9,461,175'Dual-mode memory devices and methods for operating same'2016 9,425,191'Memory device and manufacturing method of the same'2016 9,401,369'Memory device and method for fabricating the same'2016 9,397,110'3D independent double gate flash memory'2016 9,391,084'Bandgap-engineered memory with multiple charge trapping layers storing charge'2016 9,385,184'Active device and semiconductor device with the same'2016 9,385,203'Active device and high voltage-semiconductor device with the same'2016 9,379,129'Assist gate structures for three-dimensional (3D) vertical gate array memory structure'2016 9,356,105'Ring gate transistor design for flash memory'2016 9,349,745'3D NAND nonvolatile memory with staggered vertical gates'2016 9,348,748'Heal leveling'2016 9,331,204'High voltage field effect transistors and circuits utilizing the same'2016 9,324,437'Systems and methods for trimming control transistors for 3D NAND flash'2016 9,305,653'Memory array and operating method of same'2016 9,287,291'Multiple-bit-per-cell, independent double gate, vertical channel memory having split channel'2016 9,287,406'Dual-mode transistor devices and methods for operating same'2016 9,269,660'Multilayer connection structure'2016 9,263,143'Three dimensional memory device and data erase method thereof'2016 9,252,155'Memory device and method for manufacturing the same'2016 9,245,603'Integrated circuit and operating method for the same'2016 9,240,405'Memory with off-chip controller'2016 9,224,611'Semiconductor structure and manufacturing method and operating method of the same'2015 9,224,474'P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals'2015 9,214,236'Thermally assisted flash memory with diode strapping'2015 9,214,351'Memory architecture of thin film 3D array'2015 9,214,471'Memory architecture of 3D array with diode in memory string'2015 9,190,467'Semiconductor structure and manufacturing method of the same'2015 9,171,636'Hot carrier generation and programming in NAND flash'2015 9,147,468'Multiple-bit-per-cell, independent double gate, vertical channel memory'2015 9,140,976'Mask design with optically isolated via and proximity correction features'2015 9,099,538'Conductor with a plurality of vertical extensions for a 3D device'2015 9,087,736'Three-dimensional memory device'2015 9,087,825'Semiconductor structure and method for manufacturing the same'2015 9,082,656'NAND flash with non-trapping switch transistors'2015 9,035,369'Semiconductor structure and manufacturing method of the same'2015 9,024,374'3D memory array with improved SSL and BL contact layout'2015 9,018,047'3D NAND flash memory'2015 9,001,590'Method for operating a semiconductor structure'2015 8,987,098'Damascene word line'2015 8,975,687'Nonvolatile memory array with continuous charge storage dielectric stack'2015 8,951,862'Damascene word line'2015 8,947,936'Memory architecture of 3D array with diode in memory string'2015 8,941,166'Multiple patterning method'2015 8,937,340'Silicon on insulator and thin film transistor bandgap engineered split gate memory'2015 8,935,594'Structure of ECC spare bits in 3D memory'2015 8,922,020'Integrated circuit pattern and method'2014 8,890,233'3D memory array with improved SSL and BL contact layout'2014 8,889,509'Charge trapping devices with field distribution layer over tunneling barrier'2014 8,861,273'Bandgap engineered charge trapping memory in two-transistor nor architecture'2014 8,860,124'Depletion-mode charge-trapping flash device'2014 8,853,818'3D NAND flash memory'2014 8,846,549'Method of forming bottom oxide for nitride flash memory'2014 8,829,646'Integrated circuit 3D memory array and manufacturing method'2014 8,824,212'Thermally assisted flash memory with segmented word lines'2014 8,811,077'Memory architecture of 3D array with improved uniformity of bit line capacitances'2014 8,780,602'Integrated circuit self aligned 3D memory array and manufacturing method'2014 8,772,858'Vertical channel memory and manufacturing method thereof and operating method using the same'2014 8,760,928'NAND flash biasing operation'2014 8,759,899'Integration of 3D stacked IC device with peripheral circuits'2014 8,724,393'Thermally assisted flash memory with diode strapping'2014 8,705,278'One-transistor cell semiconductor on insulator random access memory'2014 8,704,205'Semiconductor structure with improved capacitance of bit line'2014 8,675,381'Transistor having an adjustable gate resistance and semiconductor device comprising the same'2014 8,659,944'Memory architecture of 3D array with diode in memory string'2014 8,643,078'Semiconductor structure and manufacturing method of the same'2014 8,644,077'Memory device, manufacturing method and operating method of the same'2014 8,630,114'Memory architecture of 3D NOR array'2014 8,609,554'Semiconductor structure and method for manufacturing the same'2013 8,598,032'Reduced number of masks for IC device with stacked contact levels'2013 8,574,992'Contact architecture for 3D memory array'2013 8,547,741'Nonvolatile stacked NAND memory'2013 8,501,574'Resistive memory device and manufacturing method thereof and operating method thereof'2013 8,503,213'Memory architecture of 3D array with alternating memory string orientation and string select structures'2013 8,486,791'Mufti-layer single crystal 3D stackable memory'2013 8,488,387'Thermally assisted dielectric charge trapping flash'2013 8,482,052'Silicon on insulator and thin film transistor bandgap engineered split gate memory'2013 8,481,388'Non-volatile memory device having a nitride-oxide dielectric layer'2013 8,467,219'Integrated circuit self aligned 3D memory array and manufacturing method'2013 8,437,192'3D two bit-per-cell NAND flash memory'2013 8,432,719'Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride'2013 8,426,294'3D memory array arranged for FN tunneling program and erase'2013 8,383,512'Method for making multilayer connection structure'2013 8,378,410'Semiconductor device and method of manufacturing the same'2013 8,362,615'Memory and manufacturing method thereof'2013 8,363,476'Memory device, manufacturing method and operating method of the same'2013 8,343,840'Blocking dielectric engineered charge trapping memory cell with high speed erase'2013 8,330,210'High-Îº capped blocking dielectric bandgap engineered SONOS and MONOS'2012 8,325,530'Cell operation methods using gate-injection for floating gate NAND flash memory'2012 8,324,681'Stacked non-volatile memory device and methods for fabricating the same'2012 8,315,095'Multi-gate bandgap engineered memory'2012 8,304,911'Semiconductor structure and manufacturing method of the same'2012 8,288,815'Gate structure of semiconductor device having a conductive structure with a middle portion and two spacer portions'2012 8,284,597'Diode memory'2012 8,264,028'Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays'2012 8,252,654'Method for manufacturing memory cell'2012 8,207,571'Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase'2012 8,208,279'Integrated circuit self aligned 3D memory array and manufacturing method'2012 8,203,187'3D memory array arranged for FN tunneling program and erase'2012 8,183,617'Injection method with Schottky source/drain'2012 8,153,491'Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer'2012 8,149,628'Operating method of non-volatile memory device'2012 8,119,481'High-Îº capped blocking dielectric bandgap engineered SONOS and MONOS'2012 8,101,483'Semiconductor device and method for manufacturing the same'2012 8,101,989'Charge trapping devices with field distribution layer over tunneling barrier'2012 8,094,497'Multi-gate bandgap engineered memory'2012 8,072,813'Method and apparatus for programming nonvolatile memory'2011 8,068,370'Floating gate memory device with interpoly charge trapping structure'2011 8,030,166'Lateral pocket implant charge trapping devices'2011 8,026,179'Patterning method and integrated circuit structure'2011 8,023,328'Memory device with charge trapping layer'2011 8,022,489'Air tunnel floating gate memory cell'2011 7,999,302'Charge trapping devices with field distribution layer over tunneling barrier'2011 7,999,295'Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same'2011 7,986,556'Methods of operating non-volatile memory devices'2011 7,977,735'Stacked non-volatile memory device and methods for fabricating the same'2011 7,977,227'Method of manufacturing a non-volatile memory device'2011 7,973,366'Dual-gate, sonos, non-volatile memory cells and arrays thereof'2011 7,948,799'Structure and method of sub-gate NAND memory with bandgap engineered SONOS devices'2011 7,924,626'Efficient erase algorithm for SONOS-type NAND flash'2011 7,910,981'Semiconductor device and method of manufacturing the same'2011 7,907,450'Methods and apparatus for implementing bit-by-bit erase of a flash memory device'2011 7,902,589'Dual gate multi-bit semiconductor memory array'2011 7,881,123'Multi-operation mode nonvolatile memory'2011 7,855,411'Memory cell'2010 7,851,848'Cylindrical channel charge trapping devices with effectively high coupling ratios'2010 7,848,148'One-transistor cell semiconductor on insulator random access memory'2010 7,838,923'Lateral pocket implant charge trapping devices'2010 7,839,696'Method of programming and erasing a p-channel BE-SONOS NAND flash memory'2010 7,816,727'High-Îº capped blocking dielectric bandgap engineered SONOS and MONOS'2010 7,781,825'Semiconductor device and method for manufacturing the same'2010 7,772,072'Method for manufacturing non-volatile memory'2010 7,763,927'Non-volatile memory device having a nitride-oxide dielectric layer'2010 7,737,488'Blocking dielectric engineered charge trapping memory cell with high speed erase'2010 7,709,334'Stacked non-volatile memory device and methods for fabricating the same'2010 7,701,769'Method and apparatus for programming nonvolatile memory'2010 7,688,626'Depletion mode bandgap engineered memory'2010 7,652,320'Non-volatile memory device having improved band-to-band tunneling induced hot electron injection efficiency and manufacturing method thereof'2010 7,643,349'Efficient erase algorithm for SONOS-type NAND flash'2010 7,642,585'Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays'2010 7,636,257'Methods of operating p-channel non-volatile memory devices'2009 7,576,386'Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer'2009 7,560,762'Asymmetric floating gate NAND flash memory'2009 7,529,137'Methods of operating bandgap engineered memory'2009 7,511,335'Non-volatile memory'2009 7,512,016'Method of programming and erasing a p-channel be-SONOS NAND flash memory'2009 7,510,924'Method for manufacturing memory cell'2009 7,483,308'Programming and erasing method for charge-trapping memory devices'2009 7,483,309'Programming and erasing method for charge-trapping memory devices'2009 7,473,589'Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same'2009 7,468,299'Non-volatile memory cells and methods of manufacturing the same'2008 7,463,530'Operating method of non-volatile memory device'2008 7,426,140'Bandgap engineered split gate memory'2008 7,414,282'Method of manufacturing a non-volatile memory device'2008 7,414,889'Structure and method of sub-gate and architectures employing bandgap engineered SONOS devices'2008 7,391,652'Method of programming and erasing a p-channel BE-SONOS NAND flash memory'2008 7,315,474'Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays'2008 7,279,385'Flash memory device and manufacturing method thereof'2007 7,274,601'Programming and erasing method for charge-trapping memory devices'2007 7,268,379'Memory cell and method for manufacturing the same'2007 7,259,995'Memory device'2007 7,209,390'Operation scheme for spectrum shift in charge trapping non-volatile memory'2007 7,200,045'Method for programming a charge-trapping nonvolatile memory cell by raised-Vs channel initialed secondary electron injection (CHISEL)'2007 7,164,603'Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory'2007 7,133,316'Program/erase method for P-channel charge trapping memory device'2006 7,130,221'Dual gate multi-bit semiconductor memory'2006 7,088,613'Method for controlling current during read and program operations of programmable diode'2006 7,075,828'Operation scheme with charge balancing erase for charge trapping non-volatile memory'2006 7,067,375'Non-volatile memory and method for fabricating the same'2006 6,998,671'Localized split floating gate device using drain coupling to suppress the second bit effect'2006 6,906,940'Plane decoding method and device for three dimensional memories'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2021Patents assigned to MACRONIX INT CO LTD (200)· patent assignee history

2005–2021Based in Hsinchu, TW· patent location history

2007–2016Patents assigned to LUE HANG-TING (71)· patent assignee history

2007–2015Patents assigned to SHIH YEN-HAO (12)· patent assignee history

2010Based in Kaohsiung, TW· patent location history

2012–2016Patents assigned to CHEN SHIH-HUNG (21)· patent assignee history

2012–2014Patents assigned to LAI ERH-KUN (15)· patent assignee history

2014–2019Based in Zhubei City, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MACRONIX INT CO LTD	200	2005–2021
LUE HANG-TINGself	71	2007–2016
CHEN SHIH-HUNG	21	2012–2016
LAI ERH-KUN	15	2012–2014
SHIH YEN-HAO	12	2007–2015

Locations

Location	Patents	Span
Hsinchu, TW	191	2005–2021
Zhubei City, TW	12	2014–2019
Kaohsiung, TW	1	2010