Semiconductor device and method of forming the semiconductor device

The present invention relates generally to a semiconductor device and method of making the semiconductor device and, more particularly, to a semiconductor device which includes first and second vertical field effect transistors (VFETs) connected in parallel and third and fourth VFETs connected in series.

Related art devices such as NAND and NOR devices are formed using complementary metal oxide semiconductor (CMOS) technology. These CMOS devices may be formed, for example, by using a traditional (e.g., horizontal) transistor configuration.

For example, in forming a CMOS NAND device, an n-well is formed in a p-type substrate, and a pair of p-type field effect transistors (pFETs) is formed in the n-well, and connected in parallel. A pair of n-type FETs (nFETs) is then formed on the substrate adjacent to the pair of nFETs, and connected in series.

Thus, the related art CMOS NAND device has a physical layout that covers a large area of the substrate.

An exemplary aspect of the present invention is directed to a semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, a third VFET formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth VFET formed on the substrate and connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.

Another exemplary aspect of the present invention is directed to a semiconductor device including a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, a third VFET formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth VFET formed on the substrate and connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin. The first gate is formed on the third fin under the second gate, the third fin includes an undoped region between the first and second gates, and the undoped region is gated by a fringing effect which couples the first and second gates, and the first gate is formed on the fourth fin under the second gate, the fourth fin includes an undoped region between the first and second gates, and the undoped region is gated by a fringing effect which couples the first and second gates.

Another exemplary aspect of the present invention is directed to a method of forming a semiconductor device. The method includes forming a first vertical field effect transistor (VFET) on a substrate, the first VFET including a first fin and a first gate formed on the first fin, forming a second VFET on the substrate, the second VFET being connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, forming a third VFET on the substrate, the third VFET including a third fin, and the first and second gates being formed on the third fin, and forming a fourth VFET on the substrate, the fourth VFET being connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.

With its unique and novel features, the exemplary aspects of the present invention may reduce an area required for a physical layout of the device (i.e., increase basic universal gate functionality density) and reduce wiring length, resulting in a reduction in design effort and metal layer clutter as well as line loss effects which degrade performance.

The exemplary aspects of the present invention will be better understood from the following detailed description of the exemplary embodiments of the invention with reference to the drawings, in which:

FIG. 1 illustrates a first side of the semiconductor device 100 , according to an exemplary aspect of the present invention, according to an exemplary aspect of the present invention.

FIG. 2 illustrates a second side of the semiconductor device 100 opposite the first side, according to an exemplary aspect of the present invention.

FIG. 3A illustrates a top view of a configuration of the first gate G 1 , according to an exemplary aspect of the present invention.

FIG. 3B illustrates a top view of a configuration of the second gate G 2 , according to an exemplary aspect of the present invention.

FIG. 4A is schematic diagram of a semiconductor device 401 , according to an exemplary aspect of the present invention.

FIG. 4B is schematic diagram of a semiconductor device 402 , according to an exemplary aspect of the present invention.

FIG. 5 illustrates a first side of the semiconductor device 500 , according to another exemplary aspect of the present invention.

FIG. 6 illustrates a second side of the semiconductor device 500 opposite the first side, according to another exemplary aspect of the present invention.

FIG. 7 illustrates a semiconductor device 700 , according to another exemplary aspect of the present invention.

FIG. 8 illustrates a method 800 of forming a semiconductor device, according to another exemplary aspect of the present invention.

The invention will now be described with reference to FIGS. 1-9 , in which like reference numerals refer to like parts throughout. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features can be arbitrarily expanded or reduced for clarity. Exemplary embodiments are provided below for illustration purposes and do not limit the claims.

Scaling of the related art CMOS NAND devices (e.g., including traditional transistors) is becoming more and more challenging. One option to address this is to move high-level design/circuit structures to a lower integration level.

By moving a NAND or NOR to a lower level, an exemplary aspect of the present invention may increase basic universal gate functionality density, and reduce wiring length. This reduction will yield a savings in not only design effort, but also metal layer clutter as well as line loss effects which degrade performance.

FIGS. 1 and 2 illustrate a semiconductor device 100 , according to an exemplary aspect of the present invention.

In particular, FIG. 1 illustrates a first side of the semiconductor device 100 , according to an exemplary aspect of the present invention, and FIG. 2 illustrates a second side of the semiconductor device 100 opposite the first side, according to an exemplary aspect of the present invention.

As illustrated in FIGS. 1 and 2 , the semiconductor device 100 includes a first vertical field effect transistor (VFET) VF 1 formed on a substrate, and including a first fin F 1 and a first gate G 1 formed on the first fin F 1 , a second VFET VF 2 formed on the substrate and connected in parallel with the first VFET VF 1 , and including a second fin F 2 and a second gate G 2 formed on the second fin F 2 , a third VFET VF 3 formed on the substrate and including a third fin F 3 , the first and second gates G 1 , G 2 being formed on the third fin F 3 , and a fourth VFET VF 4 (see FIG. 2 ) formed on the substrate and connected in series with the third VFET VF 3 , and including a fourth fin F 4 , the first and second gates G 1 , G 2 being formed on the fourth fin F 4 .

The semiconductor device 100 may also include a first diffusion region D 1 and a first power supply contact P 1 formed on the first diffusion region D 1 . The semiconductor device 100 may also include a second diffusion region D 2 and a second power supply contact P 2 formed on the second diffusion region D 2 .

The semiconductor device 100 may be configured as either a complementary metal oxide semiconductor (CMOS) NAND device (e.g., a 2WNAND logic gate) or a CMOS NOR device (e.g., a 2WNOR logic gate).

In particular, if the first and second VFETs VF 1 , VF 2 (connected in parallel) are p-type VFETs and the third and fourth VFETs VF 3 , VF 4 (connected in series) are n-type VFETs, then the semiconductor device 100 is configured as a (CMOS) NAND device. In this case, the first diffusion region D 1 would be a p-type diffusion region, the second diffusion region D 2 would be an n-type diffusion region, the first power supply contact P 1 would be a V DD contact, and the second power supply contact P 2 would be a ground contact.

On the other hand, if the first and second VFETs VF 1 , VF 2 (connected in parallel) are n-type VFETs and the third and fourth VFETs VF 3 , VF 4 (connected in series) are p-type VFETs, then the semiconductor device 100 is configured as a (CMOS) NOR device. In this case, the first diffusion region D 1 would be an n-type diffusion region, the second diffusion region D 2 would be a p-type diffusion region, the first power supply contact P 1 would be a ground contact, and the second power supply contact P 2 would be a V DD contact.

As illustrated in FIGS. 1 and 2 , the first, second, third and fourth fins F 1 -F 4 may be formed of a semiconductor material (e.g., silicon) and may form a channel region of the first, second, third and fourth VFETs VF 1 -VF 4 , respectively. The gates G 1 and G 2 may be formed of conductive material such as polysilicon or metal, and may wrap around the fins F 1 -F 4 in the X-direction and Z-direction (e.g., in a direction substantially parallel to a surface of the diffusion regions D 1 , D 2 ).

The first gate G 1 may be formed on the third fin F 3 either above or beneath the second gate G 2 . For example, as illustrated in FIG. 1 , the first gate G 1 is formed on the third fin F 3 above the second gate G 2 .

Similarly, the first gate G 1 may be formed on the fourth fin F 4 either above or beneath the second gate G 2 . For example, as illustrated in FIG. 2 , the first gate G 1 is formed on the fourth fin F 4 above the second gate G 2 .

As illustrated in FIG. 1 , a width in a Y-direction of the first gate G 1 on the first fin F 1 is greater than a width in the Y-direction of first gate G 1 on the third fin F 3 . Similarly, as illustrated in FIG. 2 , a width in the Y-direction of the second gate G 2 on the second fin F 2 is greater than a width in the Y-direction of second gate G 2 on the fourth fin F 3 .

In particular, a width in a Y-direction of the first gate G 1 on the first fin F 1 may be in a range from 30 nm to 60 nm, whereas a width in the Y-direction of first gate G 1 on the third fin F 3 may be in a range from 15 nm to 25 nm. Similarly, as illustrated in FIG. 2 , a width in the Y-direction of the second gate G 2 on the second fin F 2 may be in a range from 30 nm to 60 nm, whereas a width in the Y-direction of second gate G 2 on the fourth fin F 4 may be in a range from 15 nm to 25 nm.

Generally, the semiconductor material of the first, second, third and fourth fins F 1 -F 4 may be doped semiconductor material having a dopant concentration in a range from 1×10 15 cm −3 to 5×10 18 cm −3 although would typically be virtually undoped.

An entirety of the first and second fins F 1 , F 2 (or at least the portions on which the first and second gates G 1 , G 2 are formed) may be doped semiconductor material. However, at least a portion 150 of the semiconductor material of the third fin F 3 which is between the first and second gates G 1 , G 2 is formed of undoped semiconductor material. This portion 150 is a region of the third fin F 3 that may be gated by a gate fringing effect. A width of the portion 150 in the Z-direction (e.g., a distance between the first and second gates G 1 , G 2 on the third fin F 3 ) may be, for example, in a range from 1 nm to 4 nm (e.g., 2 nm to 3 nm), in order to provide the gate fringing effect.

Similarly, at least a portion 155 of the semiconductor material of the fourth fin F 4 which is between the first and second gates G 1 , G 2 is formed of undoped semiconductor material. This portion 155 is a region of the fourth fin F 4 that may be gated by the gate fringing effect. A width of the portion 155 in the Z-direction (e.g., a distance between the first and second gates G 1 , G 2 on the fourth fin F 4 ) may be, for example, in a range from 1 nm to 4 nm (e.g., 2 nm to 3 nm), in order to provide the gate fringing effect.

The gate fringing effect is an electric field leakage through a periphery of the first and second gates G 1 , G 2 , which may couple the first and second gates G 1 , G 2 (e.g., form a device-device interconnect). That is, the gate fringing effect may cause an intergate effect (e.g., inversion layer) in the channel of the third and fourth VFETs VF 3 , VF 4 (e.g., in the third and fourth fins F 3 , F 4 ). This effect may increase as the size of the semiconductor device 100 is reduced.

Referring again to FIG. 1 , the semiconductor device 100 may also include an output contact 190 for providing an output signal of the semiconductor device 100 (e.g., NAND device or NOR device). In particular, the output contact 190 may be formed on (e.g., above in the Z-direction) the first, second, third and fourth fins F 1 -F 4 , and between the first and second fins F 1 , F 2 on one side, and the third and fourth fins F 3 , F 4 on the other side.

The output contact 190 may constitute at least a part of a device-bus interconnect in the semiconductor device 100 .

Referring again to the drawings, FIGS. 3A and 3B illustrate a configuration of the first and second gates G 1 , G 2 , respectively.

In particular, FIG. 3A illustrates a top view of a configuration of the first gate G 1 , according to an exemplary aspect of the present invention. As illustrated in FIG. 3A , the first gate G 1 is formed around the first, third and fourth fins F 1 , F 3 and F 4 , but not around the second fin F 2 . As illustrated in FIG. 3A , the contact 190 may be formed between the first and third fins F 1 , F 3 .

FIG. 3B illustrates a top view of a configuration of the second gate G 2 , according to an exemplary aspect of the present invention. As illustrated in FIG. 3B , the second gate G 2 is formed around the second, third and fourth fins F 2 , F 3 and F 4 , but not around the first fin F 1 . As illustrated in FIG. 3B , the contact 190 may be formed between the second and fourth fins F 2 , F 4 .

It should be noted that this configuration of the gates G 1 , G 2 may be the same regardless of whether the semiconductor device 100 is configured as a CMOS NAND device or a CMOS NOR device.

FIG. 4A is schematic diagram of a semiconductor device 401 , according to an exemplary aspect of the present invention. The semiconductor device 401 may have a physical configuration as illustrated in FIGS. 1 and 2 , and more particularly, is configured as a CMOS NAND device.

That is, as illustrated in FIG. 4A , in the semiconductor device 401 , the first and second VFETS VF 1 , VF 2 are p-type VFETS that are connected in parallel, and the third and fourth VFETS VF 3 , VF 4 are n-type VFETS that are connected in series). Further, the first and second VFETS VF 1 , VF 2 are connected to V DD and the third and fourth VFETS VF 3 , VF 4 are connected to ground. An output contact 190 (e.g., device-bus interconnect) is connected between the first and second VFETS VF 1 , VF 2 on one side, and the third and fourth VFETS VF 3 , VF 4 on the other side.

The connection (e.g., coupling) between VF 3 and VF 4 may be provided by the gate fringing effect at regions 150 and 155 , as described above.

FIG. 4B is schematic diagram of a semiconductor device 402 , according to an exemplary aspect of the present invention. The semiconductor device 402 may have a physical configuration as illustrated in FIGS. 1 and 2 , and more particularly, is configured as a CMOS NOR device.

That is, as illustrated in FIG. 4B , in the semiconductor device 402 , the first and second VFETS VF 1 , VF 2 are n-type VFETS connected in parallel, and the third and fourth VFETS VF 3 , VF 4 are p-type VFETS connected in series. Further, the first and second VFETS VF 1 , VF 2 are connected to ground and the third and fourth VFETS VF 3 , VF 4 are connected to V DD . An output contact 190 (e.g., device-bus interconnect) is connected between the first and second VFETS VF 1 , VF 2 on one side, and the third and fourth VFETS VF 3 , VF 4 on the other side.

Again, the connection (e.g., coupling) between VF 3 and VF 4 may be provided by the gate fringing effect at regions 150 and 155 , as described above.

Referring again to the drawings, FIGS. 5 and 6 illustrate a semiconductor device 500 , according to another exemplary aspect of the present invention.

In particular, FIG. 5 illustrates a first side of the semiconductor device 500 , according to another exemplary aspect of the present invention, and FIG. 6 illustrates a second side of the semiconductor device 500 opposite the first side, according to another exemplary aspect of the present invention.

As illustrated in FIGS. 5 and 6 , the semiconductor device 500 includes a first vertical field effect transistor (VFET) VF 1 formed on a substrate, and including a first fin F 1 and a first gate G 1 formed on the first fin F 1 , a second VFET VF 2 formed on the substrate and connected in parallel with the first VFET VF 1 , and including a second fin F 2 and a second gate G 2 formed on the second fin F 2 , a third VFET VF 3 formed on the substrate and including a third fin F 3 , the first and second gates G 1 , G 2 being formed on the third fin F 3 , and a fourth VFET VF 4 (see FIG. 6 ) formed on the substrate and connected in series with the third VFET VF 3 , and including a fourth fin F 4 , the first and second gates G 1 , G 2 being formed on the fourth fin F 4 .

The semiconductor device 500 may also include a first diffusion region D 1 and a first power supply contact P 1 formed on the first diffusion region D 1 . The semiconductor device 100 may also include a second diffusion region D 2 and a second power supply contact P 2 formed on the second diffusion region D 2 .

The semiconductor device 500 may be configured as either a complementary metal oxide semiconductor (CMOS) NAND device (e.g., a 2WNAND logic gate) or a CMOS NOR device (e.g., a 2WNOR logic gate).

In particular, if the first and second VFETs VF 1 , VF 2 (connected in parallel) are p-type VFETs and the third and fourth VFETs VF 3 , VF 4 (connected in series) are n-type VFETs, then the semiconductor device 500 is configured as a (CMOS) NAND device. In this case, the first diffusion region D 1 would be a p-type diffusion region, the second diffusion region D 2 would be an n-type diffusion region, the first power supply contact P 1 would be a V DD contact, and the second power supply contact P 2 would be a ground contact.

On the other hand, if the first and second VFETs VF 1 , VF 2 (connected in parallel) are n-type VFETs and the third and fourth VFETs VF 3 , VF 4 (connected in series) are p-type VFETs, then the semiconductor device 500 is configured as a (CMOS) NOR device. In this case, the first diffusion region D 1 would be an n-type diffusion region, the second diffusion region D 2 would be a p-type diffusion region, the first power supply contact P 1 would be a ground contact, and the second power supply contact P 2 would be a V DD contact.

As illustrated in FIGS. 5 and 6 , the first, second, third and fourth fins F 1 -F 4 may be formed of a semiconductor material (e.g., silicon) and may form a channel region of the first, second, third and fourth VFETs VF 1 -VF 4 , respectively. The gates G 1 and G 2 may be formed of conductive material such as polysilicon or metal, and may wrap around the fins F 1 -F 4 in the X-direction and Z-direction (e.g., in a direction substantially parallel to a surface of the diffusion regions D 1 , D 2 ).

The first gate G 1 may be formed on the third fin F 3 either above or beneath the second gate G 2 . For example, as illustrated in FIG. 5 , the first gate G 1 is formed on the third fin F 3 above the second gate G 2 .

Similarly, the first gate G 1 may be formed on the fourth fin F 4 either above or beneath the second gate G 2 . For example, as illustrated in FIG. 6 , the first gate G 1 is formed on the fourth fin F 4 above the second gate G 2 .

It should be noted that a difference between the semiconductor device 500 in FIGS. 5 and 6 , and the semiconductor device 100 in FIGS. 1 and 2 , is that in the semiconductor device 100 , a width in the Z-direction of the first gate G 1 on the first fin F 1 is greater than a width in the Z-direction of first gate G 1 on the third fin F 3 (see FIG. 1 ), and a width in the Z-direction of the second gate G 2 on the second fin F 2 is greater than a width in the Z-direction of second gate G 2 on the fourth fin F 3 (see FIG. 2 ).

However, in the semiconductor device 500 , a width in the Z-direction of the first gate G 1 on the first fin F 1 may be substantially equal to a width in the Z-direction of first gate G 1 on the third fin F 3 (see FIG. 5 ), and a width in the Z-direction of the second gate G 2 on the second fin F 2 may be substantially equal to a width in the Z-direction of second gate G 2 on the fourth fin F 3 (see FIG. 6 ).

Further, the first fin F 1 includes a region 571 between the first gate G 1 and the diffusion region D 1 , that is doped (e.g., heavily doped) for conductivity, and the second fin F 2 includes a region 572 between the second gate G 2 and the output contact 590 (e.g., output contact) that is doped (e.g., heavily doped) for conductivity.

The regions 571 , 572 may constitute at least a part of a device-bus interconnect in the semiconductor device 500 .

The amount of doping in the regions 571 , 572 may be the same or different, and may be greater than an amount of doping of the remaining portion of the first and second fins F 1 , F 2 (e.g., the portions around which the first and second gates G 1 , G 2 are wrapped). In particular, the amount of doping in the regions 571 , 572 may be in a range from 1×10 19 cm −3 to 1×10 22 cm −3 .

Further, at least a portion 550 of the semiconductor material of the third fin F 3 which is between the first and second gates G 1 , G 2 is formed of undoped semiconductor material. This portion 550 is a region of the third fin F 3 that may be gated by a gate fringing effect. A width of the portion 550 in the Z-direction (e.g., a distance between the first and second gates G 1 , G 2 on the third fin F 3 ) may be, for example, in a range from 1 nm to 4 nm (e.g., 2 nm to 3 nm), in order to provide the gate fringing effect.

Similarly, at least a portion 555 of the semiconductor material of the fourth fin F 4 which is between the first and second gates G 1 , G 2 is formed of undoped semiconductor material. This portion 555 is a region of the fourth fin F 4 that may be gated by the gate fringing effect. A width of the portion 555 in the Z-direction (e.g., a distance between the first and second gates G 1 , G 2 on the fourth fin F 4 ) may be, for example, in a range from 1 nm to 4 nm (e.g., 2 nm to 3 nm), in order to provide the gate fringing effect.

Similar to the semiconductor device 100 , in the semiconductor device 500 the gate fringing effect is an electric field leakage through a periphery of the first and second gates G 1 , G 2 , which may couple the first and second gates G 1 , G 2 (e.g., form a device-device interconnect). That is, the gate fringing effect may cause an intergate effect (e.g., inversion layer) in the channel of the third and fourth VFETs VF 3 , VF 4 (e.g., in the third and fourth fins F 3 , F 4 ).

Referring again to FIG. 5 , the semiconductor device 500 may also include an output contact 590 for providing an output signal of the semiconductor device 500 (e.g., NAND device or NOR device). In particular, the output contact 590 may be formed on (e.g., above in the Z-direction) the first, second, third and fourth fins F 1 -F 4 , and between the first and second fins F 1 , F 2 on one side, and the third and fourth fins F 3 , F 4 on the other side.

The output contact 590 along with the regions 571 , 572 may constitute a device-bus interconnect in the semiconductor device 500 .

FIG. 7 illustrates a semiconductor device 700 , according to another exemplary aspect of the present invention. The semiconductor device 700 is similar in structure to the semiconductor device 100 and the semiconductor device 500 , but the semiconductor device 700 utilizes an extended contact 790 to constitute a part of the device-bus interconnect. That is, for example, the extended contact 790 in FIG. 7 , may be used in place of the conductive region 572 in FIG. 6 to form a part of the device-bus interconnect.

As illustrated in FIG. 7 , the extended contact 790 includes a lateral portion 790 b which is formed on (e.g., over) the first, second, third and fourth fins F 1 -F 4 , and an extended portion 790 a which is formed on the second fin F 2 , and extends down from the lateral portion 790 b toward the second gate G 2 .

The extended portion 790 a may have a length in the Y-direction in a range from 20 nm to 50 nm. In particular, the extended portion 790 a may wrap around the second fin F 2 in the X-direction and Z-direction, or may be formed on only a portion of the second fin F 2 (e.g., only on an outer longitudinal side of the second fin F 2 ).

Further, an end of the extended portion 790 a in the Y-direction which is nearest to the second gate G 2 may be formed to be substantially aligned with a bottom of the first gate G 1 on the fourth fin F 4 . That is, the end of the extended portion 790 a may be at least 5-10 nm from the second gate G 2 in the Y-direction.

Other features and functions of the semiconductor device 700 may be similar to those of the semiconductor device 500 described above.

FIG. 9 illustrates a method 900 of forming a semiconductor device, according to another exemplary aspect of the present invention.

As illustrated in FIG. 9 , the method 900 includes forming ( 910 ) a first vertical field effect transistor (VFET) on a substrate, the first VFET including a first fin and a first gate formed on the first fin, forming ( 920 ) a second VFET on the substrate, the second VFET being connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, forming ( 930 ) a third VFET on the substrate, the third VFET including a third fin, and the first and second gates being formed on the third fin, and forming ( 940 ) a fourth VFET on the substrate, the fourth VFET being connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.

With its unique and novel features, the exemplary aspects of the present invention may reduce an area required for a physical layout of the device (i.e., increase basic universal gate functionality density) and reduce wiring length, resulting in a reduction in design effort and metal layer clutter as well as line loss effects which degrade performance.

While the invention has been described in terms of one or more embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. Specifically, one of ordinary skill in the art will understand that the drawings herein are meant to be illustrative, and the design of the inventive method and system is not limited to that disclosed herein but may be modified within the spirit and scope of the present invention.

Further, Applicant's intent is to encompass the equivalents of all claim elements, and no amendment to any claim the present application should be construed as a disclaimer of any interest in or right to an equivalent of any element or feature of the amended claim.