Inventor

Terence B. Hook

Inventor

Jericho, VT, US

Overview

1996–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 189 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices23%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%

H10BElectronic memory devices4%

G06FElectric digital data processing4%

B82YSpecific uses or applications of nanostructures2%

H03KPulse technique1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%

PatentTitleYear

11,101,367Contact-first field-effect transistors2021 11,067,895Method and structures for personalizing lithography2021 11,011,513Integrating a junction field effect transistor into a vertical field effect transistor2021 10,978,454Semiconductor device and method of forming the semiconductor device2021 10,971,356Stack viabar structures2021 10,964,812Integration of input/output device in vertical field-effect transistor technology2021 10,957,794Vertical transistor contact for cross-coupling in a memory cell2021 10,937,793Vertical transistor contact for a memory cell with increased density2021 10,916,478Methods of performing fin cut etch processes for FinFET semiconductor devices2021 10,910,312Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices2021 10,910,282Prevention of charging damage in full-depletion devices2021 10,903,165Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices2021 10,903,332Fully depleted SOI transistor with a buried ferroelectric layer in back-gate2021 10,840,373Integration of input/output device in vertical field-effect transistor technology2020 10,833,069Logic gate designs for 3D monolithic direct stacked VTFET2020 10,748,901Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices2020 10,741,544Integration of electrostatic discharge protection into vertical fin technology2020 10,700,209Independent gate FinFET with backside gate contact2020 10,691,870Checking wafer-level integrated designs for rule compliance2020 10,629,443Bottom source/drain silicidation for vertical field-effect transistor (FET)2020 10,615,027Stack viabar structures2020 10,615,276Integration of input/output device in vertical field-effect transistor technology2020 10,608,080Bulk to silicon on insulator device2020 10,607,938Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices2020 10,607,992Semiconductor device and method of forming the semiconductor device2020 10,586,854Gate-all-around field effect transistor having multiple threshold voltages2020 10,566,453Vertical transistor contact for cross-coupling in a memory cell2020 10,559,670Nanosheet field effect transistors with partial inside spacers2020 10,559,572Vertical transistor contact for a memory cell with increased density2020 10,546,787Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device2020 10,541,253FinFETs with various fin height2020 10,515,859Extra gate device for nanosheet2019 10,504,889Integrating a junction field effect transistor into a vertical field effect transistor2019 10,418,462Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process2019 10,381,346Logic gate designs for 3D monolithic direct stacked VTFET2019 10,366,897Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer2019 10,346,580Checking wafer-level integrated designs for rule compliance2019 10,347,494Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer2019 10,340,340Multiple-threshold nanosheet transistors2019 10,332,959Bulk to silicon on insulator device2019 10,326,019Fully-depleted CMOS transistors with U-shaped channel2019 10,319,596Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer2019 10,283,411Stacked vertical transistor device for three-dimensional monolithic integration2019 10,276,558Electrostatic discharge protection using vertical fin CMOS technology2019 10,254,340Independently driving built-in self test circuitry over a range of operating conditions2019 10,249,743Semiconductor device with low band-to-band tunneling2019 10,249,739Nanosheet MOSFET with partial release and source/drain epitaxy2019 10,248,755Checking wafer-level integrated designs for antenna rule compliance2019 10,229,915Mirror contact capacitor2019 10,224,327Semiconductor device with different fin pitches2019 10,211,316Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process2019 10,204,839Prevention of charging damage in full-depletion devices2019 10,170,584Nanosheet field effect transistors with partial inside spacers2019 10,170,463Bipolar transistor compatible with vertical FET fabrication2019 10,170,576Stable work function for narrow-pitch devices2019 10,163,934Fully-depleted silicon-on-insulator transistors2018 10,153,291Lateral non-volatile storage cell2018 10,134,760FinFETs with various fin height2018 10,128,377Independent gate FinFET with backside gate contact2018 10,128,347Gate-all-around field effect transistor having multiple threshold voltages2018 10,121,877Vertical field effect transistor with metallic bottom region2018 10,109,639Lateral non-volatile storage cell2018 10,090,330Structure and method for fully depleted silicon on insulator structure for threshold voltage modification2018 10,038,083Semiconductor device with low band-to-band tunneling2018 10,002,800Prevention of charging damage in full-depletion devices2018 9,997,539Fully-depleted silicon-on-insulator transistors2018 9,997,607Mirrored contact CMOS with self-aligned source, drain, and back-gate2018 9,990,459Checking wafer-level integrated designs for antenna rule compliance2018 9,991,339Bulk to silicon on insulator device2018 9,985,099Semiconductor device with low band-to-band tunneling2018 9,984,883Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer2018 9,978,871Bulk to silicon on insulator device2018 9,972,497Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer2018 9,947,593Extra gate device for nanosheet2018 9,947,664Semiconductor device and method of forming the semiconductor device2018 9,947,743Structures and methods for long-channel devices in nanosheet technology2018 9,941,300Structure and method for fully depleted silicon on insulator structure for threshold voltage modification2018 9,929,145'Bipolar transistor compatible with vertical FET fabrication'2018 9,881,925'Mirror contact capacitor'2018 9,859,172'Bipolar transistor compatible with vertical FET fabrication'2018 9,853,127Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process2017 9,818,650'Extra gate device for nanosheet'2017 9,805,935'Bottom source/drain silicidation for vertical field-effect transistor (FET)'2017 9,793,271'Semiconductor device with different fin pitches'2017 9,786,546'Bulk to silicon on insulator device'2017 9,768,079'Extra gate device for nanosheet'2017 9,761,525'Multiple back gate transistor'2017 9,761,712'Vertical transistors with merged active area regions'2017 9,741,707'Immunity to inline charging damage in circuit designs'2017 9,741,706'Immunity to inline charging damage in circuit designs'2017 9,735,250'Stable work function for narrow-pitch devices'2017 9,711,501'Interlayer via'2017 9,673,190'ESD device compatible with bulk bias capability'2017 9,673,221'Semiconductor device with low band-to-band tunneling'2017 9,666,693'Structure and method to minimize junction capacitance in NANO sheets'2017 9,653,463'Semiconductor device with different fin pitches'2017 9,627,484'Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer'2017 9,601,513'Subsurface wires of integrated chip and methods of forming'2017 9,589,956'Semiconductor device with different fin pitches'2017 9,583,486'Stable work function for narrow-pitch devices'2017 9,577,038'Structure and method to minimize junction capacitance in nano sheets'2017 9,520,329'Fully-depleted silicon-on-insulator transistors'2016 9,520,391'Field effect transistor having delay element with back gate'2016 9,515,138'Structure and method to minimize junction capacitance in nano sheets'2016 9,490,335'Extra gate device for nanosheet'2016 9,484,270'Fully-depleted silicon-on-insulator transistors'2016 9,431,388'Series-connected nanowire structures'2016 9,378,329'Immunity to inline charging damage in circuit designs'2016 9,236,398'Passive devices for FinFET integrated circuit technologies'2016 9,219,114'Partial FIN on oxide for improved electrical isolation of raised active regions'2015 9,178,495'Establishing a thermal profile across a semiconductor chip'2015 9,171,952'Low gate-to-drain capacitance fully merged finFET'2015 9,142,564'Pseudo butted junction structure for back plane connection'2015 9,064,976'Modeling charge distribution on FinFET sidewalls'2015 9,064,885'Electrostatic discharge resistant diodes'2015 9,064,824'In-situ annealing for extending the lifetime of CMOS products'2015 9,059,120'In-situ relaxation for improved CMOS product lifetime'2015 9,054,124'Electrostatic discharge resistant diodes'2015 9,018,052'Integrated circuit including DRAM and SRAM/logic'2015 9,012,997'Semiconductor device including ESD protection device'2015 9,009,638'Estimating transistor characteristics and tolerances for compact modeling'2015 8,994,085'Integrated circuit including DRAM and SRAM/logic'2015 8,959,008'Method for dynamically switching analyses and for dynamically switching models in circuit simulators'2015 8,916,426'Passive devices for FinFET integrated circuit technologies'2014 8,881,379'Method of making heat sink for integrated circuit devices'2014 8,835,330'Integrated circuit including DRAM and SRAM/logic'2014 8,729,908'Static noise margin monitoring circuit and method'2014 8,653,597'Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip'2014 8,653,596'Integrated circuit including DRAM and SRAM/logic'2014 8,619,979'Physically unclonable function implemented through threshold voltage comparison'2013 8,564,074'Self-limiting oxygen seal for high-K dielectric and design structure'2013 8,552,500'Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability'2013 8,513,106'Pseudo butted junction structure for back plane connection'2013 8,431,955'Method and structure for balancing power and performance using fluorine and nitrogen doped substrates'2013 8,416,009'Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip'2013 8,407,656'Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range'2013 8,230,586'Method of cooling a resistor'2012 8,012,848'Trench isolation and method of fabricating trench isolation'2011 7,994,895'Heat sink for integrated circuit devices'2011 7,939,894'Isolated high performance FET with a controllable body resistance'2011 7,928,513'Protection against charging damage in hybrid orientation transistors'2011 7,879,650'Method of providing protection against charging damage in hybrid orientation transistors'2011 7,863,112'Method and structure to protect FETs from plasma damage during FEOL processing'2011 7,824,933'Method of determining n-well scattering effects on FETs'2010 7,785,979'Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same'2010 7,712,057'Determining allowance antenna area as function of total gate insulator area for SOI technology'2010 7,709,365'CMOS well structure and method of forming the same'2010 7,682,910'Method of selectively adjusting ion implantation dose on semiconductor devices'2010 7,649,262'Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing'2010 7,615,827'Dual gate dielectric thickness devices and circuits using dual gate dielectric thickness devices'2009 7,572,650'Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing'2009 7,566,946'Precision passive circuit structure'2009 7,560,345'Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage'2009 7,516,426'Methods of improving operational parameters of pair of matched transistors and set of transistors'2009 7,492,016'Protection against charging damage in hybrid orientation transistors'2009 7,470,959'Integrated circuit structures for preventing charging damage'2008 7,310,036'Heat sink for integrated circuit devices'2007 7,300,807'Structure and method for providing precision passive elements'2007 7,302,376'Device modeling for proximity effects'2007 7,173,338'Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing'2007 7,166,904'Structure and method for local resistor element in integrated circuit technology'2007 7,132,323'CMOS well structure and method of forming the same'2006 7,132,318'Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage'2006 7,098,513'Low trigger voltage, low leakage ESD NFET'2006 7,087,470'Dual gate dielectric thickness devices'2006 7,067,886'Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage'2006 6,956,417'Leakage compensation circuit'2005 6,881,672'Selective silicide blocking'2005 6,825,490'On chip resistor calibration structure and method'2004 6,797,592'Method for forming a retrograde implant'2004 6,700,163'Selective silicide blocking'2004 6,670,683'Composite transistor having a slew-rate control'2003 6,610,585'Method for forming a retrograde implant'2003 6,489,223'Angled implant process'2002 6,339,018'Silicide block bounded device'2002 6,333,204'Dual EPI active pixel cell design and method of making the same'2001 6,307,805'High performance semiconductor memory device with low power consumption'2001 6,278,102'Method of detecting electromagnetic radiation with bandgap engineered active pixel cell design'2001 6,271,565'Asymmetrical field effect transistor'2001 6,256,755'Apparatus and method for detecting defective NVRAM cells'2001 6,239,649'Switched body SOI (silicon on insulator) circuits and fabrication method therefor'2001 6,194,702'Method of forming a complementary active pixel sensor cell'2001 6,083,794'Method to perform selective drain engineering with a non-critical mask'2000 6,026,964'Active pixel sensor cell and method of using'2000 6,022,770'NVRAM utilizing high voltage TFT device and method for making the same'2000 5,982,225'Hot electron compensation for improved MOS transistor reliability'1999 5,972,765'Use of deuterated materials in semiconductor processing'1999 5,898,196'Dual EPI active pixel cell design and method of making the same'1999 5,562,770'Semiconductor manufacturing process for low dislocation defects'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2021Patents assigned to IBM (179)· patent assignee history

1996–2021Based in Jericho Center, VT, US· patent location history

2001–2021Based in Jericho, VT, US· patent location history

2010–2021Based in Essex Junction, VT, US· patent location history

2012–2015Patents assigned to HOOK TERENCE B (14)· patent assignee history

2014–2015Patents assigned to CHENG KANGGUO (2)· patent assignee history

2015–2018Patents assigned to GLOBALFOUNDRIES INC (8)· patent assignee history

2016–2018Patents assigned to MENDEZ HORACIO (3)· patent assignee history

2017Based in Terence, VT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	179	1996–2021
HOOK TERENCE Bself	14	2012–2015
GLOBALFOUNDRIES INC	8	2015–2018
MENDEZ HORACIO	3	2016–2018
CHENG KANGGUO	2	2014–2015

Locations

Location	Patents	Span
Jericho, VT, US	159	2001–2021
Jericho Center, VT, US	25	1996–2021
Essex Junction, VT, US	4	2010–2021
Terence, VT, US	1	2017