Integrated level translator and latch for fence architecture

The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells, methods of manufacture and use.

Voltage level translator circuits are useful in certain applications, including wireless handsets, notebook computers and personal digital assistants (PDAs) and, more particularly in SRAM cells, which run on two or more different voltage levels. For example, circuitry utilized with such portable applications may be configured so that a portion of the circuitry, such as, for example, input/output (IO) buffers, runs at a higher voltage level, while another portion of the circuitry, e.g., core logic, runs at a lower voltage level. This difference in voltage levels often necessitates the use of a voltage level translator circuit for interfacing between the multiple voltage levels.

Conventional voltage level translator circuits have been found to be unreliable at certain process, voltage and/or temperature (PVT) conditions. In fact, it has been found that conventional level translators and latch circuitry is slow as logic depth is high. Also, the conventional level translator and latch circuitry has high setup time. Moreover, the clock and wordline propagation delay in such conventional configurations can be high. In addition, conventional latches are not well suited for fenced architectures.

In an aspect of the disclosure, a structure comprises an integrated level translator and latch for input signals comprising a first clock (CLKS) and a second clock (CLKH), the first clock (CLKS) being used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) being a latch clock.

In an aspect of the disclosure, an integrated level translator and latch for input signals comprises: a first clock (CLKS) in VCS domain and which is configured as a precharge and evaluation clock with its timing being critical for forward edge; a second clock (CLKH) derived from the first clock (CLKS); a third clock (CLKHN) which is inverse to the second clock (CLKN), the second clock (CLKN) and the third clock (CLKHN) being latch clocks; and a keeper device comprising a plurality of transistors in series. A first transistor of the keeper device is independently controlled by an input (INP) and a second transistor of the keeper device is controlled by an output (OUTN) of a level translator.

In an aspect of the disclosure, a method comprises: at the initial stage of operation, setting a first clock (CLKHN) and a second clock (CLKS) to low and a third clock (CLKH) to high, wherein the low signals of the first clock (CLKHN) and the second clock (CLKS) result in an input (INP) going low; and holding a keeper device in an ON state so that an output (OUT) will be pre-charged to low, which is fed to the keep device as the input (INP).

The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.

FIG. 1 shows an integrated level translator and latch circuit in accordance with aspects of the present disclosure.

FIG. 2 shows a timing diagram of the integrated level translator and latch circuit of FIG. 1 .

FIG. 3 shows an integrated level translator and latch circuit and accompanying timing diagram in accordance with additional aspects of the present disclosure.

FIG. 4 shows an integrated level translator and latch circuit and accompanying timing diagram in accordance with additional aspects of the present disclosure.

The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures, methods of manufacture and use. As should be understood by those of skill in the art, fence architecture means all the inputs are latched at the boundary of the SRAM cell. In this way, all setup and hold are referenced with respect to this latch. Other styles of architecture include set up and hold referenced internal to the SRAM cell.

In more specific embodiments, the present disclosure describes integrated level translator and latch circuits for all input signals including wordline (WL) decoder, WL address, decode address and column address. In embodiments, the integrated level translator and latch circuits include two clocks, CLKH and CLKS, with CLKS being used as a pre-charge/evaluation clock in VCS domain, with only the timing of clock CLKS being critical for forward edge.

Advantageously, in embodiments, the integrated level translator and latch circuits have low logical depth and achieves higher performance, e.g., faster access time and enables high frequency operation, than conventional circuits. In addition, the integrated level translator and latch circuits have reduced setup and hold time for the latch, with the hold time being tunable for improved yields. In addition, the circuits described herein provide many additional advantages including, but not limited to:

(i) Pre-charge and evaluate scheme is highly suitable for WL decoders;

(ii) Providing a smaller size than a conventional latch and level translator, hence providing considerable savings of real estate on a semiconductor chip;

(iii) Providing less load on clock due to clock leg sharing;

(iv) Consuming less power (e.g., low power) due to only the selected address decode signal having to be toggled; and

(v) Compatible with fenced architectures.

FIG. 1 shows an integrated level translator and latch circuit in accordance with aspects of the present disclosure. In particular, the integrated level translator and latch circuit 10 of FIG. 1 includes two clocks: CLKH and CLKS. In embodiments, CLKH is a hold clock and CLKS is a pre-charge/evaluation clock in the VCS domain, with only the timing of clock CLKS being critical for forward edge. In embodiments, the clock CLKS is an internal, self-timed clock which has a slight delay to the external clock CLK. The input to the integrated level translator and latch circuit 10 is in the VDD domain, whereas, the output is in the VCS domain.

The integrated level translator and latch circuit 10 further includes CLKHN, which is an inverted clock CLKH. For example, when the clock CLKH goes low, the clock CLKHN will go high, or vice versa. In embodiments, the clocks CLKH/CLKHN are the latch clocks which are derived from the clock CLKS (e.g., rising edge pulse stretched clock CLKS is clock CLKHN at approximately six 6 gates pulse stretch delay (see timing diagram of FIG. 2 )). Accordingly, the clock CLKH is equal to the CLKS with a rising edge delay but with a falling edge being the same as clock CLKS. (See, e.g., FIG. 2 .) In embodiments, in order to reduce loading on the clocks CLKS, CLKH and CLKHN, the boxed legs are shared across four such latches.

Still referring to FIG. 1 , the integrated level translator and latch circuit 10 further includes a plurality of transistors T 1 -T 10 . In embodiments, transistors T 5 and T 6 are PMOS transistors arranged in a series configuration and which are configured to be used as a keeper device 20 . As should be understood by those of skill in the art, the operation of the PMOS transistor T 5 of the keeper device 20 is dependent on the input INP; whereas, the operation of the PMOS transistor T 6 of the keeper device 20 operates by the output signal, OUTN.

In embodiments, the transistors T 7 -T 10 are configured to be used as a feedback loop 30 . In one implementation, the transistors T 7 and T 8 are PMOS transistors and the transistors T 9 and T 10 are NMOS transistors, all of which are arranged in a series configuration. As further shown in FIG. 1 , the transistors T 1 -T 2 are PMOS transistors and transistors T 3 -T 4 are NMOS transistors arranged in a series configuration, with their output OUTN leading to one of the keeper device 20 , the feedback loop 30 or an inverter 40 . Transistor T 4 can be shared across four blocks to minimize clock loading.

FIG. 1 further shows the inverter 40 provided at the output, OUTN, of the transistors T 1 -T 4 . Moreover, a NOR gate 50 is shown to have an input INPN (VDD) or input of the clock CLKHN. The output of the NOR gate 50 is the input INP. As should be understood by those of skill in the art, the input INPN is part decoded WL address in the VDD domain. In embodiments, 8 WL addresses and 20 latches can be provided for a 256 WL.

FIG. 2 shows a timing diagram of the integrated level translator and latch circuit of FIG. 1 . Referring to both the timing diagram of FIG. 2 and the integrated level translator and latch circuit 10 of FIG. 1 , the setup time of the integrated level translator and latch circuit 10 is provided in relation to the rising edge of the clock CLKS; whereas, the hold time is provided in relation to the rising edge of the clock CLKHN. For example, when the clock CLKS is low, the output OUT is pre-charged low; whereas, when the input is high, the output is high (with the feedback loop 30 being in the OFF state). So, when the CLKS is high, the output will follow the input.

More specifically, at the initial stage of operation, the clock CLKHN and clock CLKS are low (and CLKH is high as inverted from clock CLKHN). The low signals of the clock CLKHN and clock CLKS will result in the input INP being low. In this initial stage, the PMOS transistors T 1 and T 2 are turned ON (e.g., high), and the output OUTN will turn ON the PMOS transistor T 6 of the keeper device 20 . In this way, the keeper device 30 will be held in an ON state and the output OUT will be pre-charged to low. It should be noted that the operation of the transistor T 5 is dependent on the input INP. For example, when INP is low, the transistor T 5 will be ON; whereas, when INP is high, the transistor T 5 will be turned OFF (e.g., resulting in the keeper device 20 being OFF). Also, when the CLKH is high the feedback loop 30 will be turned OFF, e.g., transistors T 7 and T 10 are turned OFF.

Still referring to FIGS. 1 and 2 , when the clock CLKS is high, e.g., INP is high, the transistor T 1 is turned OFF and the NMOS transistors T 3 and T 4 are turned ON. In turn, the output OUTN will be low and the output OUT will be high. In this operational stage, the PMOS transistor T 5 is turned OFF, resulting in the keeper device 20 being OFF. It should also be recognized that nothing is holding when the transistor T 1 is turned OFF. Also, it should be now be understood that when the clock CLKS is high, both the PMOS and NMOS devices (e.g., transistors T 7 -T 10 ) are turned OFF. And, in the evaluating mode, the keeper device 30 will hold the value of OUTN high. In embodiments, the pre-charge path is slower than the evaluate path.

FIG. 3 shows an integrated level translator and latch circuit and accompanying timing diagram in accordance with additional aspects of the present disclosure. In the embodiment of FIG. 3 , the integrated level translator and latch circuit 10 ′ includes feedback loop 30 and forward path 30 ′, while eliminating the need for the NOR gate 50 shown in FIG. 1 . As shown, the each of the feedback loop 30 and forward path 30 ′ include transistors T 7 -T 10 in a series arrangement. In addition, the PMOS transistor T 3 shown in FIG. 1 can be eliminated due to the fact that the clock signal of clock CLKHN will be fed through the feedback loop 30 and forward path 30 ′. Also, the clocks CLKH and CLKHN are in the VDD domain.

In operation of the circuit 10 ′, for example, when the clock CLKH is high and the clock CLKHN is low, the output OUTN will drive the input INP. Also, when the clock CLKH is low and the clock CLKHN is high, the feedback loop 30 and forward path 30 ′ will be turned ON. Also, although the integrated level translator and latch circuit 10 ′ is functionally equivalent to the circuit 10 of FIG. 1 , it should be recognized that the circuit 10 ′ of FIG. 3 has less loading on all the three clocks.

FIG. 4 shows an integrated level translator and latch circuit and accompanying timing diagram in accordance with additional aspects of the present disclosure. In FIG. 4 , the integrated level translator and latch circuit 10 ″ includes a forward path with five transistors (e.g., T 1 -T 4 and T 11 ), with the remaining portion of circuit 10 ″ similar to that shown in FIG. 1 . In embodiments, transistor T 11 is in the VCS domain which can be shared across four blocks to minimize clock loading. In addition, transistors T 3 and T 4 can also be shared across four blocks to minimize clock loading. In this embodiment, the input of the transistor T 11 is a signal from clock CLKHN and the input of the transistor T 11 is a signal from clock CLKH.

In operation, when the CLKS is high, the integrated level translator and latch circuit 10 ″ will be in the evaluate mode. Also, in the initial operational stage, when the clock CLKH is high and the clock CLKHN is low, the transistors T 1 and T 5 are turned ON, the transistor T 4 is OFF and the initial output OUTN is pre-charged high. In embodiments, the transistor T 2 may or may not be turned ON, depending on the inputs A, B, C. In turn, the output OUT is low. Also, when the CLKS is low, the output OUT is pre-charged to low; whereas, when the clock CLKS is high, the output OUT is equal to INP. On the other hand, when the clock CLKH is low and clock CLKHN is high, the feedback loop 20 will be ON, which will hold the state of the output OUT.

In embodiments, the inputs A, B, C are WL address in VDD domain and the clock CLKS is the pre-charge/evaluation clock in the VCS domain. Also, as previously noted, the clocks CLK/CLKN are derived from CLKS (e.g., rising edge pulse stretched CLKS is CLKN of approximately 6 gates pulse stretch delay). Additionally, the clocks CLK/CLKN are the latch clocks. Similar to that already described, setup time is in relation to the CLKS rising edge and the hold is in relation to the CLKN rising edge. Moreover, in order to reduce loading on CLKS, CLK and CLKN, the boxed legs are shared across four such latches.

The circuit of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the circuit of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the circuit uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.

The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.