Inventor
Venkatraghavan Bringivijayaraghavan
Inventor
Cheyyar, IN
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores56%
H03KPulse technique15%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
G06FElectric digital data processing5%
H01LSemiconductor devices3%
H04LTransmission of digital information, e.g. telegraphic communication3%
G01RMeasuring electric variables2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
11,024,347Multiple sense amplifier and data path-based pseudo dual port SRAM202110,964,357Skewed sense amplifier for single-ended sensing202110,600,474Write assist202010,522,217Column-dependent positive voltage boost for memory cell supply voltage201910,510,384Intracycle bitline restore in high performance memory201910,395,700Integrated level translator201910,381,069Write assist201910,217,507Bending circuit for static random access memory (SRAM) self-timer201910,199,095Bit line strapping scheme for high density SRAM201910,186,312Hybrid stack write driver201910,176,857Read and write scheme for high density SRAM201910,170,164Sense amplifier latch circuit and sense amplifier multiplexed latch circuit201910,020,809Integrated level translator and latch for fence architecture20189,929,064'Through-substrate via (TSV) testing'20189,905,279'Systems, circuits, and methods for charge sharing'20189,881,669'Wordline driver with integrated voltage level shift function'20189,859,873'Minimization of bias temperature instability (BTI) degradation in circuits'20189,787,292'High performance multiplexed latches'20179,761,285'Sense amplifier and latching scheme'20179,721,628'Address based memory data path programming scheme'20179,607,668'Systems, circuits, and methods for charge sharing'20179,570,155'Circuit to improve SRAM stability'20179,570,156'Data aware write scheme for SRAM'20179,548,104'Boost control to improve SRAM write operation'20179,437,282'High performance sense amplifier'20169,405,468'Stacked memory device control'20169,400,602'Stacked memory device control'20169,390,769'Sense amplifiers and multiplexed latches'20169,281,045'Refresh hidden eDRAM memory'20169,251,890'Bias temperature instability state detection and correction'20169,236,116'Memory cells with read access schemes'20169,208,859'Low power static random access memory (SRAM) read data path'20159,157,960'Through-substrate via (TSV) testing'20159,111,599'Memory device'20158,984,320'Command paths, apparatuses and methods for providing a command to a data block'20158,824,233'Systems, circuits, and methods for charge sharing'20148,797,080'Circuits, apparatuses, and methods for delay models'20148,767,483'Apparatus and methods having majority bit detection'20148,760,961'Write command and write data timing circuit and methods for timing the same'20148,644,096'Command paths, apparatuses, memories, and methods for providing internal commands to a data path'20148,582,380'Systems, circuits, and methods for charge sharing'20138,509,011'Command paths, apparatuses, memories, and methods for providing internal commands to a data path'20138,441,888'Write command and write data timing circuit and methods for timing the same'20138,064,269'Apparatus and methods having majority bit detection'20118,023,343'Systems and methods for issuing address and data signals to a memory array'20118,004,313'Methods, devices, and systems for a high voltage tolerant buffer'20117,969,813'Write command and write data timing circuit and methods for timing the same'20117,746,720'Techniques for reducing leakage current in memory devices'20107,729,182'Systems and methods for issuing address and data signals to a memory array'20107,605,611'Methods, devices, and systems for a high voltage tolerant buffer'20097,511,534'Circuits, devices, systems, and methods of operation for a linear output driver'20097,245,548'Techniques for reducing leakage current in memory devices'20076,965,263'Bulk node biasing method and apparatus'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2018Patents assigned to MICRON TECHNOLOGY INC (23)· patent assignee history
2005–2010Based in Boise, ID, US· patent location history
2009–2018Based in Plano, TX, US· patent location history
2011–2015Patents assigned to BRINGIVIJAYARAGHAVAN VENKATRAGHAVAN (8)· patent assignee history
2011–2015Patents assigned to BROWN JASON M (3)· patent assignee history
2014–2021Based in Cheyyar, IN· patent location history
2015–2020Patents assigned to GLOBALFOUNDRIES INC (25)· patent assignee history
2015–2018Patents assigned to IBM (6)· patent assignee history
2015–2019Based in Tamilnadu, IN· patent location history
2017Based in Bengaluru, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 25 | 2015–2020 |
| MICRON TECHNOLOGY INC | 23 | 2005–2018 |
| BRINGIVIJAYARAGHAVAN VENKATRAGHAVANself | 8 | 2011–2015 |
| IBM | 6 | 2015–2018 |
| BROWN JASON M | 3 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cheyyar, IN | 22 | 2014–2021 |
| Plano, Texas, US | 16 | 2009–2018 |
| Tamilnadu, IN | 11 | 2015–2019 |
| Boise, ID, US | 3 | 2005–2010 |
| Bengaluru, IN | 1 | 2017 |