Averaging circuit which determines average voltage of N samples, using log2N-scale capacitors

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-020691, filed Feb. 5, 2016, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to an averaging circuit which determines average voltage of N samples, using log 2 N-scale capacitors.

A discrete-time wireless receiver including a switched capacitor circuit has a high configurability. The discrete-time wireless receiver needs to eliminate noise. In a high-frequency domain applied to radio, noise is primarily thermal noise. The amplitude of noise approximates to a normal distribution.

In the case where the amplitude of noise contained in a signal approximates to a normal distribution, a number of signal values (samples) of the signal are sampled to determine an average value, so that the noise (noise power) contained in the signal can be reduced.

As an averaging circuit which determines an average value of N (a natural number of 2 or more) signal values, an averaging circuit employing N sampling switches and N capacitors is known.

FIG. 1 is a circuit diagram showing an example of an averaging circuit according to the first embodiment.

FIG. 2 is a circuit diagram showing an example of the first stage of an operation performed by the averaging circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing an example of the second stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 4 is a circuit diagram showing an example of the third stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 5 is a circuit diagram showing an example of the fourth stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 6 is a circuit diagram showing an example of the fifth stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 7 is a circuit diagram showing an example of the sixth stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 8 is a circuit diagram showing an example of the seventh stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 9 is a circuit diagram showing an example of the eighth stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 10 is a circuit diagram showing an example of the ninth stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 11 is a circuit diagram showing an example of the tenth stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 12 is a circuit diagram showing an example of the eleventh stage of the operation performed by the averaging circuit according to the first embodiment.

FIG. 13 is a circuit diagram showing an example of a general averaging circuit as a comparative example.

FIG. 14 is a graph showing an example of a relationship between noise power and the number N of signal values to be equalized in the averaging circuit according to the first embodiment.

FIG. 15 is a graph showing an example of a reduction result of a circuit area in the averaging circuit according to the first embodiment.

FIG. 16 is a circuit diagram showing an example of a schematic configuration of an averaging circuit according to the second embodiment.

FIG. 17 is a circuit diagram showing an example of a detailed configuration of the averaging circuit according to the second embodiment.

FIG. 18 is a timing chart showing an example of an operation of the averaging circuit, according to the second embodiment.

FIG. 19 is a circuit diagram showing an example of a schematic configuration of an averaging circuit according to the third embodiment.

FIG. 20 is a circuit diagram showing an example of a detailed configuration of the averaging circuit according to the third embodiment.

FIG. 21 is a timing chart showing an example of an operation of the averaging circuit according to the third embodiment.

In general, according to one embodiment, an averaging circuit includes a capacitor circuit and a controller which controls the capacitor circuit. The capacitor circuit includes a plurality of circuit units and a plurality of averaging switches. The circuit units includes capacitors and sampling switches. The capacitor and sampling switch included in each of the circuit units are connected in series to each other. The averaging switches switch two capacitors connected in serious among the capacitors included in the circuit units. The controller controls the sampling switches included in the circuit units and the averaging switches. The controller causes a first first-stage average voltage to be applied to a first capacitor included in the circuit units. The first first-stage average voltage is an average of a first sample voltage applied to the first capacitor and a second sample voltage applied to a second capacitor included in the circuit units. The controller causes a second first-stage average voltage to be applied to the second capacitor. The second first-stage average voltage is an average of a third sample voltage applied to the second capacitor and a fourth sample voltage applied to a third capacitor included in the circuit units. The controller causes a first second-stage average voltage to be applied to the first capacitor. The first second-stage average voltage is an average of the first and second first-stage average voltages applied to the first and second capacitors.

Embodiments will be described hereinafter with reference to the accompanying drawings. In the drawings, identical elements will be denoted by the same reference numbers, respectively.

First Embodiment

In the first embodiment, for example, a discrete-time wireless receiver includes a reception module which receives a given input signal N times at intervals, a noise elimination module which determines an average value of N signal values of the signal received by the reception module, to thereby eliminate noise from the signal, and a signal processor which performs analog/digital conversion based on the value of the signal from which the noise have been eliminated.

In the following explanation of the first embodiment, an averaging circuit included in a noise elimination module in a wireless transceiver is described by way of example; however, a device including the averaging circuit is not limited to this.

With respect to the first embodiment, an averaging circuit which determines an average value of N signal values (N is the number of samples) using (log 2 N)+1 capacitors will be referred to. With respect to the first embodiment, identical structural elements will be denoted by the same reference numeral, and after they are explained once, their explanations will be omitted or simply explained.

FIG. 1 is a circuit diagram showing an example of an averaging circuit according to the first embodiment.

In an example illustrated in FIG. 1 , N is 8; and FIG. 1 illustrates an averaging circuit which determines an average value of eight signal values using four capacitors. However, N can be changed as long as the formula N=A×2 P (A is 1, 2 or 3, and P is a natural number) is satisfied.

The averaging circuit 1 includes a switched capacitor circuit 2 and a controller 3 .

The switched capacitor circuit 2 includes four sampling switches S 1 to S 4 , four capacitors C 1 to C 4 and three averaging switches A 1 to A 3 . In the first embodiment, a sampling switch and a capacitor which are connected in series to each other may be handled as a single circuit unit.

The averaging circuit 1 includes four sampling switches S 1 to S 4 , four capacitors C 1 to C 4 and three averaging switches A 1 to A 3 .

One end of sampling switch S 1 is connected to input terminal I, and the other end of sampling switch S 1 is connected to one end of capacitor C 1 . The other end of capacitor C 1 is grounded.

The same is true of sampling switches S 2 to S 4 and capacitors C 2 to C 4 ; that is, sampling switches S 2 to S 4 and capacitors C 2 to C 4 are set in the same manner as sampling switch S 1 and capacitor C 1 .

Ends of averaging switches A 1 to A 3 are respectively connected to ends of sampling switches S 1 to S 3 and ends of capacitors C 1 to C 3 . The other ends of averaging switches A 1 to A 3 are respectively connected to the above ends of sampling switches S 2 to S 4 and the above ends of capacitors C 2 to C 4 .

The capacitances of capacitors C 1 to C 4 are equal to each other.

Output terminal O is connected to one end of one of capacitors C 1 and C 2 . In the example illustrated in FIG. 1 , output terminal O is connected to one end of capacitor C 1 .

The controller 3 , as described later, produces control signals for effecting switching between ON and OFF states (closing and opening) of each of sampling switches S 1 to S 4 and switching between ON and OFF states (closing and opening) of each of averaging switches A 1 to A 3 .

With reference to FIGS. 2 to 12 , it will be explained how the averaging circuit 1 is operated to determine an average value. FIGS. 2 to 12 illustrate the states of the switches at respective stages, omitting the controller 3 for simplicity.

FIG. 2 is a circuit diagram showing an example of the first stage of an operation performed by the averaging circuit 1 according to the first embodiment.

The averaging circuit 1 determines an average value of signal values of input signal D I input from input terminal I. The voltage of input signal D I varies with the passage of time.

At the first stage, the controller 3 opens (turns off) sampling switches S 1 to S 4 and averaging switches A 1 to A 3 . At this time, the voltages applied to capacitors C 1 to C 4 are zero.

FIG. 3 is a circuit diagram showing an example of the second stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the second stage, the controller 3 closes (turns on) sampling switch S 2 . Thereby, voltage V 1 of input signal D I at time t 1 is applied to capacitor C 2 connected in series to sampling switch S 2 . The voltage obtained based on input signal D I will be referred to as the sampling voltage.

FIG. 4 is a circuit diagram showing an example of the third stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the third stage, the controller 3 opens sampling switch S 2 , and then closes sampling switch S 1 . Thereby, voltage V 2 of input signal D I at time t 2 is applied to capacitor C 1 connected in series to sampling switch S 1 .

FIG. 5 is a circuit diagram showing an example of the fourth stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the fourth stage, the controller 3 opens sampling switch S 1 , and then closes sampling switch S 3 and averaging switch A 1 . Thereby, voltage V 3 of input signal D I at time t 3 is applied to capacitor C 3 connected in series to sampling switch S 3 . Furthermore, voltages applied to both capacitors C 1 and C 2 are equalized (their average is determined) and are each set to (V 1 +V 2 )/2.

FIG. 6 is a circuit diagram showing an example of the fifth stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the fifth stage, the controller 3 opens sampling switch S 3 and averaging switch A 1 , and resets the voltage applied to capacitor C 2 (sets the voltage to zero). Then, the controller 3 closes sampling switch S 2 . Thereby, voltage V 4 of input signal D I at time t 4 is applied to capacitor C 2 connected in series to sampling switch S 2 .

FIG. 7 is a circuit diagram showing an example of the sixth stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the sixth stage, the controller 3 opens sampling switch S 2 , and then closes averaging switch A 2 . Thereby, voltages applied to both capacitors C 2 and C 3 are equalized (their average is determined) and are each set to (V 3 +V 4 )/2.

FIG. 8 is a circuit diagram showing an example of the seventh stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the seventh stage, the controller 3 opens averaging switch A 2 , and then closes averaging switch A 1 . Thereby, voltages applied to both capacitors C 1 and C 2 are equalized (averaged out) and are each set to (V 1 +V 2 +V 3 +V 4 )/2.

FIG. 9 is a circuit diagram illustrating by way of example the eighth stage of the operation of the averaging circuit 1 according to the first embodiment.

At the eighth stage, the controller 3 opens averaging switch A 1 , and then resets the voltages applied to capacitors C 2 and C 3 (sets the voltages to zero).

FIG. 10 is a circuit diagram showing an example of the ninth stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the ninth stage, the controller 3 performs the same control over sampling switches S 2 to S 4 and averaging switches A 2 and A 3 as over sampling switches S 1 to S 3 and averaging switches A 1 and A 2 at the first to eighth stages as illustrated in FIGS. 2 to 9 .

FIG. 11 is a circuit diagram showing an example of the tenth stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the tenth stage, the voltage applied to capacitor C 1 is varied to (V 1 +V 2 +V 3 +V 4 )/4, and the voltage applied to capacitor C 2 is varied to (V 5 +V 6 +V 7 +V 8 )/4. It should be noted that voltages V 5 to V 8 are voltages of input signal D I at time t 5 to t 8 , respectively. The voltages applied to capacitors C 3 and C 4 are changed to zero.

FIG. 12 is a circuit diagram showing an example of the eleventh stage of the operation performed by the averaging circuit 1 according to the first embodiment.

At the eleventh stage, the controller 3 closes averaging switch A 1 . Thereby, voltages applied to both capacitors C 1 and C 2 are equalized and are each set to (V 1 +V 2 +V 3 +V 4 +V 5 +V 6 +V 7 +V 8 )/8.

The controller 3 causes charge accumulated in either capacitor C 1 or C 2 to be output from output terminal O. As a result, a voltage having the average value of the voltages of input signal D I at time t 1 to t 8 can be output.

It should be noted that the above second and third stages may be applied in reverse order. That is, it may be set that at the second stage, the controller 3 closes sampling switch S 1 to apply voltage V 1 to capacitor C 1 , and at the third stage, the controller 3 closes sampling switch S 2 to apply voltage V 2 to capacitor C 2 . In this case, at the fourth stage, the controller 3 opens sampling switch S 2 , and then closes sampling switch S 3 and averaging switch A 1 .

Furthermore, it may be set that in the above fourth and fifth stages, the controller 3 determines the average of the voltages applied to both capacitors C 1 and C 2 , and resets the voltage applied to capacitor C 2 (sets it to zero); and then causes voltage V 3 to be applied to capacitor C 3 by closing sampling switch S 3 , and voltage V 4 to be applied to capacitor C 2 by closing sampling switch S 2 . In this case, sampling switch S 3 and sampling switch S 2 may be operated in reverse order. That is, it may be set that sampling switch S 2 is closed to apply voltage V 3 to capacitor C 2 , and sampling switch S 3 is closed to apply voltage V 4 to capacitor C 3 .

Furthermore, the above operation of resetting the voltage applied to capacitor C 3 (setting it to zero) at the eighth stage may be performed at any time before the seventh stage is started after determining the average of the voltages applied to both capacitors C 2 and C 3 at the sixth stage.

The advantage of the averaging circuit 1 according to the first embodiment, which has the structure as described above, will be explained.

FIG. 13 is a circuit diagram showing an example of a general averaging circuit, which will be described as a comparative example. The averaging circuit 100 determines the average value of N signal values. In this case, the averaging circuit 100 includes N sampling switches S 1 to S N , N capacitors C 1 to C N and N−1 averaging switches A 1 to A N-1 .

One end of sampling switch S 1 is connected to input terminal I, and the other end of sampling switch S 1 is connected to one end of capacitor C 1 . The other end of capacitor C 1 is grounded.

The same is true of sampling switches S 2 to S N and capacitors C 2 to C N ; that is, sampling switches S 2 to S N and capacitors C 2 to C N are set in the same manner as sampling switch S 1 and capacitor C 1 .

Ends of averaging switches A 1 to A N-1 are respectively connected to ends of sampling switches S 1 to S N-1 and ends of capacitors C 1 to C N-1 . The other ends of averaging switches A 1 to A N-1 are respectively connected to the above ends of sampling switches S 2 to S N and the above ends of capacitors C 2 to C N .

The capacitances of capacitors C 1 to C N are equal to each other.

Output terminal O is connected to any of averaging switches A 1 to A N-1 .

First, the averaging circuit 100 opens sampling switches S 1 to S N , and also opens averaging switches A 1 to A N-1 .

Next, the averaging circuit 100 closes only sampling switch S 1 to accumulate in capacitor C 1 , charge input from input terminal I.

Subsequently, the averaging circuit 100 opens sampling switch S 1 and closes sampling switch S 2 to accumulate in capacitor C 2 , charge input from input terminal I.

Thereafter, in the same manner as described above, charge input from input terminal I is accumulated in capacitors C 3 to C N successively.

Then, the averaging circuit 100 open sampling switches S 1 to S N and close averaging switches A 1 to A N-1 to equalize the voltages applied to capacitors C 1 to C N , (determine the average of the voltages) i.e., equalize charge accumulated in capacitors C 1 to C N . The averaging circuit 100 outputs the equalized charge from any of capacitors C 1 to C N through output terminal O.

In the averaging circuit 100 , the greater the number N of signal values to be equalized (signal values the average of which is to be determined), the greater the number of sampling switches S 1 to S N , that of capacitors C 1 to C N and that of averaging switches A 1 to A N-1 . Therefore, the greater the number N of signal values to be equalized, the greater the area of the averaging circuit 100 .

FIG. 14 is a graph showing an example of a relationship between noise power and the number N of signal values to be equalized in the averaging circuit 1 according to the first embodiment.

In both a theoretical value and the result of a simulation such as one done with Simulation Program with Integrated Circuit Emphasis (SPICE), the greater the number N of signal values to be equalized, the lower the noise power. To be more specific, N signal values are equalized (the average of these signal values is determined), so that noise power can be reduced to 1/N.

FIG. 15 is a graph showing an example of a reduction result of a circuit area, i.e., the area of the averaging circuit 1 according to the first embodiment.

In an ordinary averaging circuit 100 , the greater the number N of signal values to be equalized, the greater the number of capacitors included in the averaging circuit 100 . Inevitably, the circuit area is increased in proportion to the increase in the number of capacitors. By contrast, in the averaging circuit 1 according to the first embodiment, the number M (M is a natural number of 2 or more) of capacitors can be reduced to (log 2 N)+1. That is, in the first embodiment, even if the number N of signal values is increased, it is restricted that the circuit area is increased.

The averaging circuit 1 according to the first embodiment is used to reduce noise in, for example, a wireless receiver. With respect to the averaging circuit 1 , the average of N signal values can be determined in a circuit area which varies in proportion to (log 2 N)+1, and is smaller than a circuit area varying in proportion to N. For example, where N=128, the area of the averaging circuit 1 can be reduced by approximately 94% of the area of the ordinary averaging circuit.

It should be noted that the above explanation of the first embodiment is given with respect to the case where the average of signal values is determined under a condition in which capacitors C 1 to C M have the same capacitance. However, if a plurality of capacitors, which are provided such that ends of the capacitors are connected to input terminal I, with switches interposed between the ends of the capacitors and the input terminal, and the other ends of the capacitors are grounded, have different capacitances which depend on the values of weighting coefficients, respectively, they can be applied to another kind of circuit such as a finite impulse response (FIR) filter.

Second Embodiment

The second embodiment will be explained by referring to the averaging circuit according to the first embodiment in detail. In the following, the explanations given above with reference to FIGS. 1 to 15 are not repeated.

FIG. 16 is a circuit diagram showing an example of a schematic configuration of an averaging circuit 1 according to the second embodiment.

FIG. 17 is a circuit diagram showing an example of a detailed configuration of the averaging circuit 1 according to the second embodiment.

The averaging circuit 1 includes M sampling switches S 1 to S M and M capacitors C 1 to C M , M−1 averaging switches A 1 to A M-1 , M reset switches R 1 to R M , reset switches R 1 to R M , output switch S OUT and output capacitor C OUT .

Ends of reset switches R 1 to R M are connected to ends of capacitors C 1 to C M , respectively. The other ends of reset switches R 1 to R M are grounded.

When reset switches R 1 to R M are closed (turned on), charge accumulated in capacitors C 1 to C M is reset so that the capacitances of capacitors C 1 to C M are set to zero. The controller 3 , as described later, produces control signals for effecting switching between ON and OFF states (closing and opening) of each of sampling switches S 1 to S 4 and switching between ON and OFF states (closing and opening) of each of averaging switches A 1 to A 3 .

An end of output switch S OUT is connected to an end of sampling switch S 1 and an end of capacitor C 1 . The other end of output switch S OUT is connected to an end of output capacitor C OUT and output terminal O. The other end of output capacitor C OUT is grounded.

When output switch S OUT is closed, output signal D 0 is output from output terminal O.

The controller 3 , as described later, produces control signals for effecting switching between ON and OFF states (closing and opening) of each of sampling switches S 1 to S M , each of averaging switches A 1 to A M-1 , each of reset switches R 1 to R M , and output switch S OUT .

FIG. 18 is a timing chart illustrating an example of the operation of the averaging circuit 1 according to the second embodiment. FIG. 18 illustrates by way of example the case where sampling switches S 1 to S 3 , averaging switches A 1 and A 2 and reset switches R 1 to R 3 are opened and closed, so that an average value of N (N=4) signal values is determined.

It should be noted that where N=8, an average value (first average value) of four signals is determined by opening and closing sampling switches S 1 to S 3 , averaging switches A 1 to A 3 and reset switches R 1 and R 2 , and an average value (second average value) of other four signals is determined by opening and closing sampling switches S 2 to S 4 , averaging switches A 2 to A 4 and reset switches R 2 and R 3 ; and an average value of the first average value and the second average value is further determined.

Also, where N=12 or more, 12 or more signals are divided into three or more groups, an average value of four signal values belonging to each of the three or more groups is determined, that is, average values of the three or more groups are successively determined; and an average value of the determined average values of the three or more groups is then determined.

The controller 3 operates in response to a clock signal CLK. The clock signal CLK repeatedly changes between high and low. This will be explained in detail as follows:

When first clock signal CLK 1 is high, the controller 3 closes (turns on) sampling switch S 2 . Thereby, voltage V 1 is applied to capacitor C 2 .

When second clock signal CLK 2 is high, the controller 3 closes sampling switch S 1 . Thereby, voltage V 2 is applied to capacitor C 1 .

When third clock signal CLK 3 is high, the controller 3 closes averaging switch A 1 and sampling switch S 3 . Thereby, voltage (V 1 +V 2 )/2 is applied to capacitors C 1 and C 2 , and voltage V 3 is applied to capacitor C 3 .

In a period between a period which third clock signal CLK 3 is high and a period in which fourth clock signal CLK 4 is high (when third clock signal CLK 3 becomes low), the controller 3 closes reset switch R 2 . Thereby, the voltage of capacitor C 2 is reset.

When fourth clock signal CLK 4 is high, the controller 3 closes sampling switch S 2 . Thereby, voltage V 4 is applied to capacitor C 2 .

When fifth clock signal CLK 5 is high, the controller 3 closes averaging switch A 2 . Thereby, voltage (V 3 +V 4 )/2 is applied to capacitors C 2 and C 3 .

In a period between a period in which fifth clock signal CLK 5 is high and a period in which sixth clock signal CLK 6 is high (when fifth clock signal CLK 5 becomes low), the controller 3 closes reset switch R 3 . Thereby, the voltage of capacitor C 3 is reset.

When sixth clock signal CLK 6 is high, the controller 3 closes averaging switch A 1 and output switch S OUT . Thereby, voltage (V 1 +V 2 +V 3 +V 4 )/4 is applied to capacitors C 2 and C 3 , and an output signal corresponding to voltage (V 1 +V 2 +V 3 +V 4 )/4 is output from output terminal O.

In a period between a period in which sixth clock signal CLK 6 is high and a period in which seventh clock signal CLK 7 is high (when sixth clock signal CLK 6 becomes low), the controller 3 closes reset switch R 2 . Thereby, the voltage of capacitor C 2 is reset.

An algorithm which is applied in the controller 3 according to the second embodiment will be explained.

k is a natural number which satisfies the formula 0<k≤N.

In the case where k=a 0 ·2 0 +a 1 ·2 1 + . . . +a P ·2 P (P is a natural number), X(k) is expressed by formula (1) below.

X ( k )=Σ q=0 P a q   (1)

For example, where k=5, if 5 is expressed in a binary number, it is 101. In this case, X(5) is 2.

First, sampling of voltage V k will be explained. It should be noted that in the second embodiment, it will be referred to as sampling that a voltage corresponding to an input signal is applied to a capacitor.

Where k is an odd number, the controller 3 closes X(k)+1 th sampling switch S X(k)+1 to apply voltage V k to X(k)+1 th capacitor C X(k)+1 .

Where k is an even number, the controller 3 closes X(k−1) th sampling switch S X(k−1) to apply voltage V k to X(k−1) th capacitor C X(k−1) .

Then, equalization will be explained.

The controller 3 performs first to third controls, which will be explained below, over averaging switches A 1 to A M-1 .

In the first control, in the case where k is a multiple of 2, after completion of k th sampling and before completion of k+1 th sampling, the controller 3 closes X(k−1) th averaging switch A X(k−1) to equalize voltages applied to X(k−1) th capacitor C X(k−1) and X(k−1)+1 th capacitor C X(k−1)+1 .

In the second control, in the case where k is a multiple of 4, before completion of k+1 th sampling, the controller 3 closes X(k−1)−1 th averaging switch A X(k−1)−1 , and equalizes voltages applied to X(k−1)−1 th capacitor C X(k−1)−1 and X(k−1) th capacitor C X(k−1) . The second control over an averaging switch is performed after the first control over the averaging switch.

In the third control, in the case where k is a multiple of an exponent of 2 (2 P ), before completion of sampling of k+1 th sampling, the controller 3 closes X(k−1)+1−P th averaging switch A X(k−1)+1−P , and equalizes voltages applied to X(k−1)+1−P th capacitor C X(k−1)+1−P and X(k−1)+2−P th capacitor C X(k−1)+2−P . The third control over an averaging switch is performed after the second control over the averaging switch. It should be noted that the above operation is performed on all values of P in the ascending order of the value of P.

For example, if an averaging switch satisfies execution conditions for execution of a plurality of controls which are included in the above first to third controls (for example, an execution condition in which k is 2 or 4), and the plurality of controls have the same processing content, only one of the controls is performed.

As described above, if an averaging switch satisfies execution conditions for execution of a plurality of controls which are included in the above first to third controls (for example, an execution condition in which k is 8 or 16), and the plurality of controls have different processing content, the third control is performed after the first and second controls.

Next, it will be explained how a capacitor is reset.

After the controller 3 closes X(k−1) th averaging switch A X(k−1) , before starting k+1 th sampling, the controller 3 closes X(k−1)+1 th reset switch R X(K−1)+1 to discharge capacitor C X(k−1)+1 .

After the above operation is completed, the controller 3 increments the value of k by 1, and also performs sampling of voltage V k+1 . When k becomes greater than N, the sampling is ended.

To be more specific, for example, if k is 16, it is a multiple of 2, and the execution condition for the above first control is thus satisfied. Also, since k is a multiple of 4, the execution condition for the second control is satisfied. In addition, since k is a multiple of 2 3 and 2 4 , and P=3 and 4, the execution condition for the third control is satisfied. Therefore, the first to third controls are successively performed in the following manner.

First, in the first control, averaging switch A 4 is closed to equalize the voltages applied to capacitors C 4 and C 5 .

Next, in the second control, averaging switch A 3 is closed to equalize the voltages applied to capacitors C 3 and C 4 .

Furthermore, in the third control, as a control to be performed in the case where P=3, averaging switch A 2 is closed to equalize the voltages applied to capacitors C 2 and C 3 . Subsequently, as a control to be performed in the case where P=4, averaging switch A 1 is closed to equalize the voltages applied to capacitor C 1 and C 2 .

After the operations of the above first to third controls, the controller 3 increments the value of k by 1, and performs sampling of voltage V 17 .

As described above, in the averaging circuit 1 according to the second embodiment, the circuit area can be effectively reduced as explained with respect to the first embodiment.

Third Embodiment

The third embodiment will be explained by referring to a modification of the averaging circuit according to each of the first and second embodiments. In the following, the explanations given above with reference to FIGS. 1 to 18 are not repeated.

FIG. 19 is a circuit diagram showing an example of a schematic configuration of an averaging circuit 1 A according to the third embodiment.

FIG. 20 is a circuit diagram showing an example of a detailed configuration of the averaging circuit 1 A according to the third embodiment.

The averaging circuit 1 A includes M sampling switches S 1 to S M and M capacitors C 1 to C M , M averaging switches A 1 to A M , M reset switches R 1 to R M , output switch S OUT and output capacitor C OUT .

In the third embodiment, sampling switches S 1 to S M , capacitors C 1 to C M and reset switches R 1 to R M are formed to have the same structures as those in the first embodiment and the second embodiment.

In the third embodiment, ends of averaging switches A 1 to A M are connected to ends of capacitors C 1 to C M , respectively. The other ends of averaging switches A 1 to A M are connected to one end of output switch S OUT . The other end of output switch S OUT is connected to one end of output capacitor C OUT and output terminal O. The other end of output capacitor C OUT is grounded.

When output switch S OUT is closed, output signal D 0 is output from output terminal O.

FIG. 21 is a timing chart showing an example of an operation of the averaging circuit 1 A according to the third embodiment. To be more specific, FIG. 21 shows by way of example the case where sampling switches S 1 to S 3 , averaging switches A 1 to A 3 and reset switches R 1 to R 3 are opened and closed, so that an average value of N signals (N=4) is determined.

It should be noted that where N=8, an average value (first average value) of four signals is determined by opening and closing sampling switches S 1 to S 3 , averaging switches A 1 to A 3 and reset switches R 1 to R 3 , and an average value (second average value) of other four signals is determined by opening and closing sampling switches S 2 to S 4 , averaging switches A 2 to A 4 and reset switches R 2 to R 4 ; and an average value of the first average value and the second average value is further determined.

Also, where N=12 or more, 12 or more signals are divided into three or more groups, an average value of four signal values belonging to each of the three or more groups is determined, that is, average values of the three or more groups are successively determined; and an average value of the determined average values of the three or more groups is then determined.

The controller 3 A operates in response to a clock signal CLK. The clock signal CLK repeatedly changes between high and low. This will be explained in detail as follows:

When first clock signal CLK 1 is high, the controller 3 A closes sampling switch S 2 . Thereby, voltage V 1 is applied to capacitor C 2 .

When second clock signal CLK 2 is high, the controller 3 A closes sampling switch S 1 . Thereby, voltage V 2 is applied to capacitor C 1 .

When third clock signal CLK 3 is high, the controller 3 A closes averaging switches A 1 and A 2 and sampling switch S 3 . Thereby, voltage (V 1 +V 2 )/2 is applied to capacitors C 1 and C 2 , and voltage V 3 is applied to capacitor C 3 .

In a period between a period which third clock signal CLK 3 is high and a period in which fourth clock signal CLK 4 is high (when third clock signal CLK 3 becomes low), the controller 3 A closes reset switch R 2 . Thereby, the voltage of capacitor C 2 is reset.

When fourth clock signal CLK 4 is high, the controller 3 A closes sampling switch S 2 . Thereby, voltage V 4 is applied to capacitor C 2 .

When fifth clock signal CLK 5 is high, the controller 3 A closes averaging switches A 2 and A 3 . Thereby, voltage (V 3 +V 4 )/2 is applied to capacitors C 2 and C 3 .

In a period between a period which fifth clock signal CLK 5 is high and a period in which sixth clock signal CLK 6 is high (when fifth clock signal CLK 5 becomes low), the controller 3 A closes reset switch R 3 . Thereby, the voltage of capacitor C 3 is reset.

When sixth clock signal CLK 6 is high, the controller 3 A closes averaging switches A 1 and A 2 and output switch S OUT . Thereby, voltage (V 1 +V 2 +V 3 +V 4 )/4 is applied to capacitors C 2 and C 3 , and an output signal corresponding to voltage (V 1 +V 2 +V 3 +V 4 )/4 is output from output terminal O.

In a period between a period which sixth clock signal CLK 6 is high and a period in which seventh clock signal CLK 7 is high (when sixth clock signal CLK 6 becomes low), the controller 3 A closes reset switch R 2 . Thereby, the voltage of capacitor C 2 is reset.

An algorithm which is applied in the controller 3 A according to the third embodiment will be explained.

k, P and X(k) are the same as those in the second embodiment.

Sampling of voltage V k is also the same as in the second embodiment.

Next, equalization will be explained.

The controller 3 A performs first to third controls, which will be explained below, over averaging switches A 1 to A M .

In the first control, in the case where k is a multiple of 2, after completion of k th sampling and before completion of k+1 th sampling, the controller 3 A closes X(k−1) th averaging switch A X(k−1) and X(k−1)+1 th averaging switch A X(k−1)+1 to equalize the voltages applied to X(k−1) th capacitor C X(k−1) and X(k−1)+1 th capacitor C X(k−1)+1 .

In the second control, in the case where k is a multiple of 4, before completion of k+1 th sampling, the controller 3 A closes X(k−1)−1 th averaging switch A X(k−1)−1 and X(k−1) th averaging switch A X(k−1) to equalize the voltages applied to X(k−1)−1 th capacitor C X(k−1)−1 and X(k−1) th capacitor C X(k−1) . The second control over an averaging switch is performed after the first control over the averaging switch.

In the third control, in the case where k is a multiple of an exponent of 2 (2 P ), before completion of sampling of k+1 th sampling, the controller 3 A closes X(k−1)+1−P th averaging switch A X(k−1)+1−P and X(k−1)+2−P th averaging switch A X(k−1)+2−P to equalize voltages applied to X(k−1)+1−P th capacitor C X(k−1)+1−P and X(k−1)+2−P th capacitor C X(k−1)+2−P . The third control over an averaging switch is performed after the second control over the averaging switch. It should be noted that the above operation is performed on all values of P in the ascending order of the value of P.

It should be noted that in the third embodiment, if an averaging switch satisfies execution conditions for execution of a plurality of controls which are included in the above first to third controls, and the plurality of controls have the same processing content, only one of the controls is performed as in the second embodiment.

Next, it will be explained how a capacitor is reset.

After the controller 3 A closes X(k−1) th averaging switch A X(k−1) , before starting k+1 th sampling, the controller 3 A closes X(k−1)+1 th reset switch R X(K−1)+1 to discharge capacitor C X(k−1)+1 .

After completion of the above operation, the controller 3 A increments the value of k by 1, and also performs sampling of voltage V k+1 . When k becomes greater than N, the sampling is ended.

In the averaging circuit 1 A as explained above, the circuit area can be effectively reduced as in the first and second embodiments.

Furthermore, in the third embodiment, M averaging switches A 1 to A M are assigned to M capacitors C 1 to C M , respectively. Thereby, a single set of switches, i.e., a reset switch, a sampling switch and an averaging switch, are assigned to a single capacitor, thus clarifying the relationship between circuit elements.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.