Inventor
Takayasu Sakurai
Inventor
Tokyo, JP
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores38%
H03KPulse technique18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G06FElectric digital data processing4%
H10DInorganic electric semiconductor devices4%
G01RMeasuring electric variables3%
G05FSystems for regulating electric or magnetic variables3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
A61BDiagnosis1%
A61FFilters implantable into blood vessels1%
PatentTitleYear
10,413,247Signal detection device, signal detection method, and method of manufacturing signal detection device201910,177,750Averaging circuit which determines average voltage of N samples, using log201910,116,261Oscillator circuit20189,276,589'Signal transmission circuit'20169,036,443'Integrated circuit device'20159,000,751'Voltage detecting circuit'20158,742,838'Stacked structure with a voltage boosting supply circuit'20148,618,870'Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit'20138,514,013'Integrated circuit device having a plurality of integrated circuit chips and an interposer'20137,768,790'Electronic circuit'20107,266,035'Self-aligned row-by-row dynamic VDD SRAM'20077,088,084'Power supply circuit capable of rapidly changing output voltages'20066,529,042'Semiconductor integrated circuit'20036,215,159'Semiconductor integrated circuit device'20016,037,805'Integrated circuit device having small amplitude signal transmission'20005,933,029'Semiconductor integrated circuit device comprising a bias circuit, a driver circuit, and a receiver circuit'19995,673,214'Discrete cosine transform processor'19975,596,520'CMOS full adder circuit with pair of carry signal lines'19975,539,331'Field programmable gate array having transmission gates and semiconductor integrated circuit for programming connection of wires'19965,459,342'Field programmable gate array with spare circuit block'19955,434,517'ECL output buffer with a MOS transistor used for tristate enable'19955,294,911'Data comparator'19945,258,957'Semiconductor memory device'19935,153,699'Semiconductor device'19924,984,208'Dynamic read/write memory with improved refreshing operation'19914,974,203'Arrangement and construction of an output control circuit in a semiconductor memory device'19904,958,326'Semiconductor memory device having a function of simultaneously clearing part of memory data'19904,939,695'Virtual type static semiconductor memory device including refresh detector circuitry'19904,905,192'Semiconductor memory cell'19904,866,677'Semiconductor memory device with multiple alternating decoders coupled to each word line'19894,857,763'MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased'19894,853,897'Complementary semiconductor memory device'19894,853,654'MOS semiconductor circuit'19894,827,453'Semiconductor memory control circuit'19894,812,735'Intermediate potential generating circuit'19894,769,792'Semiconductor memory device with voltage bootstrap'19884,764,901'Semiconductor memory device capable of being accessed before completion of data output'19884,757,217'Refresh operation control circuit for semiconductor device'19884,744,063'Static memory utilizing transition detectors to reduce power consumption'19884,740,713'MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased'19884,683,382'Power-saving voltage supply'19874,682,306'Self-refresh control circuit for dynamic semiconductor memory device'19874,677,592'Dynamic RAM'19874,618,945'Semiconductor memory device'19864,592,026'Memory device resistant to soft errors'19864,587,638'Semiconductor memory device'19864,555,778'Semiconductor memory device'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–2019Patents assigned to TOSHIBA KK (33)· patent assignee history
1985–2019Based in Tokyo, JP· patent location history
1995–2007Based in Setagaya, JP· patent location history
2003–2015Patents assigned to UNIV TOKYO (4)· patent assignee history
2013–2015Patents assigned to SAKURAI TAKAYASU (5)· patent assignee history
2013–2015Patents assigned to TAKAMIYA MAKOTO (4)· patent assignee history
2013–2015Patents assigned to ISHIDA KOICHI (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOSHIBA KK | 33 | 1985–2019 |
| SAKURAI TAKAYASUself | 5 | 2013–2015 |
| TAKAMIYA MAKOTO | 4 | 2013–2015 |
| UNIV TOKYO | 4 | 2003–2015 |
| ISHIDA KOICHI | 3 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 38 | 1985–2019 |
| Setagaya, JP | 9 | 1995–2007 |