Semiconductor device and a method for fabricating the same

The disclosure relates to a method for manufacturing a semiconductor device, and more particularly to field effect transistor (FETs) having different gate dielectric thicknesses and a manufacturing method therefor.

Some semiconductor device such as an embedded flash memory, a high-voltage FET, and bipolar-CMOS-DMOS devices require formation of multiple gate dielectric (gate oxide) layers having different thicknesses. The process for manufacturing multiple gate dielectric (gate oxide) layers includes multiple formations of gate dielectric layers and removal of at least one formed gate dielectric layer. A process that does not affect FET properties has been requested.

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A-7D shows exemplary plan views (viewed from the above) and cross sectional views illustrating various stages of the sequential fabrication process of a semiconductor device according to one embodiment of the present disclosure.

FIGS. 8-10 show exemplary plan views illustrating various stages of the sequential fabrication process of a semiconductor device according to another embodiment of the present disclosure.

FIGS. 11A-12B show exemplary plan views and cross sectional views illustrating various stages of the sequential fabrication process of a semiconductor device according to another embodiment of the present disclosure.

FIGS. 13A and 13B show exemplary plan views (viewed from the above) illustrating one of the various stages of the sequential fabrication process of a semiconductor device according to another embodiment of the present disclosure.

FIG. 14 shows an exemplary cross sectional view of a semiconductor device.

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comp rising” or “consisting of.”

FIGS. 1A-7D show exemplary plan views (viewed from the above) and cross sectional views illustrating various stages of the sequential fabrication process of a semiconductor device according to one embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown by FIGS. 1A-7D , and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG. 1A, 2A , . . . 7 A show plan (top) views and FIGS. 1B, 2B , . . . 7 B show cross sectional views along line X 1 -X 1 of FIGS. 1A, 2A , . . . 7 A, respectively.

In one embodiment of the present disclosure, the semiconductor device includes a first FET formed in a region A and a second FET formed in a region B, as shown in FIGS. 1A and 1B . The regions A and B may be adjacent to each other or may be separated by one or more elements of the semiconductor device. In some embodiments, a gate dielectric layer of the first FET is thicker than a gate dielectric layer of the second FET, and thus a threshold voltage of the first FET is higher than that of the second FET.

FIGS. 1A and 1B show a structure after isolation regions 20 A and 20 B are formed in a substrate 10 . The isolation regions (first isolation region 20 A and second isolation region 20 B) are also called shallow trench isolation (STI).

The isolation regions 20 A and 20 B are formed by trench etching the substrate 10 and filling the trenches with an insulating material. The isolation regions are made of, for example, one or more layers of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials instead of silicon oxide are deposited. Flowable dielectric materials, as their name suggest, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks. In some embodiments, multiple anneal processes are conducted. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and/or phosphorous. The isolation regions may be formed by one or more layers of SOG, SiO, SiON, SiOCN and/or fluorine-doped silicate glass (FSG) in some embodiments.

The substrate 10 is silicon substrate in one embodiment, and is appropriately doped. The substrate 10 may comprise another elementary semiconductor, such as germanium; a compound semiconductor including Group IV-IV compound semiconductors such as SiC and SiGe, III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

Portions of the substrate surrounded by the isolation regions 20 A and 20 B are referred to as active regions 15 A and 15 B, respectively, in which a channel, a source and a drain of an FET are formed.

In FIGS. 2A and 2B , a first dielectric layer 30 A is formed over the first active region 15 A and a second dielectric layer 30 B is formed over the second active region 15 B. The first and second dielectric layers are formed at the same time. In one embodiment, the first and second dielectric layers are silicon dioxide which is formed by thermal oxidation. In other embodiments, the first and second dielectric layers are silicon oxide, silicon nitride and/or silicon oxynitride formed by chemical vapor deposition (CVD). A thickness of the first and second dielectric layers is in a range from about 1 nm to about 200 nm in some embodiments.

In FIGS. 3A and 3B , a mask layer is formed over the regions A and B. The mask layer is a photo resist pattern formed by a lithography operation. The masks layer includes a first mask layer 40 A formed in the region A and a second mask layer 40 B formed in the region B. The first mask layer 40 A is formed over the first active region 15 A to entirely cover the first active region 15 A and to cover a portion of the isolation region 20 A surrounding the first active region 15 A. The second mask layer 40 B is formed on at least a part of a border line BL between the isolation region 20 B and the second active region 15 B. The second mask layer 40 B covers a part, but not the entirety, of the second dielectric layer 30 B formed on the second active region 15 B and covers a part of the isolation region 20 B surrounding the second active region 15 B.

As shown in the later figures, a gate electrode extends in the X direction of the figures. The second mask layer 40 B covers at least parts of the border line BL extending in the Y direction, as shown in FIG. 3A . The dimension L 1 of the second mask layer 40 B in the Y direction is equal to or greater than a dimension of the gate electrode in the Y direction. In some embodiments, L 1 is 1 to 2 times the dimension of the gate electrode in the Y direction. In certain embodiments, the dimension L 1 of the second mask layer 40 B in the Y direction is smaller than the dimension of the gate electrode in the Y direction

Further, as shown in FIG. 3A , an area of the second mask layer 40 B that covers the isolation region 20 B is greater than an area of the mask layer 40 B that covers the second dielectric layer 30 B formed on the active region 15 B. In other words, when the second mask layer 40 B has a rectangular shape (L 1 ×W 1 ), the length D 1 of the second mask layer over the second isolation region 20 B is greater than the length D 2 of the second mask layer over the second dielectric layer 30 B, as shown in FIG. 3A . In some embodiments, D 1 +D 2 is set equal to or a slightly greater than an alignment margin allowed in the lithography operation for forming the mask layer. It is noted that D 2 may vary depending on the lateral etching bias in the following removal of dielectric layer 30 B.

Although in FIGS. 3A and 3B , the region A is entirely covered by the mask layer 40 A. However, the isolation region 20 A may partially be exposed from the mask layer 40 A.

As shown in FIGS. 4A and 4B , the second dielectric layer 30 B not covered by the mask layer 40 B is removed by using, for example, wet etching and/or dry etching. In one embodiment, wet etching with buffered HF or dilute HF is used. As shown in FIG. 4B , the second active region 15 B not covered by the mask layer 40 B is exposed. Parts of the second dielectric layer 30 B located under the mask layer 40 B are partially etched but some parts remain under the mask layer 40 B as shown in FIG. 4B .

Further, as shown in FIG. 4B , the isolation region 20 B not covered by the mask layer 40 B is also etched to form a divot or a recess 25 B. The isolation region 20 B covered by the mask layer 40 B is not etched. The first dielectric layer 30 A and the isolation region 20 A in the region A are not etched.

After the etching, the mask layers 40 A and 40 B are removed by, for example, ashing and cleaning operations, as shown in FIGS. 5A and 5B . Here, a bottom of the divot 25 B formed in the isolation region 20 B is located below a level of the interface between the second dielectric layer 30 B and the active region 15 B because an etching rate for the isolation region 20 B is greater than an etching rate for the second dielectric layer 30 B in the etching operation. In some embodiments, a depth of the divot 25 B is in a range of about 1 nm to about 100 nm.

Subsequently, an additional dielectric layer is formed over the first region A and the second region B, thereby forming a first gate dielectric layer 35 A and a second gate dielectric layer 35 B, as shown in FIGS. 6A and 6B . In one embodiment, the additional dielectric layer is silicon dioxide which is formed by thermal oxidation. In other embodiments, the additional dielectric layer is silicon oxide, silicon nitride and/or silicon oxynitride formed by chemical vapor deposition (CVD).

As shown in FIGS. 6A and 6B , by the additional thermal oxidation, the thickness of the first gate dielectric layer 35 A can be formed thicker than the first dielectric layer 30 A. Further, in the second region B, the exposed surface of the second active region 15 B is oxidized, thereby forming the second gate dielectric layer 35 B. Since parts of the second dielectric layer 30 B remain at the edge of the second active region 15 B, the second gate dielectric layer 35 B includes a first region 35 B- 1 and a second region 35 B- 2 having a thickness greater than the first region 35 B- 1 . The thickness of the first region 35 B- 1 is in a range from about 1 nm to about 150 nm in some embodiments. The thickness of the second region 35 B- 2 and the thickness of the first gate dielectric layer 35 A are substantially the same and are in a range from about 2 nm to about 200 nm, in some embodiments.

After the gate dielectric layers are formed, a first gate electrode 50 A and a second gate electrode 50 B are formed as shown in FIGS. 7A and 7B . As shown in FIG. 7A , the first and second gate electrodes extend in the X direction. Of course, at least one of the first and second gate electrodes may extend in the Y direction. The first and second gate electrodes are made of a conductive material, such as a polysilicon and a metal material, and formed by a film deposition operation, a lithography operation and an etching operation.

As set forth above, a width L 2 of the second gate electrode 50 B is equal to or less than the dimension L 1 of the second mask layer 40 B (see, FIG. 3B ).

Further, as shown in FIG. 7B , the divot 25 B is filled with the material (e.g., polysilicon) of the second gate electrode 50 B. The filled divot is physically separated and located away from the border line (the closest border line) BL between the isolation region 20 B and the second active region 15 B. The filled divot is not in contact with the second gate dielectric layer 35 B at the level of the interface between the second gate electrode 50 B and the second gate dielectric layer 35 B. A distance D 3 between the edge of the filled divot (closest to the border line BL) and the border line BL is equal to or more than about 5 nm. The upper limit of D 3 depends on the circuit design and may range from the order of 100 nm to the order of micro meters, e.g., 5 μm.

FIGS. 7C and 7D are cross sectional views along line Y 1 -Y 1 and Y 2 -Y 2 of FIG. 7A , respectively. Along the Y direction, divots (recesses) 26 B are formed in the isolation region 20 B. As shown in FIG. 7C , the width of the second region 35 B- 2 along the Y direction is equal to or greater than the width of the second gate electrode 50 B.

FIGS. 8-10 show exemplary plan views illustrating various stages of the sequential fabrication process of a semiconductor device according to another embodiment of the present disclosure. FIGS. 8-10 show CMOS inverter layouts. The same or similar configurations, operations, processes and/or material as those explained with FIGS. 1A-7D are employed in this embodiment, and the detailed explanation thereof may be omitted.

As shown in FIG. 8 , an inverter is formed in a high voltage region C and an inverter is also formed in a low voltage region D. Each of the high and low voltage regions includes a PMOS region and an NMOS region. The PMOS region includes an N-Well and a P+ region and the NMOS region includes a P-Well (not shown) and an N+ region. The PMOS region may also include a N+ region for a substrate contact, and the NMOS region may also include a P+ region for a substrate contact.

Active regions 15 C and 15 E, surrounded by isolation region 20 C, are formed in the PMOS and NMOS regions, respectively, in the high voltage region C, and active regions 15 D and 15 F, surrounded by isolation region 20 D, are formed in the PMOS and NMOS regions, respectively, in the low voltage region D. Further, dielectric layers 30 C and 30 D are formed in the active regions.

As shown in FIG. 9 , the high voltage region C is covered by a mask layer 40 C. In the low voltage region D, similar to FIG. 3A , parts of border lines between the active regions and the isolation region 20 D are covered by mask layer 40 D as shown in FIG. 9 .

After the similar operations as those for FIGS. 4A-7D , gate electrodes 50 C and 50 D are formed, as shown in FIG. 10 .

FIG. 11A-12B shows exemplary plan views and cross sectional views illustrating various stages of the sequential fabrication process of a semiconductor device according to another embodiment of the present disclosure. The same or similar configurations, operations, processes and/or material as those explained with FIGS. 1A-10 are employed in this embodiment, and the detailed explanation thereof may be omitted. FIGS. 11A-12B illustrate the manufacturing operations in the second region B.

In FIGS. 3A and 3B , the second mask layer 40 B is formed on only a part of a border line BL between the isolation region 20 B and the second active region 15 B. In this embodiment, the second mask layer 40 E is formed to cover the entire border line BL, as shown in FIGS. 11A and 11B . Further, the second mask layer 40 E covers the entire isolation region 20 B. In other words, the mask layer 40 E has an opening only over the second dielectric layer 35 B in the second active region 15 B, and the size of the opening is slightly smaller than the second active region 15 B.

After the similar operations explained with respect to FIGS. 4A-7D , the second gate electrode 50 B is formed over the second gate dielectric layer 35 B, as shown in FIGS. 12A and 12B . With the second mask layer 40 E of this embodiment, it is possible to eliminate any divot formed in the isolation region.

FIGS. 13A and 13B show exemplary plan views (viewed from the above) illustrating one of the various stages of the sequential fabrication process of a semiconductor device according to another embodiment of the present disclosure.

In FIG. 13A , the second mask layer 40 F is formed to cover the entire border lines in Y direction. The length of the second mask layer 40 F in the Y direction is substantially the same as the length of the active region 15 B in the Y direction. With this mask layer 40 F, the similar structure as shown in FIG. 12B can be obtained.

In FIG. 13B , the second mask layer 40 G is formed to cover the entire border lines in Y direction, and the length of the second mask layer 40 G in the Y direction is longer than the length of the active region 15 B in the Y direction. With this mask layer 40 G, the similar structure as shown in FIG. 12B can be obtained.

FIG. 14 shows a comparative example of an FET structure. Unlike the present embodiments, the second mask layer is not used in this example. If the second mask layers are not used and the portion of the isolation insulating layer surrounding the second active region 15 B is also etched, the resultant FET has a structure shown in FIG. 14 . In this case, the divot 25 filled with a material of the gate electrode 50 is formed in the isolation region 20 and is in contact with the gate dielectric layer 30 or is located very close to the gate dielectric layer 30 . In such a case, a high electric field may be caused at around the active region and the gate electrode edge. As a result, a threshold voltage of corner devices near the isolation region may be decreased and may further lead to a double hump effect, which makes it difficult to determine a threshold voltage in curve fitting of a device simulation.

In contrast, as set forth above, in the present disclosure, in manufacturing an FET having relatively thinner gate dielectric layer, at least parts of the border line (and adjacent regions) along the Y direction (perpendicular to the X direction in which the second gate electrode extends) between the second isolation region 20 B and the second active region 15 B are covered by a second mask layer ( 40 B and 40 D- 40 G), and the first dielectric layer 35 B exposed from the second mask layer is etched. Since at least a portion of the second isolation region adjacent to the border line BL is covered by the second mask layer, the portion of the second isolation region over which a second gate electrode is to be formed is not etched during the etching of the first dielectric layer 35 B.

Accordingly, even if the second isolation region is etched to cause a divot, the location of the divot can be set away from the border line BL. Thus, it is possible to suppress a high electric field which would otherwise be caused at around the active region and the gate electrode edge, and to stabilize a threshold voltage of the FET across the semiconductor device. Moreover, it is possible to more precisely determine a threshold voltage in curve fitting of the device simulation.

It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages.

According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, an isolation region is formed in a substrate such that the isolation region surrounds an active region of the substrate in plan view. The isolation region includes an insulating material. A first dielectric layer is formed over the active region. A mask layer is formed on at least a part of a border line between the isolation region and the active region. The mask layer covers a part, but not entirety, of the first dielectric layer and a part of the isolation region surrounding the active region. The first dielectric layer not covered by the mask layer is removed such that a part of the active region is exposed. After the first dielectric layer is removed, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. A gate electrode is formed over the gate dielectric layer.

According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device including a first field effect transistor (FET) and a second FET, an isolation region is formed in a substrate such that the isolation region surrounds a first active region of the substrate for the first FET and a second active region of the substrate for the second FET in plan view. The isolation region includes an insulating material. A first dielectric layer is formed over the first and second active regions. A first mask layer is formed over the first active region to entirely cover the first active region and to cover a portion of the isolation region surrounding the first active region, and a second mask layer is formed on at least a part of a border line between the isolation region and the second active region, the second mask layer covering a part, but not entirety, of the first dielectric layer formed on the second active region and a part of the isolation region surrounding the second active region. The first dielectric layer formed on the second active region not covered by the second mask layer is removed such that a part of the second active region is exposed. The first and second mask layers are removed. After the first and second mask layers are removed, a second dielectric layer is formed so that a first gate dielectric layer for the first FET and a second gate dielectric layer for the second FET are formed. A first gate electrode is formed over the first gate dielectric layer for the first FET and a second gate electrode is formed over the second gate dielectric layer for the second FET.

In accordance with yet another aspect of the present disclosure, a semiconductor device includes an active region including a channel, a source and a drain, an isolation region surrounding the active region, a gate dielectric layer disposed on the channel, and a gate electrode disposed over the channel. The gate dielectric layer includes a first region and a second region having a thickness greater than the first region, and the second region is in contact with the isolation region.

The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.