Driving circuit

The invention relates to a driving circuit, and more particularly to a driving circuit with an electrostatic discharge (ESD) protection function.

Generally, every semiconductor integrated circuit comprises a plurality of input/output pads and controls at least one external element via the input/output pads. For example, the external element may be activated according to the voltage level of an input/output pad. However, when an electrostatic discharge (ESD) event occurs at the input/output pad, an ESD current may pass through the integrated circuit or the external element.

In accordance with an embodiment, a driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller so that the controller turns on the release control element to release ESD currents. When the ESD event does not occur at the power terminal and the input/output pad, the detector does not activate the controller and the release control element is turned on according to a control signal to control the voltage level of the input/output pad.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a block diagram of a driving circuit, according to various aspects of the present disclosure;

FIGS. 2A-2B are schematic diagrams of exemplary embodiments of the driving circuit, according to various aspects of the present disclosure;

FIGS. 3A-3C are schematic diagrams of exemplary embodiments of the driving circuit, according to various aspects of the present disclosure;

FIGS. 4A-4B are schematic diagrams of exemplary embodiments of the driving circuit, according to various aspects of the present disclosure; and

FIGS. 5A-5C are schematic diagrams of exemplary embodiments of the driving circuit, according to various aspects of the present disclosure.

The following description is the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 is a block diagram of a driving circuit, according to various aspects of the present disclosure. The driving circuit 100 comprises a detector 110 , a controller 120 , and a release control element 130 . In this embodiment, the driving circuit 100 is capable of controlling the voltage level of an input/output pad (I/O pad) 150 and has an ESD protection function to release an ESD current from the power terminal 140 or the input/output pad 150 .

The detector 110 is coupled to the power terminal 140 and the input/output pad 150 . The detector 110 detects whether an ESD event occurs at the power terminal 140 or the input/output pad 150 and generates a detection signal S D and a trigger signal S T . Either the detection signal S D or the trigger signal S T is utilized to activate the controller 120 . For example, when an ESD event occurs at the power terminal 140 or the input/output pad 150 , the detector 110 utilizes the detection signal S D or the trigger signal S T to activate the controller 120 . When no ESD event occurs at the power terminal 140 or the input/output pad 150 , the detector 110 utilizes the detection signal S D or the trigger signal S T to de-activate the controller 120 .

The controller 120 is coupled to the detector 110 and generates a control signal S C1 according to the detection signal S D and the trigger signal S T . In one embodiment, when the controller 120 is activated by the detection signal S D , the controller 120 asserts the control signal S C1 according to the trigger signal S T . In this case, the controller 120 uses the trigger signal S T as the control signal S C1 . In another embodiment, when the controller 120 is activated by the trigger signal S T , the controller 120 asserts the control signal S C1 according to the detection signal S D . In this case, the controller 120 uses the detection signal S D as the control signal S C1 .

The release control element 130 is coupled to the power terminal 140 or the input/output pad 150 and coupled to the controller 120 . In one embodiment, when the control signal S C1 is asserted, it means that an ESD event occurs at the power terminal 140 or at the input/output pad 150 . Therefore, the controller 120 turns on the release control element 130 to release an ESD current from the power terminal 140 or from the input/output pad 150 . However, when the control signal S C1 is not asserted, it means that no ESD event occurs at the power terminal 140 or the input/output pad 150 . At this time, the release control element 130 operates according to a control signal S C2 . For example, when the voltage level of the control signal S C2 is at a pre-determined level, the release control element 130 is turned on to control the voltage level of the input/output pad 150 . At this time, the release control element 130 serves as a buffer. When the voltage level of the control signal S C2 is not at the pre-determined level, the release control element 130 is turned off.

FIG. 2A is a schematic diagram of an exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. The detector 110 comprises a resistor R 11 , a capacitor C 11 , a P-type transistor P 11 , and an N-type transistor N 11 . The resistor R 11 is coupled between the power terminal 140 and a node 111 . The capacitor C 11 is coupled between the node 111 and a ground terminal GND. In this embodiment, the resistor R 11 and the capacitor C 11 are configured to detect whether an ESD event occurs at the power terminal 140 or at the input/output pad 150 and to generate the detection signal S D .

The gate of the P-type transistor P 11 is coupled to the node 111 . The source of the P-type transistor P 11 is coupled to the input/output pad 150 . The drain of the P-type transistor P 11 is coupled to the controller 120 . The gate of the N-type transistor N 11 is coupled to the node 111 . The source of the N-type transistor N 11 is coupled to the ground terminal GND. The drain of the N-type transistor N 11 is coupled to the drain of the P-type transistor P 11 . In this embodiment, the P-type transistor P 11 and the N-type transistor N 11 constitute an inverter and generate the trigger signal S T according to the detection signal S D .

The controller 120 is a P-type transistor P 12 . The gate of the P-type transistor P 12 is coupled to the node 111 to receive the detection signal S D . The source of the P-type transistor P 12 is coupled to the drain of the P-type transistor P 11 . The drain of the P-type transistor P 12 is coupled to the release control element 130 . The release control element 130 is an N-type transistor N 12 . The gate of the N-type transistor N 12 is coupled to the drain of the P-type transistor P 12 . The source of the N-type transistor N 12 is coupled to the ground terminal GND. The drain of the N-type transistor N 12 is coupled to the input/output pad 150 .

When a positive ESD event occurs at the input/output pad 150 and the power terminal 140 is coupled to ground, the driving circuit 200 A operates in a protection mode. In the protection mode, the voltage level of the node 111 is at a low voltage level due the capacitive coupling of the capacitor C 11 . Since the voltage level of the detection signal S D is at the low voltage level, the P-type transistor P 11 is turned on so that the voltage level of the trigger signal S T is at a high voltage level. At this time, since the P-type transistor P 12 is also turned on, the voltage level of the control signal S C1 is at the high voltage level. Therefore, the N-type transistor N 12 is turned on. When the N-type transistor N 12 is turned on, an ESD current is released from the input/output pad 150 to the ground terminal GND.

However, when no ESD event occurs at the input/output pad 150 or at the power terminal 140 , the driving circuit 200 A operates in a normal mode. In the normal mode, the power terminal 140 receives a high operation voltage (e.g. 3.3V), and the ground terminal GND receives a low operation voltage (e.g. 0V). Therefore, the voltage level of the node 111 is at the high voltage level. Since the voltage level of the detection signal S D is at the high voltage level, the N-type transistor N 11 is turned on, and the P-type transistor P 12 is turned off. At this time, the N-type transistor N 12 operates according to the control signal S C2 . In one embodiment, when the control signal S C2 is at a high voltage level, the N-type transistor N 12 is turned on to set the voltage level of the input/output pad 150 at a low voltage level. In another embodiment, when the voltage level of the control signal S C2 is at a low voltage level, the N-type transistor N 12 is turned off to stop setting the voltage level of the input/output pad 150 .

FIG. 2B is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. FIG. 2B is similar to FIG. 2A except the addition of a transmission gate 210 . Since the operations of the detector 110 , the controller 120 , and the release control element 130 shown in FIG. 2B are the same as the operations of the detector 110 , the controller 120 , and the release control element 130 shown in FIG. 2A , descriptions of the operations of the detector 110 , the controller 120 , and the release control element 130 shown in FIG. 2B are omitted for brevity.

In this embodiment, the transmission gate 210 transmits the control signal S C2 to the N-type transistor N 12 according to the voltage level (e.g. the detection signal S D ) of the node 111 . In one embodiment, the control signal S C2 is provided by an external element (not shown). The N-type transistor N 12 controls the voltage level of the input/output pad 150 according to the control signal S C2 . As shown in FIG. 2B , the transmission gate 210 comprises a P-type transistor P 13 , an N-type transistor N 13 , and an inverter INV 1 .

The source of the P-type transistor P 13 receives the control signal S C2 . The drain of the P-type transistor P 13 is coupled to the gate of the N-type transistor N 12 . The gate of the N-type transistor N 13 is coupled to the node 111 to receive the detection signal S D . The source of the N-type transistor N 13 is coupled to the drain of the P-type transistor P 13 . The drain of the N-type transistor N 13 receives the control signal S C2 . The input terminal of the inverter INV 1 is coupled to the gate of the N-type transistor N 13 . The output terminal of the inverter INV 1 is coupled to the gate of the P-type transistor P 13 .

When the voltage level of the detection signal S D is at the low voltage level, it represents that a positive ESD event occurs with grounding GND. Therefore, the P-type transistor P 13 and the N-type transistor N 13 are turned off In this case, the transmission gate 210 resists an ESD current into other elements, such as the element which generates the control signal S C . However, when the voltage level of the detection signal S D is at the high voltage level, it means that there has been no ESD event. Therefore, the P-type transistor P 13 and the N-type transistor N 13 are turned on to provide the control signal S C2 to the gate of the N-type transistor N 12 . At this time, the N-type transistor N 12 operates according to the control signal S C2 .

FIG. 3A is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. In this embodiment, the detector 110 comprises a capacitor C 21 , a resistor R 21 , a P-type transistor P 21 , and an N-type transistor N 21 . The capacitor C 21 is coupled between the power terminal 140 and the node 111 . The resistor R 21 is coupled to the node 111 and the ground terminal GND. The capacitor C 21 and the resistor R 21 are configured to detect whether an ESD event occurs at the power terminal 140 and generate the detection signal S D at the node 111 .

The gate of the P-type transistor P 21 is coupled to the node 111 . The source of the P-type transistor P 21 is coupled to the power terminal 140 . The drain of the P-type transistor P 21 is coupled to the controller 120 . The gate of the N-type transistor N 21 is coupled to the node 111 . The source of the N-type transistor N 21 is coupled to the ground terminal GND. The drain of the N-type transistor N 21 is coupled to the drain of the P-type transistor P 21 . In this embodiment, the P-type transistor P 21 and the N-type transistor N 21 constitute an inverter and generate the trigger signal S T according to the detection signal S D .

The controller 120 is an N-type transistor N 22 . The gate of the N-type transistor N 22 is coupled to the node 111 to receive the detection signal S D . The source of the N-type transistor N 22 is coupled to the release control element 130 . The drain of the N-type transistor N 22 is coupled to the drain of the P-type transistor P 21 to receive the trigger signal S T . The release control element 130 is a P-type transistor P 22 . The gate of the P-type transistor P 22 is coupled to the source of the N-type transistor N 22 . The source of the P-type transistor P 22 is coupled to the power terminal 140 . The drain of the P-type transistor P 22 is coupled to the input/output pad 150 .

When a positive ESD event occurs at the power terminal 140 and the input/output pad 150 is coupled to ground, the driving circuit 300 A enters a protection mode. In the protection mode, the voltage level of the detection signal S D is at the high voltage level. Therefore, the N-type transistors N 21 and N 22 are turned on so that the voltage level of the trigger signal S T and the control signal S C1 are at the low voltage level. Therefore, the P-type transistor P 22 is turned on to release an ESD current from the power terminal 140 to the input/output pad 150 .

When no ESD event occurs at the power terminal 140 and the input/output pad 150 is grounded, and the power terminal 140 receives a high operation voltage, and the ground terminal GND receives a low operation voltage, the driving circuit 300 A enters a normal mode. In the normal mode, the voltage level of the detection signal S D is at the low voltage level. Therefore, the P-type transistor P 21 is turned on, and the N-type transistor N 22 is turned off. Since the N-type transistor N 22 is turned off, the P-type transistor P 22 operates according to the control signal S C2 . In one embodiment, when voltage level of the control signal S C2 is at a low voltage level, the P-type transistor P 22 is turned on to set the voltage level of the input/output pad 150 at a high voltage level.

FIG. 3B is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. FIG. 3B is similar to FIG. 3A except that the driving circuit 300 B shown in FIG. 3B further comprises a capacitor C 22 . The capacitor C 22 is coupled between the input/output pad 150 and the ground terminal GND to avoid the voltage level of the ground terminal GND at a floating level. In this case, when the driving circuit 300 B operates in a protection mode, since the input/output pad 150 is grounded, the voltage level of the ground terminal GND is at a ground level due to the capacitive coupling of the capacitor C 22 . Since FIGS. 3A and 3B have the same principles, a description of FIG. 3B is omitted for brevity.

FIG. 3C is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. FIG. 3C is similar to FIG. 3A with the exception that the driving circuit 300 C shown in FIG. 3C further comprises a transmission gate 310 . The transmission gate 310 transmits the control signal S C2 to the P-type transistor P 22 according to the voltage level (e.g. the trigger signal S T ) of the drain of the P-type transistor P 21 . Then, the P-type transistor P 22 controls the voltage level of the input/output pad 150 according to the control signal S C2 .

In this embodiment, the transmission gate 310 comprises a P-type transistor P 23 , an N-type transistor N 23 , and an inverter INV 2 . The gate of the P-type transistor P 23 is coupled to the output terminal of the inverter INV 2 . The source of the P-type transistor P 23 receives the control signal S C2 . The drain of the P-type transistor P 23 is coupled to the gate of the P-type transistor P 22 . The gate of the N-type transistor N 23 is coupled to the drain of the P-type transistor P 21 to receive the trigger signal S T . The source of the N-type transistor N 23 is coupled to the drain of the P-type transistor P 23 . The drain of the N-type transistor N 23 receives the control signal S C2 . The input terminal of the inverter INV 2 is coupled to the gate of the N-type transistor N 23 .

When the driving circuit 300 C operates in a normal mode (no ESD event), the voltage level of the trigger signal S T is at a high voltage level. Therefore, the P-type transistor P 23 and the N-type transistor N 23 are turned on to provide the control signal S C2 to the gate of the P-type transistor P 22 . When the voltage level of the control signal S C2 is at a low voltage level, since the P-type transistor P 22 is turned on, the voltage level of the input/output pad 150 is at the high voltage level. Since the operations of the detector 110 , the controller 120 , and the release control element 130 shown in FIG. 3C are the same as the operations of the detector 110 , the controller 120 , and the release control element 130 shown in FIG. 3A , descriptions of the detector 110 , the controller 120 , and the release control element 130 shown in FIG. 3C are omitted.

FIG. 4A is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. The detector 110 comprises a capacitor C 41 , a resistor R 41 , a P-type transistor P 41 , and an N-type transistor N 41 . The capacitor C 41 is coupled between the power terminal 140 and the node 111 . The resistor R 41 is coupled between the node 111 and the ground terminal GND. The capacitor C 41 and the resistor R 41 are configured to detect whether an ESD event occurs at the power terminal 140 or at the input/output pad 150 and generate the detection signal S D .

The gate of the P-type transistor P 41 is coupled to the node 111 . The source of the P-type transistor P 41 is coupled to the input/output pad 150 through the capacitor C 42 . The gate of the N-type transistor N 41 is coupled to the node 111 . The source of the N-type transistor N 41 is coupled to the ground terminal GND. The drain of the N-type transistor N 41 is coupled to the drain of the P-type transistor P 41 to output the trigger signal S T .

In this embodiment, the controller 120 is a P-type transistor P 42 . The gate of the P-type transistor P 42 is coupled to the drain of the P-type transistor P 41 to receive the trigger signal S T . The source of the P-type transistor P 42 is coupled to the node 111 to receive the detection signal S D . The drain of the P-type transistor P 42 is coupled to the release control element 130 . The release control element 130 is an N-type transistor N 42 . The gate of the N-type transistor N 42 is coupled to the drain of the P-type transistor P 42 . The source of the N-type transistor N 42 is coupled to the ground terminal GND. The drain of the N-type transistor N 42 is coupled to the input/output pad 150 .

The capacitor C 42 is coupled between the power terminal 140 and the input/output pad 150 . When a positive ESD event occurs at the input/output pad 150 and the ground terminal GND is grounded, the voltage level of the detection signal S D is at a high voltage level. At this time, the driving circuit 400 A enters a protection mode. In the protection mode, since the voltage level of the detection signal S D is at the high voltage level, the N-type transistor N 41 is turned on so that the voltage level of the trigger signal S T is at a low voltage level. In this case, the P-type transistor P 42 is turned on. Since the voltage level of the detection signal S D is at the high voltage level, the voltage level of the control signal S C1 is also at the high voltage level to turn on the N-type transistor N 42 . When the N-type transistor N 42 is turned on, an ESD current is released from the input/output pad 150 to the ground terminal GND.

When no ESD event occurs at the power terminal 140 or the input/output pad 150 , and the power terminal 140 receives a high operation voltage, and the ground terminal GND receives a low operation voltage, the driving circuit 400 A enters a normal mode. In the normal mode, the voltage level of the detection signal S D is at a low voltage level. Therefore, the P-type transistor P 41 is turned on. Since the source of the P-type transistor P 41 is coupled to the power terminal 140 , the voltage level of the trigger signal S T is at a high voltage level. Therefore, the P-type transistor P 42 is turned off. In this case, the N-type transistor N 42 is controlled by the control signal S C . For example, when the voltage level of the control signal S C2 is at a high voltage level, the N-type transistor N 42 is turned on to set the voltage level of the input/output pad 150 at the low voltage level. When the voltage level of the control signal S C2 is at a low voltage level, the N-type transistor N 42 is turned off to stop setting the voltage level of the input/output pad 150 at the low voltage level.

FIG. 4B is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. FIG. 4B is similar to FIG. 4A except that the driving circuit 400 B shown in FIG. 4B further comprises a transmission gate 410 . The transmission gate 410 transmits the control signal S C2 to the N-type transistor N 42 according to the voltage level (i.e. the trigger signal S T ) of the drain of the P-type transistor P 41 .

As shown in FIG. 4B , the transmission gate 410 comprises a P-type transistor P 43 , an N-type transistor N 43 , and an inverter INV 3 . The gate of the P-type transistor P 43 is coupled to the output terminal of the inverter INV 3 . The source of the P-type transistor P 43 receives the control signal S C2 . The drain of the P-type transistor P 43 is coupled to the gate of the N-type transistor N 42 .

The gate of the N-type transistor N 43 is coupled to the drain of the P-type transistor P 41 to receive the trigger signal S T . The source of the N-type transistor N 43 is coupled to the drain of the P-type transistor P 43 . The drain of the N-type transistor N 43 receives the control signal S C2 . The input terminal of the inverter INV 3 is coupled to the gate of the N-type transistor N 43 .

When the voltage level of the trigger signal S T is at a low voltage level, the N-type transistor N 43 and the P-type transistor P 43 are turned off. Therefore, the transmission gate 410 does not provide the control signal S C2 to the N-type transistor N 42 . When the voltage level of the trigger signal S T is at a high voltage level, the N-type transistor N 43 and the P-type transistor P 43 are turned on to transmit the control signal S C2 to the gate of the N-type transistor N 42 . At this time, if the voltage level of the control signal S C2 is at a high voltage level, the N-type transistor N 42 is turned on to set the voltage level of the input/output pad 150 at a low voltage level. If the voltage level of the control signal S C2 is at a low voltage level, the N-type transistor N 42 is turned off to stop setting the voltage level of the input/output pad 150 .

FIG. 5A is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. The detector 110 comprises a resistor R 51 , a capacitor C 51 , a P-type transistor P 51 , and an N-type transistor N 51 . The resistor R 51 is coupled between the power terminal 140 and the node 111 . The capacitor C 51 is coupled between the node 111 and the ground node GND. The resistor R 51 and the capacitor C 51 are configured to determine whether an ESD event occurs at the power terminal 140 and generate the detection signal S D . The gate of the P-type transistor P 51 is coupled to the node 111 . The source of the P-type transistor P 51 is coupled to the power terminal 140 . The gate of the N-type transistor N 51 is coupled to the node 111 . The source of the N-type transistor N 51 is coupled to the ground terminal GND. The drain of the N-type transistor N 51 is coupled to the drain of the P-type transistor P 51 .

In this embodiment, the controller 120 is an N-type transistor N 52 , and the release control element 130 is a P-type transistor P 52 . The gate of the N-type transistor N 52 is coupled to the drain of the P-type transistor P 51 to receive the trigger signal S T . The source of the N-type transistor N 52 is coupled to the node 111 . The drain of the N-type transistor N 52 is coupled to the release control element 130 . The gate of the P-type transistor P 52 is coupled to the drain of the N-type transistor N 52 . The source of the P-type transistor P 52 is coupled to the power terminal 140 . The drain of the P-type transistor P 52 is coupled to the input/output pad 150 .

When a positive ESD event occurs at the power terminal 140 , and the input/output pad 150 is grounded, the driving circuit 500 A enters a protection mode. In the protection mode, the voltage level of the detection signal S D is at a low voltage level. Therefore, the P-type transistor P 51 is turned on so that the voltage level of the trigger signal S T is at a high voltage level. Since the voltage level of the trigger signal S T is at the high voltage level, the N-type transistor N 52 is turned on so that the voltage level of the control signal S C1 is at the low voltage level to turn on the P-type transistor P 52 . When the P-type transistor P 52 is turned on, an ESD current is released from the power terminal 140 to the input/output pad 150 .

When no ESD event occurs at the power terminal 140 , and the power terminal 140 receives a high operation voltage, and the ground terminal GND receives a low operation voltage, which is lower than the high operation voltage, the driving circuit 500 A enters a normal mode. In the normal mode, the voltage level of the detection signal S D is at the high voltage level so that the N-type transistor N 51 is turned on. At this time, since the voltage level of the trigger signal S T is at a low voltage level, the N-type transistor N 52 is turned off In this mode, the P-type transistor P 52 controls the voltage level of the input/output pad 150 according to the control signal S C2 . For example, when the voltage level of the control signal S C2 is at a low voltage level, the P-type transistor P 52 is turned on to set the voltage level of the input/output pad 150 at a high voltage level. When the voltage level of the control signal S C2 is at a high voltage level, the P-type transistor P 52 is turned off to stop setting the voltage level of the input/output pad 150 .

FIG. 5B is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. FIG. 5B is similar to FIG. 5A except that the driving circuit 500 B shown in FIG. 5B further comprises a capacitor C 52 . As shown in FIG. 5B , the capacitor C 52 is coupled between the input/output pad 150 and the ground terminal GND to control the voltage level of the ground terminal GND. For example, when the input/output pad 150 is grounded, the voltage level of the ground terminal GND is also coupled to ground.

FIG. 5C is a schematic diagram of another exemplary embodiment of the driving circuit, according to various aspects of the present disclosure. FIG. 5C is similar to FIG. 5A except that the driving circuit 500 C shown in FIG. 5C further comprises a transmission gate 510 . The transmission gate 510 transmits the control signal S C2 to the P-type transistor P 52 according to the voltage level (i.e. the detection signal S D ) of the node 111 . The P-type transistor P 52 controls the voltage level of the input/output pad 150 according to the control signal S C2 .

In this embodiment, the transmission gate 510 comprises a P-type transistor P 53 , an N-type transistor N 53 , and an inverter INV 4 . The gate of the P-type transistor P 53 is coupled to the output terminal of the inverter INV 4 . The source of the P-type transistor P 53 receives the control signal S C2 . The drain of the P-type transistor P 53 is coupled to the gate of the P-type transistor P 52 . The gate of the N-type transistor N 53 is coupled to the node 111 to receive the detection signal S D . The source of the N-type transistor N 53 is coupled to the drain of the P-type transistor P 53 . The drain of the N-type transistor N 53 receives the control signal S C2 . The input terminal of the inverter INV 4 is coupled to the gate of the N-type transistor N 53 .

When the voltage level of the detection signal S D is at a low voltage level, the N-type transistor N 53 and the P-type transistor P 53 are turned off. Therefore, the transmission gate 510 does not provide the control signal S C2 to the P-type transistor P 52 . When the voltage level of the detection signal S D is at a high voltage level, the N-type transistor N 53 and the P-type transistor P 53 are turned on to transmit the control signal S C2 to the gate of the P-type transistor P 52 . At this time, if the voltage level of the control signal S C2 is at the low voltage level, the P-type transistor P 52 is turned on to set the voltage level of the input/output pad 150 at the high voltage level. If the voltage level of the control signal S C2 is at the high voltage level, the P-type transistor P 52 is turned off to stop setting the voltage level of the input/output pad 150 .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.