Memory apparatus and write failure responsive negative bitline voltage write assist circuit thereof

The present invention generally relates to a memory apparatus, and more particularly to a write assist circuit of the memory apparatus with negative bit line scheme.

Referring to FIG. 1 , FIG. 1 illustrates a schematic plot of a static random access memory (SRAM) cell. The SRAM cell 100 includes six transistors, and is coupled to a bit line BL, an inverted bit line BLB, and a word line WL. In a data writing operation, when a stored data at a node N 1 is logic “1” and a write data with logic “0” is written to the node N 1 , the write data is carried on the bit line BL with logic “0”, and the transistor PG is turned on according to a signal on the word line WL. At the same time, the transistor PU is also turned on by a voltage on the node N 2 with logic “0”. That is, the node N 1 is discharge to logic “0” by the transistor PG, and is also charge to a power voltage VDD (logic “1”) by the transistor PU. It should be noted here, when driving abilities of the transistor PG is weaker than the transistor PU owing to process variation, a write-failure event can happen.

The present disclosure provides a memory apparatus and a write assist circuit thereof, and the write assist circuit can guarantee successful write operations on the memory apparatus with a negative bit line (NBL) write assist scheme.

The present disclosure provides the write assist circuit including a write detection circuit, a write detection-aware write driver and a write condition recovery circuit. The write detection circuit receives a write failure detection enable signal and a write data, and generates a write detect control signal and generating a selecting signal according to a detection result signal and the write data. The write detection-aware write driver receives the write detect control signal and operates a write detection operation on a selected memory cell according to the write detect control signal, and decides whether to provide a negative voltage to one of a bit line and an inverted bit line of the selected memory cell or not according to the selecting signal.

The present disclosure provides the memory apparatus including a plurality of memory cells, a plurality of Y-pass circuits, a plurality of write detection-aware write drivers, a plurality of read circuits and a negative voltage generator shared by multiple input output (I/O) circuits of the memory apparatus. Each of the write detection-aware write drivers includes the write assist circuit mentioned above. The Y-pass circuits are coupled to the memory cells. The write circuits are respectively coupled to the Y-pass circuits, and the read circuits are coupled to the Y-pass circuits and respectively coupled to the write detection-aware write drivers. The negative voltage generator is coupled to the write assist circuits, generated according to an enable signal and provides the negative voltage to all of the write assist circuits according to each of a plurality of selecting signals of each of the I/O circuits.

According to the above descriptions, in the present disclosure, the negative bit line scheme can be activated for assisting the write operation for the memory apparatus. Furthermore, the negative bit lines scheme of present disclosure can be activated dynamically only when it is needed. The write assist circuit may detect whether the write operation is successful or fault, and the negative bit line scheme may be activated only when the write operation is fault. Such as that, dynamic energy of the memory apparatus can be saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 illustrates a schematic plot of a static random access memory (SRAM) cell.

FIG. 2A illustrates a schematic plot of a write assist circuit according to an embodiment of present disclosure.

FIG. 2B illustrates a schematic plot of a write detection-aware write driver according to an embodiment of present disclosure.

FIG. 2C illustrate a schematic plot of the write result deciding circuit according to the embodiment in FIG. 2B of present disclosure.

FIG. 3 illustrates waveform plot of the write assist circuit according to the embodiment of present disclosure.

FIG. 4 illustrates a block diagram of function circuits according to an embodiment of present disclosure.

FIG. 5 illustrates a schematic plot of a write assist circuit according to another embodiment of present disclosure.

FIG. 6A illustrates a schematic plot of a memory apparatus according to an embodiment of present disclosure.

FIG. 6B illustrate a block diagram of the write detection-aware write driver according to the embodiment in FIG. 6A of present disclosure.

Reference will now be made in detail to the present preferred embodiment of the invention, examples of which are illustrated in the accompanying drawings.

Referring to FIG. 2A , FIG. 2A illustrates a schematic plot of a write assist circuit according to an embodiment of present disclosure. The write assist circuit 201 includes a write detection-aware write driver 2011 , a write condition recovery circuit 2012 , and a write detection circuit 2013 . During a write detection time period, the write condition recovery circuit 2012 is coupled to a selected memory cell SMC, and the write condition recovery circuit 2012 respectively couples the bit line and the inverted bit line of the selected memory cell SMC to the write data line WDL and the inverted write data line WDLB according to a write pass-gate control signal WEPG, and providing a pre-charge voltage to the write data line WDL or the inverted data line WDLB during the write detection time period according to a recovery signal PSW. The write detection circuit 2013 is coupled to the write condition recovery circuit 2012 and the write detection-aware write driver 2011 . The write detection circuit 2013 receives a detected result signal DRS, a write data DIN and a write failure detection enable signal WDEN, and generates a write detect control signal CTL according to the write failure detection enable signal WDEN and the write data DIN during the write detection time period and generates a selecting signal SWS according to the detection result signal DRS and the write data DIN. The write detection circuit 2013 generates the write pass-gate control WEPG according to a word line signal WL and the detected result signal DRS and generates the recovery signal PSW according to the detected result signal DRS. The write detection-aware write driver 2011 is coupled to the write condition recovery circuit 2012 . The write detection-aware write driver 2011 receives the write detect control signal CTL and operates a write detection operation on the selected memory cell SMC in real time according to the write detect control signal CTL, and decides whether to provide a negative voltage VNBL to one of a bit line and an inverted bit line of the selected memory cell SMC or not according to the selecting signal SWS. Wherein, a voltage level of the negative voltage VNBL is lower than a voltage level of a reference ground voltage of the write assist circuit 201 .

Please be noted here, the write assist circuit 201 activates a negative bit line scheme only when a write-failure event can be determined according to the detected result signal DRS. That is, an efficiency of the negative bit line scheme can be improved.

Referring to FIG. 2B , FIG. 2B illustrates a schematic plot of a write detection-aware write driver according to the embodiment in FIG. 2A of present disclosure. The write detection-aware write driver 200 includes a power stage circuit 210 , a driving stage circuit 220 , a selecting circuit 230 , and a write result deciding circuit 240 . The power stage circuit 210 receives a power voltage VDD, and determines whether to float one of a write data line WDL and an inverted write data line WDLB of a selected memory cell or not according to sub-signals CTL 1 and CTL 2 of a write detect control signal during a write detection time period, wherein the sub-signals CTL 1 and CTL 2 may be generated according to a write failure detection enable signal WDEN, and a write data DIN The selected memory cell may be a static random access memory (SRAM) cell.

Furthermore, in FIG. 2B , the write condition recovery circuit 202 includes transistors TP 1 and TP 2 , transmission gates T 11 and T 12 . The transmission gate T 11 is coupled between the data line DL and the write data line WDL, and the transmission gate T 12 is coupled between the inverted data line DLB and the inverted write data line WDLB. The transmission gates T 11 and T 12 are respectively controlled by a write pass-gate control signal WEPG 1 (and an inverted write pass-gate control signal WEPG 1 B) and a write pass-gate control signal WEPG 2 (and an inverted write pass-gate control signal WEPG 1 B) to be turned on or cut off. The transistors TP 1 and TP 2 are respectively coupled to the data line DL and the inverted data line DLB. The transistors TP 1 and TP 2 respectively provides a pre-charge voltage PV to the data line DL and the inverted data line DLB according to the recovery signal PSW 1 and PSW 2 .

In detail, in a data writing operation, the transmission gates T 11 and T 12 are turned on, and the write data line WDL and the inverted write data line WDLB are respectively connected to a bit line and an inverted bit line of the selected memory, and the write data DIN can be written to the selected memory cell through the write data line WDL and the inverted write data line WDLB. Then, before the write detection time period of the data writing operation, one of the write data line WDL and the inverted write data line WDLB is pulled to logic “0” to be a writing “0” side, and another one of the write data line WDL and the inverted write data line WDLB is pre-charged to logic “1” to be a writing “1” side, and after the write failure detection period starts, the power stage circuit 210 floats one of the write data line WDL and the inverted write data line WDLB according to the sub-signals CTL 1 and CTL 2 .

In this embodiment, the power stage circuit 210 includes transistors M 1 and M 2 . The transistor M 1 receives the power voltage VDD and is coupled to the write data line WDL through the driving stage circuit 220 , and the transistor M 2 receives the power voltage VDD and is coupled to the inverted write data line WDLB through the driving stage circuit 220 . The transistors M 1 and M 2 are respectively controlled by the sub-signals CTL 1 and CTL 2 . For example, if the write data DIN with logic “0” is written to the selected memory cell through the write data line WDL in the data writing operation, the driving stage circuit 220 may float the inverted write data line WDLB by cutting off the transistor M 2 according to the sub-signal CTL 2 after the data writing operation. If the selected memory cell is not flipped yet, a voltage level on the inverted write data line WDLB may be discharged by the selected memory cell, and a voltage level on a node N 3 is reduced. If the voltage level on the node N 3 is lower than a threshold value, the write-failure event can be determined. On the contrary, if the selected memory cell have been flipped successfully, the voltage level on the node N 3 is not discharged and is not lower than the threshold value, a write success event can be determined.

The driving stage circuit 220 is coupled to the power stage circuit 210 , the selecting circuit 230 , and the write result deciding circuit 240 . The driving stage circuit 220 provides one of a first selected voltage and the power voltage VDD to the write data line WDL, and provides one of a second selected voltage and the power voltage VDD to the inverted write data line WDLB according to the write data DIN.

In this embodiment, the driving stage circuit 220 includes transistors M 3 -M 6 . A first end of the transistor M 3 is coupled to a second end of the transistor M 1 , a second end of the transistor M 3 is coupled to the write data line WDL, and a control end of the transistor M 3 receives the write data DIN. A first end of the transistor M 4 is coupled to the write data line WDL, a second end of the transistor M 4 receives the first selected voltage from the selecting circuit 230 , and a control end of the transistor M 4 receives an inverted write data DINb. Moreover, a first end of the transistor M 5 is coupled to a second end of the transistor M 2 , a second end of the transistor M 5 is coupled to the inverted write data line WDLB, and a control end of the transistor M 5 receives the inverted write data DINb. A first end of the transistor M 6 is coupled to the inverted write data line WDLB, a second end of the transistor M 6 receives the second selected voltage from the selecting circuit 230 , and a control end of the transistor M 6 receives the write data DIN. Wherein, the write data DIN is inverted to the inverted write data DINb.

Please note, when the write-failure event mentioned above is determined, the transistor M 4 may be turned on by the inverted write data DINb (with logic “1”) and the transistor M 4 transports the first selected voltage to the write data line WDL. In this case, the first selected voltage is selected to be a negative voltage VNBL, and a voltage level of the negative voltage VNBL is smaller than a voltage of a reference ground voltage GND of the selected memory cell. That is, a negative bit line scheme can be performed, and a write assist operation can be achieved.

The selecting circuit 230 is coupled to the driving stage circuit 220 . The selecting circuit 230 selects one of the negative voltage VNBL and the reference ground voltage GND to generate the first selected voltage and selects one of the negative voltage VNBL and the reference ground voltage GND to generate the second selected voltage according to the selecting signal SWS.

The selecting circuit 230 is coupled to the driving stage circuit 220 . The selecting circuit 230 selects one of the negative voltage VNBL and the reference ground voltage GND to generate the first selected voltage and selects one of the negative voltage VNBL and the reference ground voltage GND to generate the second selected voltage according to the selecting signal SWS.

Please note, when the write success event is determined, the selecting circuit 230 provides the reference ground voltage GND to generate both of the first and second selected voltages. On the contrary, when the write-failure event is determined, the selecting circuit 230 provides the reference ground voltage GND to generate one of the first and second selected voltages for providing to a selected write data line for writing logic “1”, and provides the negative voltage VNBL to generate another one of the first and second selected voltages for providing to an unselected write data line for writing logic “0”.

In this embodiment, the selecting circuit 230 includes transmission gates TG 1 -TG 4 . The transmission gate TG 1 has an input end for receiving the negative voltage VNBL, an output end for generating the first selected voltage, and the transmission gate TG 1 may be turned on or cut off according to a sub-signal SWS 1 of a selecting signal SWS. The transmission gate TG 2 has an input end for receiving the reference ground voltage GND and an output end coupled to the output end of the transmission gate TG 1 , wherein the transmission gate TG 2 is turned on or cut off according to the sub-signal SWS 1 of the selecting signal SWS. Moreover, the transmission gate TG 3 has an input end for receiving the negative voltage VNBL, an output end for generating the second selected voltage, and the transmission gate TG 3 is turned on or cut off according to a sub-signal SWS 2 of the selecting signal SWS. The transmission gate TG 4 has an input end for receiving the reference ground voltage GND and an output end coupled to the output end of the transmission gate TG 3 , wherein the transmission gate TG 4 is turned on or cut off according to the sub-signal SWS 2 of the selecting signal SWS. Wherein, on or off statuses of the transmission gates TG 1 and TG 2 are complementary, on or off statuses of the transmission gates TG 3 and TG 4 are complementary. The selecting signal SWS can be generated according to the detection result signal DRS and the write data DIN.

The write result deciding circuit 240 is coupled to the power stage circuit 210 and the driving stage circuit 220 . The write result deciding circuit 240 generates the detection result signal DRS according to signals on the nodes N 4 , N 3 and the write failure detection enable signal WDEN. The nodes N 4 and N 3 are respectively coupled to the write data line WDL and the inverted data line WDLB.

Referring to FIG. 2C , FIG. 2C illustrates a schematic plot of the write result deciding circuit according to the embodiment in FIG. 2B of present disclosure. In this embodiment, the write result deciding circuit 240 includes transistors MB 1 -MB 5 . The transistor MB 1 forms a capacitor, and coupled between the node N 3 and a reference ground GND. The transistors MB 2 -MB 4 are coupled between a power voltage VDD and the reference ground GND in series, and control ends of the transistor MB 2 and MB 4 are coupled to the node N 3 , and a control end of the transistor MB 3 receives the write failure detection enable signal WDEN. A first end of the transistor MB 5 receives the power voltage VDD, a second end of the transistor MB 5 generates the detection result signal DRS, and a control end of the transistor MB 5 receives the write failure detection enable signal WDEN.

In detail operation of the write result deciding circuit 240 , during the write failure detection operation is operated, the transistor MB 3 is turned on (the transistor MB 5 is cut-off), and the transistors MB 2 and MB 4 form an inverter, and a voltage on the node N 3 is inverted to generate the detection result signal DRS. If the voltage level on the node N 3 is reduced to lower than the threshold value of the inverter formed by the transistors MB 2 and MB 4 , the detection result signal DRS with logic “1” can be generated, and the write-failure event can be detected. On the other hand, if the voltage level on the node N 3 is not reduced to lower than the threshold value of the inverter formed by the transistors MB 2 and MB 4 , the detection result signal DRS with logic “0” can be generated, and the write access event can be detected.

In detail operation of the write result deciding circuit 240 , during the write failure detection operation is operated, the transistor MB 3 is turned on (the transistor MB 5 is cut-off), and the transistors MB 2 and MB 4 form an inverter, and a voltage on the node N 3 is inverted to generate the detection result signal DRS. If the voltage level on the node N 3 is reduce to lower than the threshold value of the inverter formed by the transistors MB 2 and MB 4 , the detection result signal DRS with logic “1” can be generated, and the write-failure event can be detected. On the other hand, if the voltage level on the node N 3 is not reduce to lower than the threshold value of the inverter formed by the transistors MB 2 and MB 4 , the detection result signal DRS with logic “0” can be generated, and the write access event can be detected.

When not operating the write failure detection operation, the transistor MB 3 is cut-off and the transistor MB 5 is turned on. At this time, the voltage of the detection result signal DRS is pulled up to the power voltage VDD through the transistor MB 5 . Furthermore, the capacitor formed by the transistor MB 1 is used to adjust a variable speed of the voltage on the node N 3 .

Referring to FIG. 3 , FIG. 3 illustrates waveform plot of the write assist circuit according to the embodiment of present disclosure. In FIG. 3 , at the time point T 1 , after a rising edge of a write failure detection enable signal WDEN, the transistor M 2 is cut off to float the inverted write data line WDLB according to the sub-signal CTL 2 of the write detect control signal. Since the selected memory cell is not flipped, an inverted output signal QB of the selected memory cell is kept on logic “0” (see curve 312 ) before the time point T 2 . Such as that, the voltage level on the inverted write data line WDLB (see curve 322 ) is reduced from the time point T 1 to the time point T 2 . At the time point T 2 , the voltage level on the inverted write data line WDLB is lower than the threshold value, and a negative bit line scheme is activated by the sub-signal SWS 1 of the selecting signal SWS (see curve 332 ) after the time point T 2 . After the time point T 2 , the voltage level on the inverted write data line WDLB is recovered according to the sub-signal CTL 2 (referring to the arrow RC). The write data line WDL is further pulled down corresponding to the negative bit line scheme. By the write assist operation provided by the negative bit line scheme, an output data Q (see curve 311 ) and the inverted output data QB can be flipped successfully, and the data write operation can be completed efficiently.

Referring to FIG. 4 , FIG. 4 illustrates a block diagram of function circuits according to an embodiment of present disclosure. The write assist circuit of present disclosure may further include function circuits 410 , 420 and 430 . The function circuit 410 is coupled to the power stage circuit and the write result deciding circuit, and generates the sub-signals CTL 1 and CTL 2 of the write detect control signal according to the write failure detection enable signal WDEN, and the write data DIN. The second function circuit 420 is coupled to the write result deciding circuit, generates the sub-signals SWS 1 and SWS 2 of the selecting signal SWS according to the detection result signal DRS and the write data DIN. The function block 430 receives the detection result signal DRS and the word line signal WL. The function block 430 generates the recovery signals PSW 1 , PSW 2 according to the detected result signal DRS, and generates the write enable signals WPEG 1 and WPEG 2 according to a word line signal WL and the detected result signal DRS.

The function circuits 410 - 430 may be implemented by one or more logic gate(s), and any one of design methods for digital circuit design known by a person skilled in the art can be used for implementing the function circuits 410 and 420 .

Referring to FIG. 5 , FIG. 5 illustrates a schematic plot of a write assist circuit according to another embodiment of present disclosure. The write assist circuit 500 includes a write condition recovery circuit 502 , a write detection-aware write driver 501 , and a write detection circuit 503 . The write detection-aware write driver 501 includes a power stage circuit 510 , a driving stage circuit 520 , a selecting circuit 530 , a write result deciding circuit 540 , and function circuits 550 , 560 and 570 . Comparing with the write detection-aware write driver 200 , the power stage circuit 510 , the driving stage circuit 520 , the selecting circuit 530 , and the function circuits 550 - 570 are respectively same as the power stage circuit 210 , the driving stage circuit 220 , the selecting circuit 230 , and the function circuits 410 - 430 . It should be noted here, the write result deciding circuit 540 is different from the write result deciding circuit 240 . In this embodiment, the write result deciding circuit 540 includes a sense amplifier 541 and transmission gates 542 - 545 . The transmission gates 542 - 543 form a first switch unit for selecting the write data line WDL or a reference voltage Vref to connect to the sense amplifier 541 . Further, the transmission gates 544 - 545 form a second switch unit for selecting the inverted write data line WDLB or the reference voltage Vref to connect to the sense amplifier 542 . That is, the sense amplifier 541 may sense a voltage difference between the signal on the selected write data line (the write data line WDL or the inverted write data line WDLB) and the reference voltage Vref to generate a sense out signal SA_out, and the sense out signal SA_out can be used to be the detection result signal DRS.

Additionally, the sense amplifier 541 may be used for a data reading operation for the selected memory cell. The sense amplifier 541 may select to connect to the write data line WDL and the inverted write data line WDLB for the data reading operation. That is, no more additional sense amplifier need to be implement in present embodiment.

Referring to FIG. 6A . FIG. 6A illustrates a schematic plot of a memory apparatus according to an embodiment of present disclosure. The memory apparatus 600 includes a plurality of memory cells 6011 - 601 N, a plurality of Y-pass circuits 611 - 61 M, a plurality of write circuits 621 - 62 M, a plurality of read circuits 651 - 65 M, and a negative voltage generator 630 . The memory cells 6011 - 601 N form a memory cell array 601 , and the memory cells 6011 - 601 N are SRAM memory cells. The Y-pass circuits 611 - 61 M respectively correspond to a plurality of input and output (I/O) circuits IO[ 0 ]-IO[M−1], and the Y-pass circuits 611 - 61 M are coupled to the memory cell array 601 . The write circuit 621 - 62 M are respectively coupled to the Y-pass circuits 611 - 61 M. The read circuits 651 - 65 M are respectively coupled to the write circuits 621 - 62 M and respectively coupled to the Y-pass circuits 611 - 61 M. The negative voltage generator 630 is coupled to all of the write circuits 621 - 62 M.

Each of the write circuits 621 - 62 M can be implemented by including the write assist circuits 201 or 500 mentioned above. And it should be noted here, only one negative voltage generator 630 is needed for the memory apparatus 600 .

Refer to FIG. 6B , FIG. 6B illustrate a block diagram of the write detection-aware write driver according to the embodiment in FIG. 6A of present disclosure. The write detection-aware write driver 621 may include the write detection-aware write driver 2011 , the write condition recovery circuit 2012 , and the write detection circuit 2013 as shown in FIG. 2A .

The negative voltage generator 630 provides the negative voltage VNBL to one or more of the write circuits 621 - 62 M. The negative voltage generator 630 includes delay circuits 631 - 632 and voltage pumping circuits 633 - 634 . The delay circuits 631 - 632 receive an enable signal NBL_enb in sequence, and respectively generate delayed enable signals DEN 1 and DEN 2 in sequence. The delayed enable signals DEN 1 and DEN 2 are respectively fed to the voltage pumping circuits 633 - 634 , and the voltage pumping circuits 633 - 634 generate the negative voltage VNBL by a voltage pumping down operation according to a falling transition of the delayed enable signal DEN 1 and DEN 2 .

In this embodiment, the voltage pumping circuit 633 includes a buffer B 1 and a capacitor C 1 , and the voltage pumping circuit 634 includes a buffer B 2 and a capacitor C 2 . An input end of the buffer B 1 receives the delayed enable signal DEN 1 , and an output of the buffer B 1 is coupled to one end of the capacitor C 1 . Another end of the capacitor C 1 generates the negative voltage VNBL. An input end of the buffer B 2 receives the delayed enable signal DEN 2 , and an output of the buffer B 2 is coupled to one end of the capacitor C 2 . Another end of the capacitor C 2 generates the negative voltage VNBL.

Numbers of the voltage pumping circuit and the delay circuit are no limit for the negative voltage generator 630 . One or more voltage pumping circuit(s) and one or more delay circuit(s) can be implemented in the negative voltage generator 630 . In FIG. 6 , two voltage pumping circuits and two delay circuits implemented in the negative voltage generator 630 is just an example, and not used to limit a scope of present disclosure.

In summary, the present disclosure provides a write assist circuit for detecting a flipping status for the selected memory cell, and the negative bit line scheme is activated only when the write-failure event happened. That is, the negative bit line scheme can be dynamically activated, and energy consumption can be saved efficiently. Moreover, only one negative voltage generator is needed for the memory apparatus, and size of circuit of the memory apparatus can be reduced, such as that, cost of the memory apparatus can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.