Enhanced density assembly having microelectronic packages mounted at substantial angle to board

The subject matter of this application relates to microelectronic packages and assemblies in which a plurality of microelectronic packages are stacked with one another and electrically interconnected with a circuit panel.

Semiconductor die or chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer, tablet, smartphone or other mobile device.

In order to save space certain conventional designs have stacked multiple microelectronic elements or semiconductor chips within a package. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack. However, conventional stacked packages have disadvantages of complexity, cost, thickness and testability.

In spite of the above advances, there remains a need for improved stacked packages and especially stacked chip packages which incorporate multiple chips for certain types of memory, e.g., flash memory. There is a need for such packages and assemblies which are reliable, thin, testable and that are economical to manufacture.

FIG. 1 is a sectional view depicting a microelectronic assembly in accordance with an embodiment disclosed herein.

FIG. 2 is a sectional view depicting a microelectronic package in accordance with an embodiment disclosed herein.

FIG. 3 is a sectional view depicting a method of assembling a microelectronic package stack with a circuit panel in accordance with an embodiment disclosed herein.

FIG. 4 is a top down view depicting a microelectronic assembly in accordance with an embodiment disclosed herein.

FIG. 5 is a top down view depicting a circuit panel arranged to receive microelectronic packages in accordance with an embodiment disclosed herein.

FIG. 6 is a top down view further depicting a microelectronic assembly in accordance with an embodiment disclosed herein.

FIG. 7 is a sectional view depicting a microelectronic assembly in accordance with a variation of the embodiment disclosed relative to FIG. 1 herein.

FIG. 8 is a sectional view depicting a microelectronic assembly in accordance with an embodiment disclosed herein.

FIG. 9A is a diagram illustrating signal assignments of package contacts of a first package to be mounted to a first surface of a circuit panel.

FIG. 9B is a diagram illustrating signal assignments of package contacts of a second package to be mounted to a second surface of a circuit panel opposite the first surface.

FIG. 9C is a sectional view depicting a microelectronic assembly in accordance with a variation of the embodiment disclosed relative to FIG. 1 herein.

FIG. 10 is a sectional view depicting a microelectronic assembly in accordance with a variation of the embodiment disclosed relative to FIG. 1 herein.

FIG. 11 is a top down view depicting a microelectronic assembly in accordance with a variation of the embodiment disclosed relative to FIG. 6 herein.

FIG. 12 is a top down view depicting a microelectronic assembly in accordance with a variation of the embodiment disclosed relative to FIG. 6 herein.

FIGS. 13, 14, 15 and 16 are sectional views depicting stages in fabrication of a microelectronic assembly in accordance with an embodiment of the invention.

FIG. 17 is a top down view further depicting a microelectronic assembly corresponding to that depicted in FIG. 16 .

FIGS. 18, 19, 20, and 21 are sectional views depicting stages in fabrication of a microelectronic assembly in accordance with an embodiment of the invention.

FIG. 22 is a sectional view depicting a microelectronic assembly in accordance with a variation of the embodiment seen in FIG. 21 .

In accordance with one embodiment, a stacked microelectronic assembly can comprise a plurality of stacked microelectronic packages. Each microelectronic package can include a dielectric element having a major surface defining a plane, an interconnect edge surface extending away from the major surface and an interconnect region adjacent the interconnect edge surface. A plurality of electrically conductive package contacts can be disposed at the interconnect region. A microelectronic element has a front surface overlying and substantially parallel to the major surface, and a plurality of chip contacts at the front surface can be electrically coupled with the package contacts. The plurality of microelectronic packages are stacked with one another such that planes defined by the major surfaces of the dielectric elements are substantially parallel to one another. A circuit panel has a mounting surface and panel contacts at the mounting surface, wherein the plurality of package contacts of each package in the stacked microelectronic assembly are electrically coupled via an electrically conductive material with a corresponding set of panel contacts at the mounting surface. Planes defined by the major surfaces of the dielectric elements can be oriented at a substantial angle relative to the mounting surface.

In accordance with one embodiment, a stacked microelectronic assembly can comprise a plurality of stacked microelectronic packages. Each microelectronic package can include a dielectric element having a major surface defining a plane, an interconnect edge surface extending away from the major surface and an interconnect region adjacent the interconnect edge surface. A plurality of electrically conductive package contacts can be disposed at the interconnect region. Each package may include a plurality of stacked microelectronic elements each microelectronic element having a front surface defining a plane extending in a first direction and a second direction transverse to the first direction, a plurality of edge surfaces extending away from the plane of the front surface, each microelectronic element having a plurality of chip contacts at the front surface, the microelectronic elements stacked with the planes parallel to one another,

The plurality of microelectronic packages can be stacked with one another such that planes defined by the major surfaces of the dielectric elements are substantially parallel to one another. A circuit panel has a mounting surface and panel contacts at the mounting surface, wherein the plurality of package contacts of each package in the stacked microelectronic assembly are electrically coupled via an electrically conductive material with a corresponding set of panel contacts at the mounting surface. Planes defined by the major surfaces of the dielectric elements can be oriented at a substantial angle relative to the mounting surface.

A method is disclosed for fabricating a stacked microelectronic assembly. A plurality of microelectronic packages are fabricated. Each package comprises a dielectric element having a major surface defining a plane, an interconnect edge extending away from the major surface and an interconnect region adjacent the interconnect edge with a plurality of electrically conductive package contacts at the interconnect region. One or more microelectronic elements each having a memory storage array thereon, and having a front surface defining a plane extending in a first direction and a second direction transverse to the first direction and having edge surfaces extending away from the plane of the front surface, each microelectronic element having a plurality of chip contacts at the front surface, the plane defined by each microelectronic element parallel to the plane defined by the major surface of the dielectric element of the respective microelectronic package.

The plurality of microelectronic packages are received into respective receiving volumes or slots of a heat spreader element, and the package contacts of each microelectronic package are bonded to corresponding panel contacts at a major surface of a circuit panel, wherein the planes defined by the dielectric elements are oriented at a substantial angle relative to the major surface of the circuit panel.

As used in this disclosure with reference to a dielectric region or a dielectric structure of a component, e.g., circuit structure, interposer, microelectronic element, capacitor, voltage regulator, circuit panel, substrate, etc., a statement that an electrically conductive element is “at” a surface of the dielectric region or component indicates that, when the surface is not covered or assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to that surface of the dielectric region from outside the dielectric region or component. Thus, a terminal or other conductive element which is at a surface of a dielectric region may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the dielectric region.

FIG. 1 illustrates a microelectronic assembly 100 in accordance with an embodiment of the invention. As seen in FIG. 1 , microelectronic assembly 100 includes a package stack 110 which includes a plurality of microelectronic packages 108 , each microelectronic package including one or more microelectronic elements 112 . Microelectronic assembly 100 and other microelectronic assemblies disclosed or referenced herein can provide enhanced storage density which can be advantageously provided in various computing systems which can be small, medium, or large-scale computing systems, or which may be advantageously used in data centers, among which are enterprise systems, government systems, hosted systems, search engine systems, cloud storage, or other large-scale data centers.

Each package may include a single microelectronic element 112 , or in the particular case seen in FIGS. 1-2 , a plurality of stacked microelectronic elements. In one example, microelectronic element 112 may be a bare semiconductor chip, or may be a semiconductor chip having contacts at a front face thereof and additional electrically conductive features thereon which overlie the front face and are coupled with the contacts. Each microelectronic element 112 , e.g., a semiconductor chip has a front surface 114 defining a respective plane 116 - x of a plurality of planes 116 - 1 , 116 - 2 , etc. Each microelectronic element 112 may have a plurality of contacts 118 at a front surface thereof at or near a peripheral edge surface 120 of the chip, with a rear surface 122 opposite the front surface, and the interconnect edge surface 120 extending between the front and rear surfaces. Commonly available flash memory semiconductor chips, such as the NAND and NOR type flash memory chips mentioned below, typically have their chip contacts disposed at the front surface near a single peripheral edge surface 120 of the semiconductor chip. Although the front surfaces of each of the chips in the package stack are shown all oriented in the same direction in FIGS. 1 and 2 , the front surfaces of one or more of the chips in the package stack can be oriented in the opposite direction such that portions of the front surfaces of at least two of the chips which are adjacent one another would either face one another or would face in opposite directions away from one another. As seen in FIG. 2 , a second peripheral edge surface 121 of each chip is opposite from the peripheral edge surface 120 .

As best seen in FIG. 2 , each stack of microelectronic elements 112 may include a dielectric region 115 that extends between the rear surface 122 - 1 of a first chip 112 - 1 and a front surface 114 - 2 of a second chip 112 - 2 adjacent to the first chip in a microelectronic package. Such dielectric regions are disposed between adjacent surfaces of other chips in the package stack depicted in FIG. 2 . The dielectric region may include one or more adhesive layers or other dielectric material. Typically, the dielectric region includes at least adhesive layers coupled to each of the opposed front or rear surfaces of adjacent chips in the package stack. In one embodiment, the dielectric region 115 includes one or more layers of epoxy, elastomer, polyimide, parylene, or other polymeric material.

In one example, each of the microelectronic elements includes one or more memory storage arrays, which may include a particular memory type such as nonvolatile memory. Nonvolatile memory can be implemented in a variety of technologies some of which include memory cells that incorporate floating gates, such as, for example, flash memory, and others which include memory cells which operate based on magnetic polarities. Flash memory chips are currently in widespread use as solid state storage as an alternative to magnetic fixed disk drives for computing and mobile devices. Flash memory chips are also commonly used in portable and readily interchangeable memory drives and cards, such as Universal Serial Bus (USB) memory drives, and memory cards such as Secure Digital or SD cards, microSD cards (trademarks or registered trademarks of SD- 3 C), compact flash or CF card and the like. Flash memory chips typically have NAND or NOR type devices therein; NAND type devices are common. Other examples of microelectronic elements 112 include one or more of DRAM, microprocessor or controller chips or combinations thereof. Each semiconductor chip may be implemented in one of various semiconductor materials such as silicon, germanium, gallium arsenide or one or more other Group III-V semiconductor compounds or Group II-VI semiconductor compounds, etc. The microelectronic elements 112 in one or more microelectronic packages 108 and in one or more “package stacks” 110 may be a combination of different chip functionalities as described above and may comprise a combination of various different semiconductor materials as described above. In one embodiment, a microelectronic element may have a greater number of active devices for providing memory storage array function than for any other function.

Each package 108 of the package stack 110 also includes a dielectric element 130 having a major surface 132 which defines a plane 134 . The dielectric element 130 may have one or multiple layers of dielectric material and one or multiple electrically conductive layers thereon. The dielectric element 130 can be formed of various materials, which may or may not include a polymeric component, and may or may not include an inorganic component. Alternatively, the substrate may be wholly or essentially polymeric or may be wholly or essentially inorganic. In various non-limiting examples, the dielectric element can be formed of a composite material such as glass-reinforced epoxy, e.g., FR-4, or glass or ceramic material.

A plurality of electrically conductive package contacts 124 , 126 are disposed at an interconnect region 136 of the dielectric element 130 adjacent an interconnect edge 138 of the dielectric element 130 . In one example seen in FIGS. 1 and 2 , package contacts 124 are at a first major surface 132 of the dielectric element 130 , and package contacts 126 are at a second major surface 135 of the dielectric element opposite from the first major surface 132 . A thermally conductive plane, e.g., 131 A, 131 B, may be disposed at one or both of the first or second major surfaces 132 , 135 .

Element contacts 118 at front surfaces 114 of each microelectronic element of the package 108 are electrically coupled with the package contacts 124 , 126 such as through leads 128 which may include, for example, wire bonds coupled to the microelectronic elements 112 arranged in an offset or staggered arrangement such as seen in FIG. 2 . Alternatively, the electrical connections between the package contacts 124 , 126 and the element contacts 118 can include a curable electrically conductive material, such as, for example, an electrically conductive material in a polymer matrix or electrically conductive ink deposited as drops, droplets or lines of the conductive material onto the package contacts, element contacts, and the areas in between. Alternatively, lines of conductive material can be formed by blanket depositing such material and then removing the material between laterally adjacent contacts on the same microelectronic subassembly or package 108 , and between adjacent portions of the leadframe on the same microelectronic package 108 . In one example, the electrically conductive material can be such as described in U.S. Pat. No. 8,178,978 to McElrea et al., the disclosure of which is incorporated herein by reference. Alternatively, electrical connections between the package contacts and the element contacts can include a metal plated onto and in-between the package contacts 124 , 126 and the element contacts 118 .

Each package contact 124 , 126 may extend to the interconnect edge 138 of the package 108 in an interconnect region 136 which may extend from a peripheral edge or “remote surface” of the respective package 108 . In some cases, a dielectric region or insulating encapsulant region 140 may contact the element contacts 118 at the front surface of each microelectronic element 112 and may overlie a portion the major surface 132 of the dielectric element 130 . In one example, as seen in FIGS. 1 and 2 , the encapsulant region 140 has a major surface 142 which is substantially parallel to the major surface 132 of the dielectric element. In particular cases, the encapsulant region of a given package can extend laterally outward beyond two or more edge surfaces of the microelectronic elements 112 in the package to corresponding remote surfaces of the package which are spaced apart from the edge surfaces of the microelectronic elements. In an example, the dielectric region 140 may be or may include a molded dielectric region. In one example, the dielectric region may comprise a polymeric dielectric material, or alternatively a polymeric dielectric material with a filler therein which may have a lower coefficient of thermal expansion than the polymeric material. In some examples, the filler may include particles, flakes or a mesh or scaffold of an inorganic material such as a glass, quartz, ceramic or semiconductor material, among others.

As mentioned above, all package interconnects of a package typically are available for connection at an interconnect region adjacent the same interconnect edge 138 of the package. As further seen in FIG. 1 , the package contacts 124 , 126 of a stacked microelectronic package 108 in the package stack, in turn, are electrically coupled to respective panel contacts 162 at a major surface 164 of a circuit panel 160 through an electrically conductive material 127 . It will be appreciated that the substantially parallel planes 134 , 116 defined by the major surface and front surfaces of the dielectric elements and microelectronic elements are oriented at a non-zero angle 168 to a plane 165 defined by the major surface 164 of the circuit panel. In one example, the angle 168 may be a greater than or equal to 10 degrees. In a particular example, the angle can be a substantial angle having a measure greater than or equal to 20 degrees. In another example, the angle 168 can be greater than or equal to 30 degrees. In another example, the angle 168 can be greater than or equal to 15 degrees. In yet another example, the angle 168 can be greater than or equal to 90 degrees, or in some cases, can be greater than or equal to 120 degrees. FIG. 1 shows an example in which the angle 168 has a measure equal or substantially equal to 90 degrees. In this case, the major surface 164 of the circuit panel faces edge surfaces 120 of each microelectronic element. An insulating layer 170 , which in some cases may be a mechanically reinforcing layer such as an underfill, may be applied surrounding the electrical connections between the package contacts 124 , 126 and the panel contacts 162 . In some cases, the insulating layer 170 can mechanically reinforce or stiffen such electrical connections and may help those electrical connections withstand stresses due to differential thermal expansion between the packages 108 and the circuit panel 130 . In one example, the insulating layer can be a “board level underfill layer.”

In particular examples, the electrically conductive material 127 may be conductive masses, conductive pillars, stud bumps or other suitable electrically conductive material may be used to electrically connect each of the package contacts 124 , 126 with a corresponding panel contact 162 . Here, the conductive material 127 can be in form of electrically conductive bumps such as masses of solder, tin, indium or eutectic material, or drops or droplets of electrically conductive polymer material or electrically conductive ink on surfaces of the panel contacts 162 and contacting the corresponding package contacts 124 , 126 . In one example, the electrically conductive material 127 may be applied to the panel contacts 162 , the package contacts 124 , 126 , or both the package contacts and the panel contacts through a transfer mold of solder bumps, balls or features, or application of solder balls, for example, or may alternatively be deposited on the substrate contacts by plating or depositing a metal or other conductive material. Alternatively, the electrically conductive material 127 can be applied by depositing one of the above-mentioned electrically conductive polymer or electrically conductive ink or other such material as disclosed in the incorporated U.S. Pat. No. 8,178,978.

In one example, the circuit panel can be a motherboard. In another example, the circuit panel 160 can be a daughter board, module board or other board or circuit panel configured for electrical connection within a system which includes the microelectronic package stack 110 and circuit panel. The panel contacts 162 can be configured for surface mounting to another component which can be a card, tray, motherboard, etc., such as via a land grid array (LGA), ball grid array (BGA), or other technique. As in the case of the dielectric element 130 , the circuit panel 160 may include a dielectric element or other substrate which may have one or multiple layers of dielectric material and one or multiple electrically conductive layers thereon. The circuit panel 160 can be formed of various materials, which may or may not include a polymeric component, and may or may not include an inorganic component. Alternatively, the circuit panel may be wholly or essentially polymeric or may be wholly or essentially inorganic. In various non-limiting examples, the support element can be formed of a composite material such as glass-reinforced epoxy, e.g., FR-4, a semiconductor material, e.g., Si or GaAs, or glass or ceramic material.

Referring to FIG. 3 et seq., stages in a method of fabricating a microelectronic assembly 100 will now be described. As seen in FIG. 3 , a package stack 110 comprises a plurality of microelectronic packages 108 , each having features as described above relative to FIGS. 1 and 2 . The microelectronic packages 108 in each package stack 110 can be thermally coupled between the major surface 142 of the encapsulant region 140 and the major surface 135 of a dielectric element 130 substantially parallel and adjacent thereto in the package stack. The thermally conductive adhesive or grease can act to spread heat among the microelectronic packages in the assembly, and may also help conduct heat from internal areas remote from exterior edges of the assembly to edges of each package 108 which lie a exterior surfaces (not shown) of the package stack 110 . FIG. 3 further illustrates the circuit panel 160 having the electrically conductive material 127 on the panel contacts 162 at the major surface 164 of the circuit panel. FIG. 4 further illustrates a layout of the packages 108 within the package stack, wherein the dashed lines therein represent the upwardly facing major surfaces 132 of the dielectric elements 130 of the respective packages 108 in the package stack 110 . FIG. 5 illustrates bumps of the electrically conductive material 127 at the major surface 164 of the circuit panel prior to assembly of the package stack 110 thereto.

FIG. 6 further shows the package stack 110 after the package contacts are coupled with the corresponding bumps of the electrically conductive material 127 at the major surface of the circuit panel.

FIG. 7 illustrates a microelectronic assembly 200 in accordance with an alternative configuration in which the package stack 210 includes microelectronic packages 108 and, in addition, a second package 208 which can be interconnected with the circuit panel in similar fashion as the microelectronic packages 108 . In one example, the second package 208 comprises a second dielectric element 230 and a second microelectronic element electrically coupled thereto having active devices thereon which implements a registered clock driver. The registered clock driver can be configured to regenerate signals received from a common signaling bus 172 , e.g., a command address bus, on the circuit panel 160 and to transmit such signals on to other packages 108 within the microelectronic assembly. For example, when individual packages 108 therein include microelectronic elements having memory storage arrays thereon, the second package 208 can be configured to receive one or more of clock, command and address signals from the circuit panel through the panel contacts 162 coupled thereto and then regenerate all or part of such signals. The microelectronic element of the second package 208 can regenerate signals and transmit the same to other packages 108 through others of the panel contacts 162 to which the second package 208 is coupled in the microelectronic assembly 200 .

FIG. 8 illustrates another variation in which package stacks 300 and 310 each similar to the package stacks 110 or 210 described above are coupled to respective panel contacts 162 , 262 at first and second oppositely-facing mounting surfaces 164 , 264 being major surfaces of the circuit panel 160 . At each mounting surface 164 , the first panel contacts 162 are arranged thereat in first and second transverse directions parallel to the mounting surface such that centers of adjacent ones of said first panel contacts are arranged at a minimum pitch or greater. Similarly, the second panel contacts 262 are arranged in first and second transverse directions parallel to the mounting surface such that centers of adjacent ones of said first panel contacts are arranged at a minimum pitch or greater. Referring to FIG. 9A , in a particular example, individual packages 108 of a first package stack 300 have columns 224 , 226 of package contacts at respective opposite surfaces of the dielectric element 130 of each microelectronic package, wherein package contacts 124 , 126 at the respective interconnect regions of each package are electrically coupled with the panel contacts 162 , 262 of the circuit panel. FIG. 9A also illustrates an example of signal assignments of the package contacts in each column 224 , 226 of package contacts 124 , 126 of each package 108 .

Conversely, individual packages 308 of a second package stack 310 mounted to the oppositely facing second mounting surface 264 have columns 234 , 236 of package contacts 124 , 126 at the respective interconnect regions of each package 308 . FIG. 9B also illustrates an example of signal assignments of the package contacts in each column 234 , 236 of package contacts 124 , 126 of each package 308 . As will be appreciated from a comparison of the column 226 of package contacts on the packages 108 with the corresponding column 236 on packages 308 , the signal assignments of the column 224 of package contacts in packages 108 are mirrored relative to the signal assignments of the column 234 of package contacts in packages 308 of the package stack 310 opposite thereto. In addition, the signal assignments of the column 226 of package contacts in packages 108 are mirrored relative to the signal assignments of the column 236 of package contacts in packages 308 of the package stack 310 opposite thereto. Specifically, the signal assignments of individual package contacts in a column 224 on a package 108 of the first package stack 300 are symmetric about a theoretical axis 250 relative to the signal assignments of individual package contacts in column 234 on a package 308 of the second package stack 310 , and the same relationship is true of the signal assignments in column 226 of a package 108 being mirrored relative to the signal assignments of package contacts in column 236 of a package 308 .

Accordingly, in the mirrored configuration, panel contacts 162 , 262 on the opposite surfaces of the circuit panel which are assigned to carry a given signal may be aligned within one minimum pitch of the panel contacts 162 with one another in first and second transverse directions which are parallel to the mounting surface 164 . As a result, the lengths of stubs which couple the microelectronic elements within the microelectronic packages 108 , 308 on opposite surfaces of the circuit panel to the signaling bus 172 can be shortened, because package contacts in column 224 of package contacts of a first package 108 are coincident with the package contacts in a corresponding column 234 of package contacts of a second package 308 in the package stack 310 which have the corresponding or identical signal assignment and thus are electrically coupled to a same conductor of the signaling bus. Reducing the lengths of the stubs which electrically interconnect corresponding package contacts of the microelectronic packages 108 , 308 coupled to an electrically conductive signaling path of a common signaling bus 172 (e.g., an address bus or command address bus) on the circuit panel 160 in this manner can mitigate adverse effects of loading due to the stubs on the quality of signals carried by the address bus or command address bus on the circuit panel. In such way, the total energy due to reflections in the stubs coupling the microelectronic elements in the package stacks 300 , 310 to the signaling bus 172 can be reduced.

In one example, the signal assignments of each package contact of a column 224 of package contacts which are configured to carry address signals on a package 108 are mirrored relative to the signal assignments of a column 234 of package contacts which are configured to carry address signals on a package 308 . In a further example, the signal assignments of each of the package contacts which are configured to carry a clock signal on a package 108 are mirrored relative to the signal assignments of each of the package contacts which are configured to carry a clock signal on a package 308 .

FIG. 9C illustrates a microelectronic assembly according to a variation of the embodiment seen in FIG. 8 . In this case, a package stack 410 has package contacts electrically coupled with the panel contacts 362 at second major surface 264 of the circuit panel at locations which are offset from locations at which the package contacts of a package stack 300 are electrically coupled with the panel contacts 162 . The spatial offset between package stacks 300 , 410 can help address electrical effects due to loading of stubs which electrically interconnect the microelectronic elements in each package with the signaling bus 172 .

FIG. 10 depicts yet another embodiment in which microelectronic packages 508 have microelectronic elements which, in addition to overlying major surface 132 of the dielectric element 130 , include microelectronic elements overlying the oppositely-facing major surface 135 of the dielectric element 130 .

FIG. 11 illustrates microelectronic assemblies in accordance with embodiments of the invention in which an assembly of microelectronic packages 110 A are staggered relative to another assembly of microelectronic packages 110 B, such as in a direction parallel to a direction of the plane defined by the major surface of the dielectric element of each package 108 therein.

FIG. 12 illustrates yet another embodiment in which a plurality of package stacks 110 D, 110 E, 110 F and 110 G which are arranged and mounted to corresponding panel contacts 162 at surface 164 of the circuit panel 130 . In this case, the package stacks 110 D, 110 E, . . . , are arranged in a pattern having a form of a pinwheel or flower. The pinwheel pattern may allow space for an additional component to be mounted to the circuit panel in area 175 of the surface 164 between the package stacks. In this case, first planes 135 defined by the first major surfaces of the first set of stacked packages can be parallel to first planes 145 defined by the first major surfaces of the third set of stacked packages, second planes 155 defined by the first major surfaces of the second set of stacked packages are parallel to second planes 165 defined by the first major surfaces of the fourth set of stacked packages. In addition, as seen in FIG. 12 , the first planes 135 intersect the second planes 155 and may also intersect the fourth planes 165 .

FIGS. 13, 14, 15, 16, 17 illustrate stages in a method of assembling a microelectronic assembly in accordance with an embodiment of the invention which additionally includes a thermally conductive heat spreader 604 contacting external surfaces of the package stack 110 . In one example, the heat spreader 604 can be made of a metal having high thermal conductivity, which may be copper, nickel or other suitable metal. In a particular fabrication example, the heat spreader can be formed by coating external surfaces of a portion of a package stack with an electrically conductive commoning layer or seed layer 602 as seen in FIG. 14 . For example, the seed layer 602 can be deposited by physical or chemical vapor deposition or electroless plating, and in one example can be performed while covering other portions of the external surfaces with removable film 603 , resist or other coating to avoid the seed layer from being deposited where not desired. The removable film, resist or other coating then is removed. Alternatively, the seed layer 602 can be deposited on all exposed surfaces and then portions of seed layer where the heat spreader 604 is to be formed are then covered with a removable film, resist or other removable coating, and then the seed layer 602 is removed from all areas that are not covered. The removable film, resist or other coating then is removed. As further seen in FIG. 15 , the heat spreader 604 then is formed such as by an electroplating process which selectively deposits a highly thermally conductive metal such as copper on the seed layer 602 overlying the external surfaces of the package stack 110 include a surface 606 which faces upwardly and surfaces 608 , 610 which face in opposite directions and extend away from the upwardly facing surface 606 . As further seen in FIG. 16 , the package stack having the heat spreader formed thereon now is assembled with the circuit panel in a manner such as described above relative to FIGS. 1-3 . FIG. 17 further illustrates the heat spreader as seen from above the package stack 110 , with the heat spreader overlying external surfaces 608 , 610 of the package stack as seen in FIG. 15 , and the heat spreader also overlying external surfaces 612 , 614 of the package stack which extend between the external surfaces 608 , 610 .

In accordance with yet another variation, FIGS. 18, 19, 20, and 21 depict the assembly of microelectronic packages 108 with a heat spreader 704 ( FIG. 19 ) having slots 706 sized to accommodate individual packages 108 . In this case, the heat spreader includes a thermally conductive plane 708 disposed between a first microelectronic package 108 and a second microelectronic package 108 adjacent to the first microelectronic package in the stacked microelectronic assembly.

As seen in FIGS. 18-19 , the packages 108 can be inserted into the slots 706 to form a subassembly 710 ( FIG. 19 ) prior to electrically connecting the packages 108 with the circuit panel as depicted in FIGS. 20 and 21 .

FIG. 22 depicts a microelectronic assembly according a variation of the embodiment shown in FIG. 18 in which the heat spreader 804 additionally includes fins 812 to further enhance heat dissipation from the assembly in operation of the assembly in an electronic system.

Although not specifically shown in the Figures or particularly described in the foregoing, elements in the various Figures and various described embodiments can be combined together in additional variations of the invention.