Inventor

Zhuowen Sun

Inventor

Campbell, CA, US

Overview

2013–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 42 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%

H01LSemiconductor devices36%

G11CStatic stores10%

H05KPrinted circuits6%

H10DInorganic electric semiconductor devices5%

G06FElectric digital data processing2%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

H01FMagnets1%

PatentTitleYear

10,700,002Ultra high performance interposer2020 10,559,537Wire bond wires for interference shielding2020 10,522,457Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates2019 10,354,976Dies-on-package devices and methods therefor2019 10,332,833Ultra high performance interposer2019 10,325,877Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces2019 10,177,086Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates2019 10,115,678Wire bond wires for interference shielding2018 10,103,093Via structure for signal equalization2018 10,032,715Ultra high performance interposer2018 10,026,467High-bandwidth memory application with controlled impedance loading2018 10,007,622Method for reduced load memory module2018 9,991,233Package-on-package devices with same level WLP components and methods therefor2018 9,991,235Package on-package devices with upper RDL of WLPS and methods therefor2018 9,984,992Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces2018 9,985,007Package on-package devices with multiple levels and methods therefor2018 9,972,573Wafer-level packaged components and methods therefor2018 9,972,609Package-on-package devices with WLP components with dual RDLs for surface mount dies and methods therefor2018 9,947,618Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates2018 9,928,883'TFD I/O partition for high-speed, high-density applications'2018 9,905,507'Circuit assemblies with multiple interposer substrates, and methods of fabrication'2018 9,812,402'Wire bond wires for interference shielding'2017 9,728,524'Enhanced density assembly having microelectronic packages mounted at substantial angle to board'2017 9,691,702'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'2017 9,691,437'Compact microelectronic assembly having reduced spacing between controller and memory packages'2017 9,679,613'TFD I/O partition for high-speed, high-density applications'2017 9,666,521'Ultra high performance interposer'2017 9,640,236'Reduced load memory module using wire bonds and a plurality of rank signals'2017 9,640,282'Flexible I/O partition of multi-die memory solution'2017 9,595,511'Microelectronic packages and assemblies with improved flyby signaling operation'2017 9,583,417'Via structure for signal equalization'2017 9,490,222'Wire bond wires for interference shielding'2016 9,484,080'High-bandwidth memory application with controlled impedance loading'2016 9,460,758'Single package dual channel memory with co-support'2016 9,402,312'Circuit assemblies with multiple interposer substrates, and methods of fabrication'2016 9,397,038'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'2016 9,349,707'Contact arrangements for stackable microelectronic package structures with multiple ranks'2016 9,343,398'BGA ballout partition techniques for simplified layout in motherboard with multiple power supply rail'2016 9,337,170'Contact arrangements for stackable microelectronic package structures'2016 9,281,296'Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design'2016 9,070,423'Single package dual channel memory with co-support'2015 8,358,193'Planar inductor devices'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013Patents assigned to DALMIA SIDHARTH (1)· patent assignee history

2013Patents assigned to KUBES STEVEN R (1)· patent assignee history

2013Patents assigned to SUN ZHUOWEN (1)· patent assignee history

2013Patents assigned to TYCO ELECTRONICS CORP (1)· patent assignee history

2013Based in Sacramento, CA, US· patent location history

2015–2020Patents assigned to INVENSAS CORP (41)· patent assignee history

2015–2020Based in Campbell, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INVENSAS CORP	41	2015–2020
DALMIA SIDHARTH	1	2013
KUBES STEVEN R	1	2013
SUN ZHUOWENself	1	2013
TYCO ELECTRONICS CORP	1	2013

Locations

Location	Patents	Span
Campbell, California, US	41	2015–2020
Sacramento, California, US	1	2013