System and method for controlling common mode voltage via replica circuit and feedback control

Aspects of the present disclosure relate generally to common mode voltage control, and in particular, to a system and method for controlling common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control.

Differential signal processing circuits, such as variable gain amplifiers (VGAs) and continuous time linear equalizers (CTLEs), receive and apply a particular frequency-dependent gain to an input differential signal to generate an output differential signal. The input differential signal is typically received at control terminals (e.g., gates) of input transistors (e.g., field effect transistors (FETs)), and the output differential signal are generated at other terminals (e.g., drains) of the input transistors.

The effective direct current (DC) voltage level of a differential signal is generally referred to as the common mode voltage. The common mode voltage is generally the average voltage between the voltage levels of the positive and negative components of the differential signal. The common mode voltage affects the operating point of the devices to which the differential signal is applied. If the common mode voltage varies, the operating point of the devices varies, which may have undesirable consequences.

In the context of a differential signal processing circuit, the input differential signal applied to the input transistors may have a common mode voltage that varies for a number of reasons. The gain applied to the input differential signal by the differential signal processing circuit results in an output differential signal that has a common mode voltage that varies with the common mode voltage of the input differential signal. In addition, process variation of the differential signal processing circuit itself creates significant common mode voltage variation. As a result, the input transistors are subjected to varying common mode voltage levels, which has the adverse consequence of reducing gain and peaking control for the differential signal processing circuit. Additionally, the varying common mode voltage of the output differential signal may adversely affect the operation of one or more devices downstream of the differential signal processing circuit.

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

An aspect of the disclosure relates to an apparatus for generating a first output differential signal having a controlled common mode voltage. The apparatus includes a first differential signal processing circuit configured to generate a first output differential signal based on an input differential signal. The first differential signal processing circuit includes first and second load devices; first and second input transistors including first and second control terminals configured to receive first and second components of the input differential signal, respectively; first and second current-source transistors coupled in series with the first and second load devices and the first and second input transistors between a first voltage rail and a second voltage rail, respectively; wherein first and second components of the first output differential signal are configured to be generated at first and second nodes between the first and second load devices and the first and second input transistors, respectively. The apparatus further includes a first control circuit configured to control a first output common mode voltage of the first output differential signal by generating a first bias voltage for control terminals of the first and second current-source transistors from an input common mode voltage of the input differential signal.

Another aspect of the disclosure relates to a method for generating a first output differential signal having a controlled common mode voltage. The method includes applying first and second components of an input differential signal to first and second control terminals of first and second input transistors of a first differential signal processing circuit, respectively; generating first and second components of a first output differential signal at first and second nodes between first and second load devices and the first and second input transistors, respectively; and controlling a first common mode voltage of the first output differential signal including generating a first bias voltage for control terminals of first and second current-source transistors coupled in series with the first and second load devices and the first and second input transistors between first and second voltage rails, respectively, wherein the first bias voltage is generated from an input common mode voltage of the input differential signal.

Another aspect of the disclosure relates to an apparatus for generating a first output differential signal having a controlled common mode voltage. The apparatus includes means for applying first and second components of an input differential signal to first and second control terminals of first and second input transistors of a first differential signal processing circuit, respectively; means for generating first and second components of a first output differential signal at first and second nodes between first and second load devices and the first and second input transistors, respectively; and means for controlling a first common mode voltage of the first output differential signal including generating a first bias voltage for control terminals of first and second current-source transistors coupled in series with the first and second load devices and the first and second input transistors between first and second voltage rails, respectively, wherein the first bias voltage is generated from an input common mode voltage of the input differential signal.

To the accomplishment of the foregoing and related ends, the one or more embodiments include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the description embodiments are intended to include all such aspects and their equivalents.

FIG. 1 illustrates a schematic diagram of an exemplary receiver including a variable gain amplifier (VGA) with a common mode voltage control circuit in accordance with an aspect of the disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary receiver including a continuous time linear equalizer (CTLE) with a common mode voltage control circuit in accordance with another aspect of the disclosure.

FIG. 3 illustrates a schematic diagram of an exemplary receiver including a VGA cascaded with a CTLE in accordance with another aspect of the disclosure.

FIG. 4 illustrates a schematic diagram of another exemplary receiver including a VGA cascaded with a CTLE in accordance with another aspect of the disclosure.

FIG. 5 illustrates a schematic diagram of another exemplary receiver including a VGA cascaded with a CTLE in accordance with another aspect of the disclosure.

FIG. 6 illustrates a schematic diagram of another exemplary receiver including a VGA with a common mode voltage control circuit in accordance with another aspect of the disclosure.

FIG. 7 illustrates a schematic diagram of another exemplary receiver including a CTLE with a common mode voltage control circuit in accordance with another aspect of the disclosure.

FIG. 8 illustrates a schematic diagram of another exemplary receiver including a VGA cascaded with a CTLE in accordance with another aspect of the disclosure.

FIG. 9 illustrates a schematic diagram of another exemplary receiver including a VGA cascaded with a CTLE in accordance with another aspect of the disclosure.

FIG. 10 illustrates a schematic diagram of another exemplary receiver including a VGA cascaded with a CTLE in accordance with another aspect of the disclosure.

FIG. 11 illustrates a flow diagram of an exemplary method of controlling a common mode voltage of an output signal of a differential signal processing circuit in accordance with another aspect of the disclosure.

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

For differential signal processing circuits, such as voltage gain amplifiers (VGAs) and continuous time linear equalizers (CTLEs), control of the common mode voltage (effective direct current (DC) voltage level) at the outputs of these circuits is desirable to achieve tight gain and peaking control for the circuits, and to provide proper common mode voltage levels for other downstream circuits. However, the common mode voltage of an input differential signal to these circuits may be subject to variation. In addition, process variation of the devices in the VGA and CTLE create significant common mode voltage variation. If not compensated, the varying common mode voltage and the process variation affect the common mode voltage of the output differential signal, which may result in reduced gain and peaking control for the differential signal processing circuits.

FIG. 1 illustrates a schematic diagram of an exemplary receiver 100 including a variable gain amplifier (VGA) 105 in accordance with an aspect of the disclosure. The VGA 105 is an example of a differential signal processing circuit. In particular, the VGA 105 is configured to amplify an input differential signal (VIP and VIN) with a certain gain-frequency response to generate an output differential signal (VOP and VON).

As indicated, the gain of the VGA 105 may be configured to be frequency dependent, whereby, in this example, the gain may be substantially flat over a particular lower frequency range and peaks over a particular higher frequency range. The receiver 100 including the VGA 105 may be employed at a front-end of an integrated circuit (IC) to receive and amplify the input differential signal to compensate for high frequency attenuation due to propagation via a transmission medium.

As discussed in more detail herein, the receiver 100 includes a control circuit 110 configured to control a common mode voltage of the output differential signal (VOP and VON). In summary, the control circuit 110 generates a bias voltage NBIAS applied to control terminals of current-source transistors for controlling the currents I through these transistors. The common mode voltage of the output differential signal (VOP and VON) is a function of the current I through these transistors. For example, the output common mode voltage VOCM may be approximated as:

Where VDD is the supply voltage at a first voltage rail, I is the current through each of the current-source transistors, and RL is the resistance of each of the load devices, as discussed in more detail below. The control circuit 110 uses a replica circuit configured similar to one side of the VGA 105 for generating the bias voltage NBIAS based on a common mode voltage of the input differential signal (VIP and VIN).

In particular, the VGA 105 includes a first load device RL 1 (e.g., a resistor), a first input transistor M 11 (e.g., an n-channel metal oxide semiconductor (NMOS) field effect transistor (FET) (referred to herein as “NMOS”)), and a first current-source transistor M 21 (e.g., an NMOS) coupled in series between a first voltage rail (VDD) and a second voltage rail (VSS) (e.g., ground). The VGA 105 further includes a second load device RL 2 (e.g., a resistor), a second input transistor M 12 (e.g., an NMOS), and a second current-source transistor M 22 (e.g., an NMOS) coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS).

For gain and frequency response adjustment, the VGA 105 includes one or more variable capacitors CS coupled in series between the respective lower terminals (e.g., sources) of the input transistors M 11 and M 12 , and one or more variable resistors RS coupled in series between the respective lower terminals (e.g., sources) of the input transistors M 11 and M 12 . In general, the one or more resistors RS set the low frequency gain for the VGA 105 and the one or more capacitors CS provide gain peaking at higher frequency in order to compensate for high frequency attenuation of the input differential signal (VIP and VIN) as a result of propagating via a transmission medium.

As indicated, the input differential signal includes a positive component VIP and a negative component VIN, which are applied to the control terminals (e.g., gates) of the input transistors M 12 and M 11 via alternating current (AC)-coupling capacitors C 12 and C 11 , respectively. The VGA 105 generates an output differential signal including positive and negative components VOP and VON at nodes between the first and second load devices RL 1 and RL 2 and the input transistors M 11 and M 12 , respectively.

The control terminals (e.g., gates) of the current-source transistors M 21 and M 22 are coupled together, and configured to receive a bias voltage NBIAS for setting the current I through each of the transistors M 21 and M 22 . The control circuit 110 is configured to generate the bias voltage NBIAS to set and control (e.g., regulate) the common mode voltage VOCM of the output differential signal VOP and VON, as discussed further herein.

The control circuit 110 includes a replica circuit 120 having a replica load device RL R (e.g., a resistor), a replica input transistor M 1 R (e.g., an NMOS), and a replica current-source transistor M 2 R (e.g., an NMOS) coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS). The replica load resistor RL R , replica input transistor M 1 R , and replica current-source transistor M 2 R may be replicated substantially the same as or scaled versions of the load device RL 1 or RL 2 , input transistor M 11 or M 12 , and current-source transistor M 21 or M 22 , respectively. Accordingly, the replica circuit 120 is configured similar to one side of the VGA 105 .

More specifically, the replica circuit 120 may be configured to generate a replica current I R being substantially the same or a scaled version of the current I through the current-source transistor M 11 or M 12 . For reduced power consumption purposes, the replica current I R may be proportional to the current I by a defined ratio R being less than one (1) (e.g., R=1/10, where I R =R*I). To effectuate this ratio R, the replica load device RL R may be configured to have a resistance R R proportional to the resistance RL of each of the first or second load device RL 1 or RL 2 (e.g., R R =1/R*RL). Further, the input replica transistor M 1 R may be configured to have a channel width W R1 that is proportional to the channel width W 1 of each of the input transistor M 11 or M 12 by the defined ratio R (e.g., W R1 =R*W 1 ). Similarly, the replica current-source transistor M 2 R may be configured to have a channel width W R2 that is proportional to the channel width W 2 of each of the current-source transistor M 21 or M 22 by the defined ratio R (e.g., W R2 =R*W 2 ).

The common mode voltage VICM of the input differential signal VIP and VIN is taken off a node between resistors R 1 and R 2 coupled in series between the control terminals (e.g., gates) of the inputs transistors M 12 and M 11 , respectively. The resistors R 1 and R 2 may serve as a termination impedance (e.g., 50Ω) for the input of the VGA 105 . To adjust the input common mode voltage VICM of the input differential signal to be closer to a desired value, another pair of resistors R 3 and R 4 may be coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS), where the node between the resistors R 3 and R 4 is coupled to the node between resistors R 1 and R 2 .

The common mode voltage VICM of the input differential signal VIP and VIN is applied to the control terminal (e.g., gate) of the replica input transistor M 1 R . This replicates the input differential signal VIP and VIN being applied to the control terminals (e.g., gates) of the input transistors M 12 and M 11 of the VGA 105 . As the output differential signal VOP and VON is generated at the upper terminals (e.g., drains) of input transistors M 11 and M 12 , a replica output common mode voltage VOCM R is generated at the corresponding upper terminal (e.g., drain) of the replica input transistor M 1 R . The replica circuit 120 being a replica or scaled version of one side of the VGA 105 (and having the same bias voltage NBIAS applied to the corresponding current-source transistor, as discussed below) results in the replica output common mode voltage VOCM R being substantially the same as the common mode voltage VOCM of the output differential signal VOP and VON.

The control circuit 110 further includes a voltage divider having resistors R 5 and R 6 coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS). The respective resistances of the resistors R 5 and R 6 are configured to set a target output common mode voltage VOCM T for the output differential signal VOP and VON of the VGA 105 .

Additionally, the control circuit 110 includes a differential (operational) amplifier A 1 having a first input (e.g., negative) configured to receive the target output common mode voltage VOCM T . The differential amplifier A 1 includes a second input (e.g., positive) configured to receive the replica output common mode voltage VOCM R generated at the upper terminal (e.g., drain) of the replica input transistor M 1 R . The differential amplifier A 1 includes an output coupled to the control terminals (e.g., gates) of the current-source transistors M 21 and M 22 , and to the control terminal (e.g., gate) of the replica current-source transistor M 2 R .

Thus, by feedback control, the differential amplifier A 1 generates the bias voltage NBIAS to cause the replica output common mode voltage VOCM R to be substantially the same as the target common mode voltage VOCM T . Since the replica output common mode voltage VOCM R is substantially the same as the common mode voltage VOCM of the output differential signal VOP and VON of the VGA 105 , the bias voltage NBIAS causes (e.g., controls or regulates) the common mode voltage VOCM of the output differential signal to be substantially the same as the target common mode voltage VOCM T .

Accordingly, since the common mode voltage VOCM of the output differential signal VOP and VON of the VGA 105 is controlled or regulated (e.g., substantially constant), the upper terminals (e.g., drains) of the input transistors M 1 l and M 12 operate around a substantially constant and desired effective DC voltage level. This results in the VGA 105 exhibiting tight gain and peaking control. The controlled output common mode voltage VOCM of the output differential signal VOP and VON may also provide appropriate input signal levels for one or more downstream stages.

The technique of using the common mode voltage control circuit 110 may be applied to other types of differential signal processing circuits, such as continuous time linear equalizers (CTLEs), as discussed as follows.

FIG. 2 illustrates a schematic diagram of an exemplary receiver 200 including a continuous time linear equalizer (CTLE) 205 with a common mode voltage control circuit 210 in accordance with another aspect of the disclosure. The CTLE 205 is another example of a differential signal processing circuit. Thus, it shall be understood that in addition to the VGA 105 and the CTLE 205 , the common mode control circuits described herein may be applied to other types of differential signal processing circuit.

Similar to the VGA 105 , the CTLE 205 is configured to receive an input differential signal (VIP and VIN) and perform more extensive programmable equalization of the input differential signal to generate an output differential signal (VOP and VON). The control circuit 210 is similar to that of control circuit 110 , except that it includes a replica circuit 220 that is different because the CTLE 205 is different than the VGA 105 . In other words, the replica circuit 220 replicates the elements of the CTLE 205 , whereas the replica circuit 110 replicates the elements of the VGA 105 .

In particular, the CTLE 205 includes positive-side sets of selectable parallel active load devices M 31 a , M 31 b , M 41 a , and M 41 b (transistors). For simplicity purposes, only one set (M 31 a , M 31 b , M 41 a , and M 41 b ) is shown. As shown, the devices are configured as p-channel metal oxide semiconductor (PMOS) FETs (referred to herein as “PMOS”). The upper transistors M 31 a and M 32 b operate as switches to effectively place a selected one of the lower transistors M 41 a and M 41 b as a load device for the CTLE 205 . The transistors M 31 a and M 41 a are coupled in series between the first voltage rail (VDD) and the drain of input transistor M 51 . Similarly, the transistors M 31 b and M 41 b are coupled in series between the first voltage rail (VDD) and the drain of input transistor M 51 . The transistor M 41 a is diode-connected with a resistor R 11 coupled between its gate and drain. The transistor M 41 b is diode-connected without a resistor.

One bit of a select signal PK<0:7> is applied to the gate of transistor M 31 a and a corresponding bit of a complementary select signal PKN<0:7> is applied to the gate of transistor M 31 b . If the bit applied to the gate of transistor M 31 a is asserted (e.g., at VSS) and the bit applied to gate of transistor M 31 b is not asserted (e.g., at VDD), transistor M 31 a is turned on and transistor M 31 b is turned off. Accordingly, VDD is applied to transistor M 41 a via the turned-on transistor M 31 a , thereby configuring the diode-connected transistor M 41 a as a load to the positive-side of the CTLE 205 ; and VDD is not applied to transistor M 41 b due to the turned-off transistor M 31 b , thereby not configuring the diode-connected transistor M 41 b as a load to the positive-side of the CTLE 205 . Similarly, if the bit applied to the gate of transistor M 31 a is not asserted (e.g., at VDD) and the bit applied to the gate of transistor M 31 b is asserted (e.g., at VSS), then, as above, the diode-connected transistor M 41 b is configured as a load device and the diode-connected transistor M 41 a is not configured as a load device for the positive-side of the CTLE 205 .

At lower frequencies, the impedances of the diode-connected transistors M 41 a and M 41 b (with resistor R 11 ) are approximately the same. Thus, for lower frequencies, configuring either one of the diode-connected transistors M 41 a and M 41 b as a load by turning a corresponding one of the switch transistors M 31 a and M 31 b does not significantly affect the gain of the CTLE 205 . However, at higher frequencies, the impedance of the diode-connector transistor M 41 a is higher than the impedance of diode-connected transistor M 41 b due to the resistor R 11 . Accordingly, configuring transistor M 41 a as a load device by turning on transistor M 31 a (and not configuring transistor M 41 b as a load device by turning off transistor M 31 b ), produces a higher gain or peaking for the CTLE 205 , as compared to configuring transistor M 41 b as a load device by turning on transistor M 31 b (and not configuring transistor M 41 a as a load device by turning off transistor M 31 a ). Since, in this example, there are eight (8) sets of parallel active load devices, the CTLE 205 may be tuned for a desired high frequency peaking via control signals PK<0:7> and PKN<0:7>.

Similarly, the CTLE 205 includes negative-side sets of selectable parallel active load devices M 32 a , M 32 b , M 42 a , and M 42 b (e.g., PMOS transistors). For simplicity purposes, only one set (M 32 a , M 32 b , M 42 a , and M 42 b ) is shown. Each set of selectable active load devices M 32 a , M 32 b , M 42 a (with resistor R 21 ), and M 42 b are coupled between the first voltage rail (VDD) and the drain of input transistor M 52 , and may be configured substantially the same and operate in substantially the same manner (via the signals PK<0:7> and PKN<0:7>) as the set of load devices M 31 a , M 31 b , M 41 a (with resistor R 11 ), and M 41 b of the positive-side, such that the positive-side and the negative-side of the CTLE 205 are configured with substantially the same load impedance.

The CTLE 205 includes an input transistor M 51 (e.g., an NMOS) and a current-source transistor M 61 (e.g., an NMOS) coupled in series between the positive-side sets of selectable active load devices (collectively referred to as M 41 a and M 41 b ) and a second voltage rail (VSS) (e.g., ground). Similarly, the CTLE 205 includes another input transistor M 52 (e.g., an NMOS) and another current-source transistor M 62 (e.g., an NMOS) coupled in series between the negative-side sets of active load devices (collectively referred to as M 42 a and M 42 b ) and the second voltage rail (VSS).

The CTLE 205 includes additional circuitry for setting the gain-frequency response (e.g., with a high frequency resonance) of the CTLE, which includes selectable switches MS 1 -MS 3 (e.g., PMOS transistors) via corresponding select signals FB<0:2>, and corresponding capacitors CF for both the positive- and negative-sides of the CTLE. Additionally, the CTLE 205 may include neutralizing capacitors CZ cross-coupled between the upper terminals (e.g., drains) and control terminal (e.g., gates) of input transistors M 51 and M 52 , respectively. The neutralizing capacitors CZ serve to improve the input impedance matching of the CTLE 205 to reduce reflections of the input differential signal off the control terminals (e.g., gates) of the input transistors M 51 and M 52 , and to also reduce noise.

An input differential signal including positive and negative components VIP and VIN are applied to the control terminals (e.g., gates) of the input transistors M 52 and M 51 via AC-coupling capacitors C 12 and C 11 , respectively. The CTLE 205 is configured to generate an output differential signal including positive and negative components VOP and VON at the upper terminals (e.g., drains) of the input transistors M 51 and M 52 , respectively. The outputs (e.g., at drains of input transistors M 51 and M 52 ) may be coupled to a downstream device, such as a sampler/slicer. The capacitors CL shown in respective dashed boxes represent the load capacitances coupled to the outputs of the CTLE 205 , which may include the input capacitances of the downstream device. The control terminals (e.g., gates) of the current-source transistors M 61 and M 62 are coupled together, and configured to receive a bias voltage NBIAS generated by the common mode voltage control circuit 210 .

The control circuit 210 includes a replica circuit 220 , a differential (operational) amplifier A 1 , and a voltage divider including resistors R 5 and R 6 coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS). The respective resistances of the resistors R 5 and R 6 are configured to generate a target output common mode voltage VOCM T for the output differential signal VOP and VON of the CTLE 205 at the node between the resistors R 5 and R 6 .

The replica circuit 220 replicates an identical or scaled version of one side of the CTLE 205 . For instance, the replica circuit 220 includes a replica switch device M 3 R (e.g., PMOS), a replica load (diode-connected) transistor M 4 R (e.g., PMOS), a replica input transistor M 5 R (e.g., NMOS), and a replica current-source transistor M 6 R (e.g., NMOS) coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS). The replica devices M 3 R , M 4 R , M 5 R , and M 6 R may be substantially the same or scaled versions of one switch device M 31 a , M 31 b , M 32 a , or M 32 b , one load (diode-connected) transistor M 41 b or M 42 b , one input transistor M 51 or M 52 , and one current-source transistor M 61 or M 62 , respectively.

More specifically, the replica circuit 220 may be configured to generate a replica current I R being substantially the same or a scaled version of the current I through the current-source transistor M 61 or M 62 . For reduced power consumption purposes, the replica current I R may be proportional to the current I by a defined ratio R being less than one (1) (e.g., R=1/10, where I R =R*I). To effectuate this ratio R, the replica load device M 3 R may be configured to have a channel width W R3 that is proportional to the channel width W 3 of one switch device M 31 a , M 31 b , M 32 a , or M 32 b by the defined ratio R (e.g., W R3 =R*W 3 ). Similarly, the replica load (diode-connected) transistor M 4 R may be configured to have a channel width W R4 that is proportional to the channel width W 4 of one diode-connected transistor M 41 b or M 42 b by the defined ratio R (e.g., W R4 =R*W 4 ). Further, the input replica transistor M 5 R may be configured to have a channel width W R5 that is proportional to the channel width W 5 of one input transistor M 51 or M 52 by the defined ratio R (e.g., W R5 =R*W 5 ). Similarly, the replica current-source transistor M 6 R may be configured to have a channel width W R6 that is proportional to the channel width W 6 of one current-source transistor M 61 or M 62 by the defined ratio R (e.g., W R6 =R*W 6 ).

Similarly, the input to the CTLE 205 includes a set of resistors R 1 -R 4 configured to generate a common mode voltage VICM of the input differential signal VIP and VIN. The input common mode voltage VICM is applied to the replica input transistor M 5 R . A voltage VSS, being substantially the same as the voltage at the first voltage rail (VSS), is applied to the control terminal (e.g., gate) of the replica switch device M 3 R to replicate the turning on of at least one of the switch device M 31 a , M 31 b , M 32 a , or M 32 b . The replica circuit 220 being a replica or scaled version of one side of the CTLE 205 (and having the same bias voltage NBIAS applied to the corresponding current-source transistor, as discussed below) results in the replica output common mode voltage VOCM R at the upper terminal (e.g., drain) of the replica input transistor M 5 R being substantially the same as the common mode voltage VOCM of the output differential signal VOP and VON.

The differential amplifier A 1 includes a first (e.g., negative) input configured to receive the target common mode voltage VOCM T for the CTLE 205 , a second (e.g., positive) input configured to receive the replica output common mode voltage VOCM R , and an output coupled to the control terminals (e.g., gates) of the current-source transistors M 61 and M 62 of the CTLE 205 , and to the control terminal (e.g., gate) of the replica current-source transistor M 6 R .

Through feedback control, the differential amplifier A 1 generates the bias voltage NBIAS to cause the replica output common mode voltage VOCM R to be substantially the same as the target common mode voltage VOCM T . Since the replica output common mode voltage VOCM R is substantially the same as the common mode voltage VOCM of the output differential signal VOP and VON of the CTLE 205 , the common mode voltage VOCM of the output differential signal is controlled to be substantially the same as the target common mode voltage VOCM T . Again, this ensures tight gain and peaking control for the CTLE 205 , and provides an appropriate common mode voltage level for one or more downstream stages.

FIG. 3 illustrates a schematic diagram of an exemplary receiver 300 including the VGA 105 cascaded with the CTLE 205 in accordance with another aspect of the disclosure. The receiver 300 includes the VGA common mode voltage control circuit 110 slightly modified to effectuate the cascading of the VGA 105 with the CTLE 205 . Similarly, the receiver 300 includes the CTLE common mode voltage control circuit 210 slightly modified also to effectuate the cascading of the VGA 105 with the CTLE 205 .

In particular, the VGA 105 is configured to generate a first output differential signal VOP 1 and VON 1 by applying a frequency-dependent gain to the input differential signal VIP and VIN. The positive component VOP 1 and negative component VON 1 of the first output differential signal are applied to the control terminals (e.g., gates) of the input transistors M 52 and M 51 of the CTLE 205 , respectively.

As in receiver 100 , the common mode voltage VICM of the input differential signal VIP and VIN is applied to the control terminal (e.g., gate) of the replica input transistor M 1 R of the replica circuit 120 of the VGA common mode voltage control circuit 110 . The differential amplifier A 1 generates a bias voltage NBIAS 1 applied to the control terminal (e.g., gate) of replica current-source transistor M 2 R of the replica circuit 120 and the control terminals (e.g., gates) of current-source transistors M 21 and M 22 of the VGA 105 . The differential amplifier A 1 includes a first input (e.g., positive) configured to receive a first replica output common mode voltage VOCM 1 R from the upper terminal (e.g., drain) of the replica input transistor M 1 R . The differential amplifier A 1 includes a second input (e.g., negative) configured to receive a first target output common mode voltage VOCM 1 T from voltage divider R 5 /R 6 .

The differential amplifier A 1 controls a replica current I R1 flowing through the replica load device RL R , replica input transistor M 1 R , and replica current-source transistor M 2 R via the bias voltage NBIAS 1 to cause the first replica common mode voltage VOCM 1 R to be substantially the same as the first target output common mode voltage VOCM 1 T . By virtual of the fact that the replica circuit 120 is identical or a scaled version of one side of the VGA 105 , the current I 1 through the current-source transistors M 21 and M 22 is substantially the same or a multiplication factor greater than the replica current I R1 . As such, the first replica output common mode voltage VOCM 1 R is substantially the same as the first common mode voltage VOCM 1 of the first output differential signal VOP 1 and VON 1 . Since VOCM 1 R is substantially the same as VOCM 1 T , the control circuit 110 controls the first common mode voltage VOCM 1 of the first differential output signal VOP 1 and VON 1 to be substantially the same as the first target output common mode voltage VOCM 1 T .

The CTLE 205 is configured to generate a second output differential signal VOP 2 and VON 2 by applying a frequency-dependent gain to the first output differential signal VOP 1 and VON 1 from the VGA 105 . Although not shown, the second output differential signal VOP 2 and VON 2 may be applied to a sampler/slicer for converting the second output differential signal into a digital signal for further processing downstream.

As the first output differential signal VOP 1 and VON 1 of the VGA 105 is applied to the input of the CTLE 205 , the first replica common mode voltage VOCM 1 R is applied to the control terminal (e.g., gate) of the replica input transistor M 5 R of the replica circuit 220 of the CTLE common mode control circuit 210 . Similarly, the control circuit 210 includes a differential amplifier A 2 that generates a bias voltage NBIAS 2 applied to the control terminal (e.g., gate) of replica current-source transistor M 6 R of the replica circuit 220 and the control terminals (e.g., gates) of current-source transistors M 61 and M 62 of the CTLE 205 . The differential amplifier A 2 includes a first input (e.g., positive) configured to receive a second replica output common mode voltage VOCM 2 R from the upper terminal (e.g., drain) of the replica input transistor M 5 R . The differential amplifier A 2 includes a second input (e.g., negative) configured to receive a second target output common mode voltage VOCM 2 T from a voltage divider R 7 /R 8 .

Through feedback control, the differential amplifier A 2 controls a replica current I R2 flowing through the replica switch device M 3 R , replica load (diode-connected) transistor M 4 R , replica input transistor M 5 R , and replica current-source transistor M 6 R via the bias voltage NBIAS 2 to cause the second replica common mode voltage VOCM 2 R to be substantially the same as the second target output common mode voltage VOCM 2 T . By virtual of the fact that the replica circuit 220 is identical to or a scaled version of one side of the CTLE 205 , the current I 2 through the current-source transistors M 61 and M 62 is substantially the same as or a multiplication factor greater than the replica current I R2 . As such, the second replica output common mode voltage VOCM 2 R is substantially the same as the common mode voltage VOCM 2 of the second output differential signal VOP 2 and VON 2 . Since VOCM 2 R is substantially the same as VOCM 2 T , the control circuit 210 controls the common mode voltage VOCM 2 of the second differential output signal VOP 2 and VON 2 to be substantially the same as the second target output common mode voltage VOCM 2 T .

FIG. 4 illustrates a block diagram of another exemplary receiver 400 including the VGA 105 cascaded with the CTLE 205 in accordance with another aspect of the disclosure. The receiver 400 is a variation of receiver 300 . A difference between receiver 400 and receiver 300 is that the first target common mode voltage VOCM 1 T (and not the first replica common mode voltage VOCM 1 R ) is applied to the control input (e.g., gate) of the replica input transistor M 5 R of the replica circuit 220 of the common mode voltage control circuit 210 for the CTLE 205 .

The reason for this is that the control variation of the first replica common mode voltage VOCM 1 R may affect the control operation of the common mode voltage control circuit 210 . As the first target common mode voltage VOCM 1 T is substantially constant (and is substantially the same as the first replica common mode voltage VOCM 1 R ), it will not adversely affect the control operation of the common mode voltage control circuit 210 .

FIG. 5 illustrates a block diagram of yet another exemplary receiver 500 including the VGA 105 cascaded with the CTLE 205 in accordance with another aspect of the disclosure. The receiver 500 is also a variation of receiver 300 . A difference between receiver 500 and receiver 300 is that the supply voltages for the VGA replica circuit 120 , the VGA voltage divider R 5 /R 6 , the CTLE replica circuit 220 , and the CTLE voltage divider R 7 /R 8 are “cleaner” (less noisy) bandgap reference voltages. This may improve the power supply noise rejection for the VGA 105 and the CTLE 205 .

In particular, bandgap reference voltage VBG 1 for the VGA replica circuit 120 and the CTLE replica circuit 220 should be at substantially the same potential as VDD so that the replica circuits receive the same supply voltage level as the VGA 105 and CTLE 205 , respectively. The bandgap reference voltages VBG 2 and VBG 3 for the voltage dividers R 5 /R 6 and R 7 /R 8 could be substantially the same or different than the same potential as VDD.

FIG. 6 illustrates a receiver 600 including a “p-version” of a VGA 605 and a common mode voltage control circuit 610 for setting (e.g., controlling or regulating) the common mode voltage VOCM of an output differential signal VOP and VON of the VGA 605 . The VGA 605 is a p-version because it includes PMOS as input transistors and current-source transistors, and it is flipped up-side-down as compared to the “n-version” VGA 105 previously discussed.

In particular, the VGA 605 includes current-source transistors (e.g., PMOSs) M 21 and M 22 , input transistors (e.g., PMOSs) M 11 and M 12 , and load devices (e.g., resistors) RL 1 and RL 2 coupled in series in that order between the first voltage rail (VDD) and the second voltage rail (VSS) (e.g., ground), respectively. The VGA 605 similarly includes one or more variable capacitors CS and one or more variable resistors RS coupled in parallel between the upper terminals (e.g., sources) of the input transistors M 11 and M 12 . The positive component VIP and negative component VIN of the input differential signal are applied to the control terminals (e.g., gates) of the transistors M 11 and M 12 via AC-coupling capacitors C 11 and C 12 , respectively. The positive component VOP and negative component VON of the output differential signal are generated at the lower terminals (e.g., drains) of the input transistors M 12 and M 11 , respectively.

The common mode voltage control circuit 610 includes a replica circuit 620 that replicates one side of the VGA 605 . That is, the replica circuit 620 includes a replica current-source transistor M 2 R (e.g., PMOS), a replica input transistor M 1 R (e.g., PMOS), and a replica load device RL R (e.g., resistor) coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS). The common mode voltage VICM of the input differential signal, generated at the intermediate node of resistor network R 1 /R 2 and R 3 /R 4 , is applied to the control terminal (e.g., gate) of the replica input transistor M 1 R .

The common mode voltage circuit 610 further includes a differential (operational) amplifier A 1 configured to generate a bias voltage PBIAS applied to the control terminal (e.g., gate) of the replica current-source transistor M 2 R , and to the control terminals (e.g., gates) of the current-source transistors M 21 and M 22 of the VGA 605 . Through feedback control, the differential amplifier A 1 generates the bias voltage PBIAS to cause a replica common mode voltage VOCM R at the lower terminal (e.g., drain) of replica input transistor M 1 R to be substantially the same as a target common mode voltage VOCM T generated by a divider R 5 /R 6 . Accordingly, the common mode voltage control circuit 610 operates similar to control circuit 110 to generate a bias voltage PBIAS for the control terminals (e.g., gates) of the current-source transistors M 21 and M 22 (e.g., PMOSs) to set (e.g., control or regulate) the common mode voltage VOCM of the output differential signal VOP and VON to the target common mode voltage VOCM T .

FIG. 7 illustrates a receiver 700 including a “p-version” of a CTLE 605 and a common mode voltage control circuit 710 for setting (e.g., controlling or regulating) the common mode voltage VOCM of an output differential signal VOP and VON of the CTLE 705 . The CTLE 705 is a p-version because it includes PMOS as input transistors and current-source transistors, and it is flipped up-side-down as compared to the “n-version” CTLE 205 previously discussed.

In particular, the CTLE 705 includes current-source transistors (e.g., PMOSs) M 61 and M 62 , input transistors (e.g., PMOSs) M 51 and M 52 , and positive- and negative-side sets of parallel load (diode-connected) transistors (e.g., NMOS), collectively referred to as M 41 a -M 41 b and M 42 a -M 42 b , and two sets of load-selecting switch devices (e.g., NMOSs) via select signals PKN<0:7>, collectively referred to as M 31 a - b and M 32 a - b , coupled in series in that order between the first voltage rail (VDD) and the second voltage rail (VSS) (e.g., ground), respectively. The CTLE 705 similarly includes positive- and negative-side sets of selectable capacitor paths (MS 1 +CF∥MS 2 +CF∥MS 3 +CF) coupled in parallel between the lower terminals (e.g., drains) of the input transistors M 51 and M 52 and resistors R 21 and R 11 , respectively. For impedance matching and noise reduction, the CTLE 705 includes cross-coupled capacitors CZ coupled between the control terminals (e.g, gates) and lower terminals (e.g., drains) of input transistors M 51 and M 52 , respectively.

The positive component VIP and negative component VIN of the input differential signal are applied to the control terminals (e.g., gates) of the transistors M 51 and M 52 via AC-coupling capacitors C 11 and C 12 , respectively. The positive component VOP and negative component VON of the output differential signal are generated at the lower terminals (e.g., drains) of the input transistors M 52 and M 51 , respectively.

The common mode voltage control circuit 710 includes a replica circuit 720 that replicates one side of the CTLE 705 . That is, the replica circuit 720 includes a replica current-source transistor M 6 R (e.g., PMOS), a replica input transistor M 5 R (e.g., PMOS), a replica load (diode-connected) transistor M 4 R (e.g., NMOS), and a replica switch device M 3 R (e.g., NMOS) coupled in series between the first voltage rail (VDD) and the second voltage rail (VSS) (e.g., ground). The common mode voltage VICM of the input differential signal, generated at the intermediate node of resistor network R 1 /R 2 and R 3 /R 4 , is applied to the control terminal (e.g., gate) of the replica input transistor M 5 R . The voltage VDD is applied to the control terminal (e.g., gate) of the replica switch device M 3 R .

The common mode voltage circuit 710 further includes a differential (operational) amplifier A 1 configured to generate a bias voltage PBIAS applied to the control terminal (e.g., gate) of the replica current-source transistor M 6 R , and to the control terminals (e.g., gates) of the current-source transistors M 61 and M 62 of the CTLE 705 . Through feedback control, the differential amplifier A 1 generates the bias voltage PBIAS to cause a replica common mode voltage VOCM R at the lower terminal (e.g., drain) of replica input transistor M 5 R to be substantially the same as a target common mode voltage VOCM T generated by a divider R 5 /R 6 . Accordingly, the common mode voltage control circuit 710 operates similar to control circuit 210 to generate a bias voltage PBIAS for the control terminals (e.g., gates) of the current-source transistors M 61 and M 62 (e.g., PMOSs) to set (e.g., control or regulate) the common mode voltage VOCM of the output differential signal VOP and VON to the target common mode voltage VOCM T .

FIG. 8 illustrates a schematic diagram of another exemplary receiver 800 including a VGA 605 cascaded with the CTLE 705 in accordance with another aspect of the disclosure. The receiver 800 is similar to receiver 300 with the exception that it employs the p-version VGA 605 and corresponding common mode control circuit 610 , and the p-version CTLE 705 and corresponding common mode control circuit 710 .

In summary, the VGA control circuit 610 generates a first bias voltage PBIAS 1 to set and control the common mode voltage VOCM 1 of a first output differential signal VOP 1 and VON 1 generated by the VGA 605 based on the common mode voltage VICM of the input differential signal VIP and VIN, a first replica output common mode voltage VOCM 1 R , and a first target common mode voltage VOCM 1 T , as previously discussed. Similarly, the control circuit 710 generates a second bias voltage PBIAS 2 to set and control the common mode voltage VOCM 2 of a second output differential signal VOP 2 and VON 2 generated by the CTLE 705 based on the first replica common mode voltage VOCM 1 R generated by the control circuit 610 , a second replica output common mode voltage VOCM 2 R , and a second target common mode voltage VOCM 2 T , as previously discussed.

FIG. 9 illustrates a schematic diagram of another exemplary receiver 900 including a VGA 605 cascaded with the CTLE 705 in accordance with another aspect of the disclosure. The receiver 900 is a variation of receiver 800 . A difference between receiver 900 and receiver 800 is that the first target common mode voltage VOCM 1 T (and not the first replica common mode voltage VOCM 1 R ) is applied to the control input (e.g., gate) of the replica input transistor M 5 R of the replica circuit 720 of the common mode voltage control circuit 710 for the CTLE 705 .

Again, the reason for this is that the control variation of the first replica common mode voltage VOCM 1 R may affect the control operation of the common mode voltage control circuit 710 . As the first target common mode voltage VOCM 1 T is substantially constant (and is substantially the same as the first replica common mode voltage VOCM 1 R ), it should not adversely affect the control operation of the common mode voltage control circuit 710 .

FIG. 10 illustrates a schematic diagram of another exemplary receiver 1000 including the VGA 605 cascaded with the CTLE 705 in accordance with another aspect of the disclosure. The receiver 1000 is a variation of receiver 800 . A difference between receiver 1000 and receiver 800 is that the supply voltages for the VGA replica circuit 620 , the VGA voltage divider R 5 /R 6 , the CTLE replica circuit 720 , and the CTLE voltage divider R 7 /R 8 are “cleaner” (less noisy) bandgap reference voltages. This may improve the power supply noise rejection for the VGA 605 and the CTLE 705 .

In particular, bandgap reference voltage VBG 1 for the VGA replica circuit 620 and the CTLE replica circuit 720 should be at substantially the same potential as VDD so that the replica circuits receive the same supply voltage level as the VGA 605 and CTLE 705 , respectively. The bandgap reference voltages VBG 2 and VBG 3 for the voltage dividers R 5 /R 6 and R 7 /R 8 could be substantially the same as or different than VDD.

FIG. 11 illustrates a flow diagram of an exemplary method 1100 of controlling a common mode voltage of an output differential signal of a differential signal processing circuit in accordance with another aspect of the disclosure.

The method 1100 includes applying first and second components of an input differential signal to first and second control terminals of first and second input transistors of a differential signal processing circuit, respectively (block 1110 ). As illustrated in the various receivers described herein, the circuit including the AC-coupling capacitors C 11 and C 12 configured to apply the differential input signal VIP and VIN to the input transistors of the various differential signal processing circuits described herein is an example of a means for applying first and second components of an input differential signal at first and second control terminals of first and second input transistors of a differential signal processing circuit, respectively.

The method 1100 further includes generating first and second components of an output differential signal at first and second nodes between first and second load devices and the first and second input transistors, respectively (block 1120 ). As illustrated in the various receivers described herein, the various differential signal processing circuits including the variable gain amplifiers (VGAs) 105 and 605 and the continuous time linear equalizers (CTLEs) 205 and 705 are examples of means for generating first and second components of an output differential signal at first and second nodes between first and second load devices and the first and second input transistors, respectively.

The method 1100 further includes controlling a common mode voltage of the output differential signal including generating a bias voltage for control terminals of first and second current-source transistors coupled in series with the first and second load devices and the first and second input transistors between first and second voltage rails, respectively, wherein the bias voltage is generated from an input common mode voltage of the input differential signal (block 1130 ). As illustrated in the various receivers described herein, the various common mode control circuits 110 , 210 , 610 , and 710 are examples of means for controlling a common mode voltage of the output differential signal including generating a bias voltage for control terminals of first and second current-source transistors coupled in series with the first and second load devices and the first and second input transistors between first and second voltage rails, respectively, wherein the bias voltage is generated from an input common mode voltage of the input differential signal.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.