High performance multiplexed latches

The present disclosure relates to latch structures and, more particularly, to high performance multiplexed latches and methods of use.

In a memory (e.g., an embedded memory) where output data is not registered, the last stage in an output data path is typically a column data multiplexer. The multiplexer selects from among a number of column data signals based on the column address. One potential drawback with the column addresses, which are the control signals to the column data multiplexer, is that the column addresses could arrive at the column data multiplexer before the column data signals. This may occur because the column data signals, which travel through the memory core, may have a slower path relative to the column addresses. Consequently, this may result in a glitch on the output data signal due to the column data multiplexer switching from one column to a second column before new valid output data arrives at the second column. Therefore, for a brief period, old invalid output data is read out from the second column.

A conventional approach to this problem is to delay the column address to the column data multiplexer so that the column addresses arrive at the column data multiplexer after the valid output data from the memory core. For example, one approach is to insert a delay (e.g., a delay chain) in the column address path so that the column addresses arrive at the column data multiplexer after the output data. However, it may be difficult to match the output data path with the column address path.

As another example, a second approach is to provide a data path circuit (e.g., a dummy data path) to generate the column address signals to match the column address delay and the output data delay to the column data multiplexer. However, this approach may add significantly to die area overhead and design complexity. As a result, there is a need for improved memory techniques for providing the output data.

In an aspect of the disclosure, a multiplexed latch comprises: a first latch structured to receive a data signal D 0 and comprising a plurality of inverters which receive a respective input clock signal; and a second latch structured to receive a data signal D 1 and comprising a plurality of inverters which receive a respective input clock signal.

In an aspect of the disclosure, a multiplexed latch comprises: a first latch comprising: a first inverter which is structured to receive a data signal D 0 and an input clock signal CLK 0 ; a driving inverter in series with the first inverter and which is structured to receive an input clock signal CLK 1 N; a feedback inverter which is parallel to the driving inverter and which is structured to receive an input clock signal CLK 0 N; and a second latch comprising: a first inverter which is structured to receive a data signal D 1 and an input clock signal CLK 1 ; a driving inverter in series with the first inverter and which is structured to receive an input clock signal CLK 0 N; and a feedback inverter which is parallel to the driving inverter and which is structured to receive an input clock signal CLK 1 N.

In an aspect of the disclosure, a method comprises enabling an input signal into a first inverter of a first latch to drive output data through a driving inverter of the first latch while turning of a feedback inverter of the first latch and isolating a second latch.

The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.

FIG. 1 shows a schematic diagram of a high performance multiplexed latch in accordance with aspects of the present disclosure.

FIG. 2 is a timing diagram of the signals shown being processed by the structure in FIG. 1 .

The present disclosure relates to latch structures and, more particularly, to high performance multiplexed latches and methods of use. More specifically, the present disclosure relates to multiplexed latches for read data paths of an SRAM cell. Advantageously, the multiplexed latch will:

(i) eliminate the influence of decode addresses (DA) on output data (Q) and thereby enhance memory performance;

(ii) eliminate the need to latch the AD address twice for reads;

(iii) integrate a sense amplifier and multiplexer;

(iv) prevent output glitches in case the AD toggles sooner than data arrival (compared to mux operations);

(v) provide faster access time (compared to conventional latch structures);

(vi) enable high frequency operation; and

(vii) allow all decoding to be done at the Bitswitch level via programming for all decodes.

FIG. 1 show a schematic diagram of a high performance multiplexed latch in accordance with aspects of the present disclosure. In operation, the multiplexed latch 10 is provided for a read data path in SRAM cells, which eliminates the need for a multiplexer. By eliminating the need of a multiplexer, the present structure avoids many known issues such as, for example, needing either one of the mux control signals active all the time or contention between muxes during active and inactive states of Sense Amplifier Enable clock signals.

In embodiments, the multiplexed latch 10 includes a first latch structure 12 in parallel with a second latch structure 12 ′. The first latch structure 12 and the second latch structure 12 ′ each include a respective data input signal D 0 , D 1 , and a plurality of inverters. As should be understood by those of skill in the art, the inverters have only one input and are logically designed to reverse a logic state. Clock signals CLK 0 and CLK 1 are used to enable the respective latch structures 12 , 12 ′, and can be selected using AND gate logic. For example, SEL=1, CLK 1 will be high; whereas, SEL=0, CLK 0 will be high.

In embodiments, the first latch structure 12 includes a first inverter 14 in series with a second inverter 14 ′ (e.g., driving inverter). A feedback inverter 14 ″ is provided in parallel with the second inverter 14 ′. The data input signal D 0 is gated by the inverter 14 based on a clock signal CLK 0 , which is a clock signal that enables multiplexing of the latch 12 . Clock signals CLK 0 N and CLK 1 N are input into respective inverters 14 ″ and 14 ′. Clock signal CLK 0 N is an inversion of CLK 0 and clock signal CLK 1 N is an inversion of CLK 1 .

Similarly, the second latch structure 12 ′ includes a first inverter 16 in series with a second inverter 16 ′ (driving inverter). A feedback inverter 16 ″ is provided in parallel with the second inverter 16 ′. The data input signal D 1 is gated by the inverter 16 based on a clock signal CLK 1 , which is a clock signal that enables multiplexing of the latch 12 ′. Clock signals CLK 0 N and CLK 1 N are inputs to respective inverters 16 ′ and 16 ″.

In operation, selecting data input signal D 0 , when CLK 0 goes high, CLK 0 N will go low and turn off latch 12 ′. That is, latch 12 ′ will be isolated; whereas, the latch 12 will drive the output data Q. More specifically, when CLK 0 is high, CLK 0 N will go low hence turning off inverter 16 ′ of latch 12 ′ and feedback inverter 14 ″ of latch 12 . In this way, latch 12 ′ is isolated and output data Q will be driven primarily through inverter 14 ′ of latch 12 , e.g., since CLK 1 N will be high allowing inverter 14 ′ of latch 12 to be the primary driver of output Q. In contrast, when CLK 0 is low, both of the latches 12 , 12 ′ will drive output Q. This is because CLK 0 N will drive the feedback inverter 14 ″ of latch 12 on which, in turn, will drive inverter 14 ′ of latch 12 on, driving the output data Q. Accordingly, when the clock CLK 0 is turned off, in instance of data input signal D 0 , the feedback inverter 14 ″ will be driving output Q. And, as should be understood by those of skill in the art, when both CLK 0 N and CLK 1 N go high, there will be data retention and output Q is thus driven through both of the latches 12 , 12 ′.

In further operation, selecting data input signal D 1 , when CLK 1 goes high, CLK 1 N will go low turning off latch 12 . This will isolate the latch 12 and will allow the latch 12 ′ to drive output Q. More specifically, when CLK 1 is high, CLK 1 N will go low hence turning off inverter 14 ′ of latch 12 and feedback inverter 16 ″ of latch 12 ′. In this way, latch 12 is isolated and output data Q will be driven only through inverter 16 ′ of latch 12 ′. In contrast, when CLK 1 is low, both of the latches 12 , 12 ′ will drive the output Q. This is because CLK 1 N will drive the feedback inverter 16 ″ of latch 12 ′ on which, in turn, will drive inverter 16 ′ of latch 12 ′ on, driving the output data Q through the inverter 16 ′. Accordingly, when the clock CLK 1 is turned off, in instance of data input signal D 1 , the feedback inverters 16 ″ will be driving output Q. And, as should be understood by those of skill in the art, when both CLK 0 N and CLK 1 N go high, there will be data retention and output Q is thus driven through both of the latches 12 , 12 ′.

FIG. 2 is a timing diagram of the signals shown being processed by the structure in FIG. 1 . More specifically, the timing diagram shows that when SEL signal is high, data input signal D 0 is off and data input signal D 1 is enabled (e.g., on). At this stage, CLK 1 is high and the output data Q is driven as shown in cycle 0 . In contrast, when the SEL signal is turned off (not enabled) during cycle 0 , the CLK 0 will go high immediately in cycle 1 , input signal D 1 is off and data input signal D 0 is enabled (e.g., on) and, output data Q will driven starting at the beginning of cycle 1 . In cycle 1 , even though there may be a delay in arrival of data input signal D 0 vs. CLK 0 transition, there will not be any glitch as both latches store the pervious cycle data D 1 information. Thus, the structure 10 prevents any glitch in the data output Q and performance in a memory cell is increased.

Accordingly, by implementing the structure 10 described herein, the proper state will always be driven to output Q, e.g., in the SRAM data path. The structure 10 will thus enhance performance of a memory, e.g., SRAM. Moreover, by implementing this structure 10 , the implementation of driving the output Q becomes simple as the control signals for a sense amplifier, latch and multiplexer can now be the same, which, by having a same control signal, performance is enhanced (e.g., there is no output glitch or data delay).

In addition, compared to a conventional latch and multiplexer configuration, the output remains driven all the time even when both the Sense Amplifier Enable clock signals (CLK 0 , CLK 1 are low (in comparison to a typical multiplexer (mux) in which either one of the mux control signals need to be active all the time). Moreover, by implementing the structure 10 described herein, there is no contention between the muxes during active and inactive states of Sense Amplifier Enable clock signals. Also, integrating the sense amplifier, latching and multiplexing operation eliminates the need for a standalone multiplexor.

The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.