Method for forming conductive structure using polishing process

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.

One of the important drivers for increased performance in semiconductor devices is the higher levels of integration of circuits. This is accomplished by miniaturizing or shrinking device sizes on a given chip. As feature densities in semiconductor devices increase, the widths of the conductive lines and the spacing between the conductive lines and interconnect structures in the semiconductor devices also need to be scaled down.

Although existing methods for forming interconnect structures have been generally adequate for their intended purposes, as device scaling-down continues, they have not been entirely satisfactory in all respects.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A to 1G are cross-sectional representations of various stages of forming a semiconductor structure in accordance with some embodiments.

FIG. 2 is a cross-sectional representation of a semiconductor structure in accordance with some embodiments.

FIGS. 3A to 3B are cross-sectional representations of various stages of forming a semiconductor structure in accordance with some embodiments.

FIG. 4 is a cross-sectional representation of a semiconductor structure in accordance with some embodiments.

FIGS. 5A to 5D are cross-sectional representations of various stages of forming a semiconductor structure in accordance with some embodiments.

FIG. 6 is a cross-sectional representation of a semiconductor structure in accordance with some embodiments.

FIG. 7 is a cross-sectional representation of a semiconductor structure in accordance with some embodiments.

FIG. 8 is a cross-sectional representation of a semiconductor structure in accordance with some embodiments.

FIG. 9 is a cross-sectional representation of a semiconductor structure in accordance with some embodiments.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments for forming a semiconductor structure are provided. The semiconductor structure includes a conductive structure formed through a dielectric layer. In addition, during the formation of the semiconductor structure, a sacrificial layer is formed, so that the top surface of the resulting conductive structure is not level with the dielectric layer.

FIGS. 1A to 1G are cross-sectional representations of various stages of forming a semiconductor structure 100 a in accordance with some embodiments. As shown in FIG. 1A , a substrate 102 is received in accordance with some embodiments. The substrate 102 may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate 102 may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may be, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP.

In addition, the substrate 102 may include structures such as doped regions, interlayer dielectric (ILD) layers, conductive features, and/or isolation structures. Furthermore, the substrate 102 may further include single or multiple material layers to be patterned. For example, the material layers may include a silicon layer, a dielectric layer, and/or a doped poly-silicon layer.

In some embodiments, the substrate 102 includes a device region 104 , as shown in FIG. 1A . The device region 104 may have various device elements. Examples of device elements may include, but are not limited to, transistors, diodes, and other applicable elements. Examples of the transistors may include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), or the like. Various processes are performed to form the device elements, such as deposition, etching, implantation, photolithography, annealing, and other applicable processes.

A dielectric layer 106 is formed over the substrate 102 , as shown in FIG. 1A in accordance with some embodiments. In some embodiments, the dielectric layer 106 is an interlayer dielectric layer or an intermetal dielectric layer. The dielectric layer 106 may include multilayers made of multiple dielectric materials, such as low dielectric constant or extreme low dielectric constant (ELK) materials. In some embodiments, the dielectric layer 106 is made of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other applicable low-k dielectric materials.

In some embodiments, the dielectric layer 106 is formed by performing a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin-on coating process, or other applicable processes.

After the dielectric layer 106 is formed, a sacrificial layer 108 is formed over the dielectric layer 106 , as shown in FIG. 1A in accordance with some embodiments. In some embodiments, the sacrificial layer 108 and the dielectric layer 106 are made of different materials, so that they can have good polishing selectivity in the subsequent polishing process (Details will be described later). In some embodiments, the sacrificial layer 108 is made of oxide.

In some embodiments, the sacrificial layer 108 has a thickness in a range from about 50 Å to about 300 Å. The thickness of the sacrificial layer 108 may determine the height of the conductive structure formed in the dielectric layer 106 afterwards (Details will be described later).

After the dielectric layer 106 and the sacrificial layer 108 are formed over the substrate 102 , a trench 110 is formed through the dielectric layer 106 and the sacrificial layer 108 , as shown in FIG. 1B in accordance with some embodiments. In some embodiments, the trench 110 has a width in a range from about 10 nm to about 50 μm. In some embodiments, the trench 110 has a thickness in a range from about 150 Å to about 1000 Å.

Next, a barrier layer 112 is formed conformally over the substrate 102 , as shown in FIG. 1C in accordance with some embodiments. More specifically, the barrier layer 112 is formed on the sidewalls and the bottom surface of the trench 110 and on the top surface of the sacrificial layer 108 . In some embodiments, the barrier layer 112 has a thickness in a range from about 5 Å to about 50 Å. The barrier layer 112 should be thick enough to block the conductive material formed thereon from diffusing into the dielectric layer 106 . On the other hand, the barrier layer 112 may not be too thick, or the trench 110 may be blocked by the barrier layer 112 .

In some embodiments, the barrier layer 112 is made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used. The barrier layer 112 may be formed by performing a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a plasma enhanced CVD (PECVD) process, a plasma enhanced physical vapor deposition (PEPVD) process, an atomic layer deposition (ALD) process, or any other applicable deposition processes.

After the barrier layer 112 is formed, a seed layer 114 is formed over the barrier layer 112 , as shown in FIG. 1D in accordance with some embodiments. In some embodiments, the seed layer 114 is made of Cu, Co, Al, Ag, or the like. The seed layer 114 may be formed by performing a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a plasma enhanced CVD (PECVD) process, a plasma enhanced physical vapor deposition (PEPVD) process, an atomic layer deposition (ALD) process, or any other applicable deposition processes.

In some embodiments, the seed layer 114 has a thickness in a range from about 25 Å to about 35 Å. The seed layer 114 should not be too thick, or the trench 110 may be blocked by the seed layer 114 . On the other hand, the seed layer 114 may not be too thin, or the resistance may be too high.

Next, a conductive material 116 is formed over the seed layer 114 , as shown in FIG. 1E in accordance with some embodiments. More specifically, the conductive material 116 is formed in the trench 110 and over the sacrificial layer 108 . In addition, the trench 110 is fully filled with the conductive material 116 .

In some embodiments, the conductive material 116 is copper. In some embodiments, the conductive material 116 is aluminum, copper, tungsten, titanium, tantulum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other applicable materials.

In some embodiments, the conductive material 116 is formed by performing an electrochemical plating process. In some embodiments, the conductive material 116 is formed by performing a spin-on coating process, a CVD process, a PVD process, or other applicable deposition or coating processes.

In some embodiments, the conductive material 116 has a thickness in a range from about 600 Å to about 10000 Å. The conductive material 116 may be relatively thick, so that the top surface of the conductive material 116 may become relatively flat.

Afterwards, the top portion of the conductive material 116 is removed to form a conductive structure 118 a in the trench 110 , as shown in FIG. 1F in accordance with some embodiments. In some embodiments, the top portion of the conductive material 116 is removed by performing a first polishing process 124 a . In some embodiments, the first polishing process 124 a is a chemical mechanical polishing process. In some embodiments, the first polishing process 124 a is performed until the top surface of the sacrificial layer 108 is exposed. That is, an end-point detection is applied to the first polishing process 124 a . In some embodiments, the first polishing process 124 a is performed until the top surface of the barrier layer 112 is exposed.

In some embodiments, the conductive structure 118 a has a top portion 120 a formed in the sacrificial layer 108 and a bottom portion 122 a formed in the dielectric layer 106 . After the first polishing process 124 a is performed, the top surface of the conductive structure 118 a is substantially level with the top surface of the sacrificial layer 108 .

Next, the sacrificial layer 108 is removed, as shown in FIG. 1G in accordance with some embodiments. In some embodiments, the sacrificial layer 108 is removed by performing a second polishing process 126 a . In some embodiments, the second polishing process 126 a is a chemical mechanical polishing process.

The slurry used during the second polishing process 126 a is chosen so that the sacrificial layer 108 tends to be removed by the slurry while the conductive structure 118 a does not. In some embodiments, a polishing selectivity of the sacrificial layer 108 to the conductive structure 116 during the second polishing process 126 a is greater than about 3. In some embodiments, a polishing selectivity of the sacrificial layer 108 to the conductive structure 116 during the second polishing process 126 a is in a range from about 3 to about 7.

In some embodiments, a polishing selectivity of the sacrificial layer 108 to the dielectric layer 106 during the second polishing process 126 a is greater than about 3. In some embodiments, a polishing selectivity of the sacrificial layer 108 to the dielectric layer 106 during the second polishing process 126 a is in a range from about 3 to about 7.

The shape of the conductive structure 118 a may be controlled by the polishing selectivity of different materials during the second polishing process 126 a . For example, during the second polishing process 126 a , the sacrificial layer 108 is removed but the top portion 120 a of the conductive structure 118 a and the dielectric layer 106 substantially remains. Accordingly, the height of the top portion 120 a protruding from the dielectric layer 106 is substantially equal to the thickness of the sacrificial layer 108 in accordance with some embodiments.

In some embodiments, the sacrificial layer 108 is completely removed during the second polishing process 126 a , while only a portion of the top portion 120 a of the conductive structure 118 a is removed during the second polishing process 126 a . Therefore, the height of the top portion 120 a protruding from the dielectric layer 106 is smaller than the thickness of the sacrificial layer 108 in accordance with some embodiments.

In some embodiments, the first polishing process 124 a and the second polishing process 126 a are both chemical mechanical polishing processes, but the slurry used in the first polishing process 124 a is different from the slurry used in the second polishing process 126 a . In some embodiments, the first polishing process 124 a is performed at a pH value smaller than the pH value that the second polishing process 126 a is performed under. In some embodiments, the first polishing process 124 a is performed at a pH value in a range from about 6 to about 8. In some embodiments, the second polishing process 126 a is performed at a pH value in a range from about 7 to about 11. The shape of the conductive structure 118 a may be adjusted by performing the first polishing process 124 a and the second polishing process 126 a sequentially.

As shown in FIG. 1G , the semiconductor structure 100 a includes the conductive structure 118 a formed through the dielectric layer 106 . In addition, the top surface of the conductive structure 118 a is not level with the top surface of the dielectric layer 106 in accordance with some embodiments. In some embodiments, the conductive structure 118 a has a convex top surface (i.e. concave downward).

As described previously, the conductive structure 118 a is first formed in the dielectric layer 106 and the sacrificial layer 108 and the sacrificial layer 108 is removed afterwards. After the second polishing process 126 a , the sacrificial layer 106 is removed, and the top portion 120 s of the conductive structure 118 a protrudes from the dielectric layer 106 .

The conductive structure 118 a having the top portion 120 a protruding from the dielectric layer 106 may provide a greater contact surface for connecting with other conductive features. In addition, the protruding top portion 120 a of the conductive structure 118 a may be formed to compensate the non-flat top surface or insufficient height of the structure below. For example, when the top surface of the device region 104 is caved (e.g. concave) due to the manufacturing processes of forming devices in the device region, the additional height of the top portion 120 of the conductive structure 118 a may compensate the defect. Therefore, the performance of the resulting semiconductor structure 100 a may be improved.

In some embodiments, the conductive structure 118 a is a conductive feature formed in an interconnect structure. In some embodiments, the conductive structure 118 a is a contact connecting to a transistor.

FIG. 2 is a cross-sectional representation of a semiconductor structure 100 b in accordance with some embodiments. Processes and materials used to form the semiconductor structure 100 b may be similar to, or the same as, those used to form the semiconductor structure 100 a described above and are not repeated herein.

The semiconductor structure 100 b may be substantially the same as the semiconductor structure 100 a , except a device region 104 b in a substrate 102 b has a concave top surface, as shown in FIG. 2 in accordance with some embodiments.

More specifically, the semiconductor structure 100 b includes a conductive structure 118 b formed through the dielectric layer 106 over the substrate 102 b . In addition, the conductive structure 118 b includes a bottom portion 122 b formed in the dielectric layer 106 and a top portion 120 b protruding from the dielectric layer 106 .

As described previously, the protruding top portion 120 b may be used to compensate the concave top surface of the substrate 102 b . For example. When the device region 104 b has a concave top surface, the top portion 120 b of the conductive structure 118 b may have a convex top surface to compensate the height. In some embodiments, the conductive structure 118 b has a convex top surface (e.g. concave downward) and a concave bottom surface (e.g. concave upward). The risks of forming short circuit may be reduced accordingly, and the performance of the semiconductor structure 100 b may be improved.

FIGS. 3A to 3B are cross-sectional representations of various stages of forming a semiconductor structure 100 c in accordance with some embodiments. Some processes and materials used to form the semiconductor structure 100 c may be similar to, or the same as, those used to form semiconductor structure 100 a described previously and are not repeated herein.

For example, the processes shown in FIGS. 1A to 1E may be performed. Afterwards, a first polishing process 124 c is performed to form a conductive structure 118 c , as shown in FIG. 3A in accordance with some embodiments. The first polishing process 124 c may be similar to the first polishing process 124 a , but the polishing rate of the conductive structure 118 c in the first polishing process 124 c may be higher than that in the first polishing process 124 a . Therefore, after the first polishing process 124 c is performed, the conductive structure 118 c has a convex top surface in accordance with some embodiments.

As shown in FIG. 3A , the conductive structure 118 c has a top portion 120 c formed in the sacrificial layer 108 and a bottom portion 122 c formed in the dielectric layer 106 . After the first polishing process 124 c is performed, a second polishing process 126 c is performed to remove the sacrificial layer 108 , as shown in FIG. 3B in accordance with some embodiments. Similar to the second polishing process 126 a , the second polishing process 126 c may also be a chemical mechanical polishing process.

However, unlike the second polishing process 126 a , both the sacrificial layer 108 and the top portion 120 c of the conductive structure 118 c are removed during the second polishing process 126 c . That is, the polishing rate of the conductive structure 118 (e.g. the conductive material 116 ) during the second polishing process 126 c may be higher than that during the second polishing process 126 a described previously.

In some embodiments, a polishing selectivity of the sacrificial layer 108 to the conductive structure 118 c during the second polishing process 126 c is greater than about 3. In some embodiments, a polishing selectivity of the sacrificial layer 108 to the conductive structure 118 c during the second polishing process 126 c is in a range from about 3 to about 7. In some embodiments, a polishing selectivity of the sacrificial layer 108 to the dielectric layer 106 during the second polishing process 126 c is greater than about 2. In some embodiments, a polishing selectivity of the sacrificial layer 108 to the dielectric layer 106 during the second polishing process 126 c is in a range from about 2 to about 6.

As shown in FIG. 3B , the semiconductor structure 100 c includes the conductive structure 118 c formed through the dielectric layer 106 . In addition, the top surface of the conductive structure 118 c is not level with the top surface of the dielectric layer 106 in accordance with some embodiments. In some embodiments, the conductive structure 118 c has a concave top surface (i.e. concave upward). In some embodiments, the height's difference Hd between the central of the top surface of the conductive structure 118 c and the top surface of the dielectric layer 106 is in a range from about 25 Å to about 150 Å.

The conductive structure 118 c with the concave top surface may be formed to compensate the non-flat surface below. For example, when the device region 104 has a convex top surface (concave downward) due to the manufacturing processes of forming devices in the device region, the conductive structure 118 c having the concave top surface may be used to compensate the defect. Therefore, the performance of the resulting semiconductor structure 100 c may be improved.

FIG. 4 is a cross-sectional representation of a semiconductor structure 100 d in accordance with some embodiments. Processes and materials used to form the semiconductor structure 100 d may be similar to, or the same as, those used to form the semiconductor structure 100 c described above and are not repeated herein.

The semiconductor structure 100 d may be substantially the same as the semiconductor structure 100 c , except a device region 104 d in a substrate 102 d has a convex top surface, as shown in FIG. 4 in accordance with some embodiments.

More specifically, the semiconductor structure 100 d includes a conductive structure 118 d formed through the dielectric layer 106 over the substrate 102 d . As described previously, the conductive structure 118 d having the concave top surface may be used to compensate the convex top surface of the substrate 102 b . In some embodiments, the conductive structure 118 d has a concave top surface (e.g. concave upward) and a convex bottom surface (e.g. concave downward). The risks of forming short circuit may be reduced accordingly, and the performance of the semiconductor structure 100 d may be improved.

FIGS. 5A to 5D are cross-sectional representations of various stages of forming a semiconductor structure 100 e in accordance with some embodiments. Some processes and materials used to form the semiconductor structure 100 e may be similar to, or the same as, those used to form the semiconductor structure 100 a described previously and are not repeated herein.

Similar to those shown in FIGS. 1A and 1B , the dielectric layer 106 and the sacrificial layer 108 are formed over the substrate 102 . Afterwards, narrow trenches 110 e and wide trenches 110 e ′ are formed through the sacrificial layer 108 and the dielectric layer 106 , as shown in FIG. 5A in accordance with some embodiments.

In some embodiments, the width of narrow trench 110 e is smaller than the width of wide trench 110 e ′. In some embodiments, each narrow trench 110 e has a width in a range from about 10 nm to about 60 nm. In some embodiments, each wide trench 110 e ′ has a width in a range from about 60 nm to about 50 μm.

After the narrow trenches 110 e and the wide trenches 110 e ′ are formed, the barrier layer 112 , the seed layer 114 , and the conductive material 116 are conformally formed over the substrate 102 , as shown in FIG. 5B in accordance with some embodiments. The processes and materials used to form the barrier layer 112 , the seed layer 114 , and the conductive material 116 may be similar to, or the same as, those shown in FIGS. 1C to 1E .

Next, the top portion of the conductive material 116 is removed to form narrow conductive structures 118 e in the narrow trenches 110 e and wide conductive structures 118 e ′ in the wide trenches 110 e ′, as shown in FIG. 5C in accordance with some embodiments.

In some embodiments, the top portion of the conductive material 116 is removed by performing a first polishing process 124 e . In some embodiments, the first polishing process 124 e is a chemical mechanical polishing process. The first polishing process 124 e may be similar to, or the same as, the first polishing process 124 a described previously. After the first polishing process 124 e is performed, the top surfaces of the narrow conductive structures 118 e and wide conductive structures 118 e ′ are substantially level with the top surface of the sacrificial layer 108 .

Next, the sacrificial layer 108 is removed, as shown in FIG. 5D in accordance with some embodiments. In some embodiments, the sacrificial layer 108 is removed by performing a second polishing process 126 e . In some embodiments, the second polishing process 126 e is a chemical mechanical polishing process. The second polishing process 126 e may be similar to, or the same as, the second polishing process 126 a described previously.

As described previously, the polishing rate of the sacrificial layer 108 is greater than the polishing rate of the conductive material 116 during the second polishing process 124 e . Therefore, narrow top portions 120 e of the narrow conductive structures 118 e and wide top portions 120 e ′ of the wide conductive structure 118 e ′ protrude from the dielectric layer 106 .

In addition, since the widths of the narrow conductive structures 118 e and wide conductive structures 118 e ′ are different, the heights of the narrow top portions 120 e and the wide top portions 120 e ′ protruding from the dielectric layer 106 may also be different. In some embodiments, the height of the wide top portion 120 e ′ of the wide conductive structure 118 e ′ is greater than the height of the narrow top portions 120 e of the narrow conductive structure 118 e . In some embodiments, the difference between the height of the wide top portion 120 e ′ of the wide conductive structure 118 e ′ and the height of the narrow top portions 120 e of the narrow conductive structure 118 e is in a range from about 25 Å to about 75 Å.

FIG. 6 is a cross-sectional representation of a semiconductor structure 100 f in accordance with some embodiments. The semiconductor structure 100 f includes an interconnect structure 602 f formed over a substrate 102 f . In addition, the substrate 102 f includes a device region 104 f in accordance with some embodiments. In some embodiments, the device region 104 f includes a gate structure 601 embedded in an interlayer dielectric (ILD) layer 603 , source/drain regions 605 , and isolation structures 607 .

In some embodiments, the gate structure 601 includes a gate dielectric layer 609 , a gate electrode 611 , and spacers 613 . In some embodiments, the gate dielectric layer 609 is made of high k dielectric materials, such as metal oxides, metal nitrides, metal silicates, transition metaloxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, or metal aluminates. Examples of the high k dielectric materials may include, but are not limited to, hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium silicate, zirconium aluminate, zirconium oxide, titanium oxide, aluminum oxide, or hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy.

In some embodiments, the gate electrode 611 is made of a conductive material, such as aluminum, copper, tungsten, titanium, tantulum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other applicable materials.

The ILD layer 603 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, and/or other applicable dielectric materials. The ILD layer 603 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or other applicable processes.

It should be noted that the device region 104 f shown in FIG. 6 is merely an example, and other devices may be additionally or alternatively formed in the device region 104 f . In addition, some dielectric layers and conductive features may have been omitted in FIG. 6 for clarity.

The interconnect structure 602 f may include a number of metal layers formed over the device region 104 f of the substrate 102 f . In some embodiments, the interconnect structure 602 f includes conductive structures 118 f formed in a dielectric layer 106 f . The conductive structures 118 f may be similar to, or the same as, the conductive structure 118 a and/or 118 b described previously. As shown in FIG. 6 , the conductive structures 118 f may have various widths, and the top portions of the conductive structures 118 f protrude from the dielectric layer 106 f.

After the conductive structures 118 f are formed, an etch stop layer 615 is conformally formed over the substrate 102 f , as shown in FIG. 6 in accordance with some embodiments. More specifically, the etch stop layer 615 is formed on the top surface of the dielectric layer 106 f and on the top surface and the sidewalls of the top portion of the conductive structures 118 f.

In some embodiments, the etch stop layer 615 is made of silicon nitride, silicon oxynitride, and/or other applicable materials. The etch stop layer 615 may be formed by plasma enhanced CVD, low pressure CVD, ALD, or other applicable processes.

After the etch stop layer 615 is formed, a dielectric layer 106 f ′ is formed over the etch stop layer 615 , and conductive structures 118 f ′ are formed through the dielectric layer 106 f ′, as shown in FIG. 6 in accordance with some embodiments. The conductive structures 118 f ′ may be similar to, or the same as, the conductive structure 118 a and/or 118 b described previously. In some embodiments, the conductive structures 118 f ′ have various widths, and the top portions of the conductive structures 118 f ′ protrude from the dielectric layer 106 f′.

As shown in FIG. 6 , one conductive structure 118 f ′ formed in the dielectric layer 106 f ′ is connected to one connective structure 118 f formed in the dielectric layer 106 f . In addition, since the conductive structure 118 f has the top portion protruding from the dielectric layer 106 f , the electoral connection of the interconnection structure may be improved.

FIG. 7 is a cross-sectional representation of a semiconductor structure 100 g in accordance with some embodiments. The semiconductor structure 100 g is similar to the semiconductor structure 100 c , except a number of narrow conductive structures 118 g and wide conductive structure 118 g ′ are formed.

The semiconductor structure 100 g includes narrow conductive structures 118 g and wide conductive structures 118 g ′ formed through the dielectric layer 106 . In addition, the top surfaces of the narrow conductive structures 118 g and the wide conductive structures 118 g ′ have concave top surfaces. Since the widths of the narrow conductive structures 118 g and the wide conductive structures 118 g ′ are different, the height of the narrow conductive structure 118 g and the wide conductive structure 118 g ′ may also be different after the second polishing process is performed.

FIG. 8 is a cross-sectional representation of a semiconductor structure 100 h in accordance with some embodiments. The semiconductor structure 100 h includes an interconnect structure 602 h formed over a substrate 102 h . In addition, the substrate 102 h includes a device region 104 h in accordance with some embodiments. In some embodiments, the device region 104 h includes the gate structure 601 embedded in the interlayer dielectric (ILD) layer 603 , the source/drain regions 605 , and the isolation structures 607 . In some embodiments, the gate structure 601 includes the gate dielectric layer 609 , the gate electrode 611 , and the spacers 613 .

The interconnect structure 602 h may include a number of metal layers formed over the device region 104 h of the substrate 102 h . In some embodiments, the interconnect structure 602 h includes conductive structures 118 h formed in a dielectric layer 106 h . The conductive structures 118 h may be similar to, or the same as, the conductive structure 118 c and 118 d described previously. As shown in FIG. 8 , the conductive structures 118 h may have various widths, and the top surfaces of the conductive structures 118 h are not level with the top surface of the dielectric layer 106 h.

After the conductive structures 118 h are formed, an etch stop layer 615 h is conformally formed over the substrate 102 h , as shown in FIG. 8 in accordance with some embodiments. More specifically, the etch stop layer 615 h is formed on the top surface of the dielectric layer 106 f and on the concave top surfaces of the conductive structures 118 h.

After the etch stop layer 615 h is formed, a dielectric layer 106 h ′ is formed over the etch stop layer 615 h , and conductive structures 118 h ′ are formed through the dielectric layer 106 h ′, as shown in FIG. 8 in accordance with some embodiments. The conductive structures 118 h ′ may be similar to, or the same as, the conductive structure 118 c and 118 d described previously. As shown in FIG. 8 , one conductive structure 118 h ′ formed in the dielectric layer 106 h ′ is connected to one connective structure 118 h formed in the dielectric layer 106 h.

FIG. 9 is a cross-sectional representation of a semiconductor structure 100 i in accordance with some embodiments. The semiconductor structure 100 i includes an interconnect structure 602 i formed over a substrate 102 i . In addition, the substrate 102 i includes a device region 104 i in accordance with some embodiments. In some embodiments, the device region 104 i includes the gate structure 601 embedded in the interlayer dielectric (ILD) layer 603 , the source/drain regions 605 , and the isolation structures 607 . In some embodiments, the gate structure 601 includes the gate dielectric layer 609 , the gate electrode 611 , and the spacers 613 .

The interconnect structure 602 i may include a number of metal layers formed over the device region 104 i of the substrate 102 i . In some embodiments, the interconnect structure 602 i includes conductive structures 118 i formed in a dielectric layer 106 i . The conductive structures 118 i may be similar to, or the same as, the conductive structure 118 c and 118 d described previously. As shown in FIG. 9 , the conductive structures 118 i may have various widths and concave top surfaces.

After the conductive structures 118 i are formed, an etch stop layer 615 i is conformally formed over the substrate 102 i , as shown in FIG. 9 in accordance with some embodiments. More specifically, the etch stop layer 615 i is formed on the top surface of the dielectric layer 106 i and on the concave top surfaces of the conductive structures 118 i.

After the etch stop layer 615 i is formed, a dielectric layer 106 i ′ is formed over the etch stop layer 615 i , and conductive structures 118 i ′ are formed through the dielectric layer 106 i ′, as shown in FIG. 9 in accordance with some embodiments. The conductive structures 118 i ′ may be similar to, or the same as, the conductive structure 118 a and 118 b described previously. As shown in FIG. 9 , one conductive structure 118 i ′ formed in the dielectric layer 106 i ′ is connected to one connective structure 118 i formed in the dielectric layer 106 i.

As shown in FIGS. 1A to 9 and described previously, a conductive structure (e.g. conductive structures 118 a to 118 i ) is formed through a dielectric layer (e.g. dielectric layer 106 ), but the top surface of the conductive structure may not be level with the top surface of the dielectric layer. The conductive structure may be formed by performing a first polishing process (e.g. the first polishing process 124 a or 124 c ) and a second polishing process (e.g. the second polishing process 126 a or 126 c ). In addition, the shape of the conductive structure may be controlled by adjusting the first polishing process and second polishing process.

For example, the conductive structure may have a concave top surface or a convex top surface. In some embodiments, the conductive structure has the top portion (e.g. the top portions 120 a ) protruding from the dielectric layer, such that the contact surface of the conductive structure may be increase. Therefore, the performance of the resulting semiconductor structure may be improved.

In addition, the shape of the conductive structure may be adjusted to compensate with the non-flat top surface of the device region (e.g. device regions 104 a to 104 i ) below the conductive structure. Accordingly, the risks of forming short circuit may be reduced, and the performance of the semiconductor structure may be improved.

Embodiments of a semiconductor structure and methods for forming the same are provided. The method includes forming a conductive structure through a dielectric layer. During the formation of the conductive structure, a polishing process may be performed, such that the resulting conductive structure may have a top surface which is not level with the top surface of the dielectric layer. The conductive structure may be formed over an non-flat surface of a substrate to compensate with the substrate. Therefore, the performance of the semiconductor structure may be improved.

In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a sacrificial layer over the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a trench through the sacrificial layer and the dielectric layer and forming a conductive structure in the trench. The method for manufacturing a semiconductor structure further includes removing the sacrificial layer. In addition, a top surface of the conductive feature is not level with a top surface of the dielectric layer after the sacrificial layer is removed.

In some embodiments, a method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a sacrificial layer over the dielectric layer. The method for manufacturing a semiconductor structure includes forming a trench through the sacrificial layer and the dielectric layer and forming a conductive material in the trench and over the sacrificial layer. The method for manufacturing a semiconductor structure includes removing a top portion of the conductive material to form a conductive structure in the trench and removing the sacrificial layer such that a top surface of the conductive structure is not level with a top surface of the dielectric layer.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate and a dielectric layer formed over the substrate. The semiconductor structure further includes a first conductive structure formed through the dielectric layer. In addition, the first conductive structure has a concave top surface or a convex top surface, such that the concave top surface or the convex top surface of the first conductive structure is not level with the top surface of the dielectric layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.