Memory array with memory cells arranged in pages

This non-provisional application claims priority of U.S. provisional application No. 62/063,410, filed on Oct. 14, 2014, included herein by reference in its entirety.

1. Field of the Invention

The present invention relates to a nonvolatile memory array, and more particularly, to a nonvolatile memory array with memory cells arranged in pages.

2. Description of the Prior Art

An electrically rewritable nonvolatile memory is a type of memory that retains information it stores even when no power is supplied to memory blocks and allows on-board rewriting of a program. Due to the wide range of applications for various uses, there is a growing need for a nonvolatile memory to be embedded in the same chip with the main circuit, especially for personal electronic devices having strict requirement for circuit area.

An example of a nonvolatile memory cell is a memory cell comprising two or three transistors, which are memory transistors for retaining data, and one or two select transistor for selecting a memory transistor as a so-called memory bit. Also, the memory bit maybe arranged in different pages, that is, within different words, for flexible access. In this case, the nonvolatile memory cell may include two select transistors for further control.

Typically, the memory transistor has a floating gate. The floating gate is able to hold electrons during a programming operation of a memory cell. When erasing data in the memory cell, an FN (Fowler Nordheim) tunnel current is induced and flows via a tunnel under the floating gate, causing the emission of electrons from the floating gate.

However, to operate memory cells disposed in different pages may require complicated control signals on different signal lines, making the operations of the nonvolatile memory inflexible and requiring a significant amount of space for line connections.

One embodiment of the present invention discloses a memory array. The memory array includes a memory page. The memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells. The first word line is for receiving a first word line signal, and the first select gate line is for receiving a first select gate signal. The first control line is for receiving a first control line signal, and the first erase line is for receiving a first erase line signal. Each of first memory cells includes a word line node coupled to the first word line, a select gate coupled to the first select gate line, a control node coupled to the first control line, an erase node coupled to the first erase line, a bit line node for receiving a bit line signal, and a source line node for receiving a source line signal.

The bit line nodes of the plurality of first memory cells are for receiving different bit line signals, and the source line nodes of the plurality of first memory cells are for receiving different source line signals.

During an program operation of a selected first memory cell of the plurality of first memory cells, a bit line signal received by the selected first memory cell and a bit line signal received by an unselected first memory cell are at different voltages, and a source line signal received by the selected first memory cell and a source line signal received by the unselected first memory cell are at different voltages.

Another embodiment of the present invention discloses a memory array. The memory array includes a first memory page and a second memory page. The first memory page includes a first word line for receiving a first word line signal, a first select gate line for receiving a first select gate signal, a first control line for receiving a first control line signal, a first erase line for receiving a first erase line signal, and a plurality of first memory cells. Each of the first memory cells is coupled to the first word line, the first select gate line, the first control line, and the first erase line, and receives a bit line signal and a source line signal.

The second memory page includes a second control line for receiving a second control line signal, a second erase line for receiving a second erase line signal, and a plurality of second memory cells. Each of the second memory cells is coupled to the first word line, the first select gate line, the second control line, and the second erase line, and receives a bit line signal and a source line signal.

Another embodiment of the present invention discloses a memory array. The memory array includes a first memory page and a second memory page. The first memory page includes a first word line for receiving a first word line signal, a first select gate line for receiving a first select gate signal, a first control line for receiving a first control line signal, a first erase line for receiving a first erase line signal, and a plurality of first memory cells. Each of the first memory cells is coupled to the first word line, the first select gate line, the first control line, and the first erase line, and receives a bit line signal and a source line signal.

The second memory page includes a second word line for receiving a second word line signal, a second select gate line for receiving a second select gate signal, a second control line for receiving a second control line signal, a second erase line for receiving a second erase line signal, and a plurality of second memory cells. Each of the second memory cells is coupled to the second word line, the second select gate line, the second control line, the second erase line, a bit line node of a corresponding first memory cell in the first memory page, and a source line node of the corresponding first memory cell in the first memory page.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 shows a memory array according to one embodiment of the present invention.

FIG. 2 shows the memory cell of the memory array in FIG. 1 according to one embodiment of the present invention.

FIG. 3 shows a top view of the layout of a memory page of the memory array in FIG. 1 according to one embodiment of the present invention.

FIG. 4 shows a top view of the layout of a memory page of the memory array in FIG. 1 according to another embodiment of the present invention.

FIG. 5 shows a top view of the layout of a memory page of the memory array in FIG. 1 according to another embodiment of the present invention.

FIG. 6 shows a memory array according to another embodiment of the present invention.

FIG. 7 shows a memory array according to another embodiment of the present invention.

FIG. 8 shows a memory array according to another embodiment of the present invention.

FIG. 1 shows a memory array 100 according to one embodiment of the present invention. The memory array 100 includes a first memory page MP 1 . The first memory page MP 1 includes a first word line WL 1 , a first select gate line SG 1 , a first control line CL 1 , a first erase line EL 1 , and N first memory cells M 1 C 1 to M 1 C N , where N is a positive integer.

The first word line WL 1 is for receiving a first word line signal SWL 1 , and the first select gate line SG 1 is for receiving a first select gate signal SSG 1 . The first control line CL 1 is for receiving a first control line signal SCL 1 , and the first erase line EL 1 is for receiving a first erase line signal SEL L .

Each of the first memory cells M 1 C 1 to M 1 C N includes a word line node, a select gate, a control node, an erase node, a bit line node, and a source line node. The word line nodes of the first memory cells M 1 C 1 to M 1 C N are coupled to the first word line WL 1 , the select gates of the first memory cells M 1 C 1 to M 1 C N are coupled to the first select gate line SG 1 , the control nodes of the first memory cells M 1 C 1 to M 1 C N are coupled to the first control line CL 1 , and the erase nodes of the first memory cells M 1 C 1 to M 1 C N are coupled to the first erase line EL 1 .

The bit line nodes of the first memory cells M 1 C 1 to M 1 C N receive different bit line signals through different bit lines BL 1 to BL N . That is, the bit line nodes of the first memory cells M 1 C 1 to M 1 C N may receive the bit line signals SBL 1 to SBL N respectively. Also, the source line nodes of the first memory cells M 1 C 1 to M 1 C N receive different source line signals through different source lines SL 1 to SL N . That is, the source line nodes of the first memory cells M 1 C 1 to M 1 C N may receive the source line signals SSL 1 to SSL N respectively.

FIG. 2 shows a memory cell 200 according to one embodiment of the present invention. The memory cell 200 includes a first select transistor T 1 , a floating gate transistor T 2 , and a second select transistor T 3 .

A connection node of the first select transistor T 1 is coupled to a first connection node of the floating gate transistor T 2 , and the second connection node of the floating gate transistor T 2 is coupled to a connection node of the second select transistor T 3 .

Furthermore, when using the memory cell 200 as a first memory cell, for example, the first memory cell M 1 C n (n is a positive integer no greater than N), in the first memory page MP 1 , a node of the first select transistor T 1 can be the source line node of the first memory cell M 1 C n for receiving the source line signal SSL n , a gate of the first select transistor T 1 can be the select gate of the first memory cell M 1 C n coupled to the first select gate line SG 1 . Also, a floating gate of the floating gate transistor T 2 can be coupled to the control node CN of the first memory cell M 1 C n and further to the first control line CL 1 , and can be coupled to the erase node EN of the first memory cell M 1 C n and further to the first erase line EL 1 . A node of the second select transistor T 3 can be the bit line node of the first memory cell M 1 C n for receiving the bit line signal SBL n , and a gate of the second select transistor T 3 can be the word line node of the first memory cell M 1 C n coupled to the first word line WL 1 .

Table 1 shows voltages of the signals received by the first memory cell M 1 C n of the first memory cells M 1 C 1 to M 1 C N when the first memory cell M 1 C n is selected for different operations, where n is an integer between 1 and N. In Table 1, the first voltage VPP and the fourth voltage VEE are greater than the second voltage VDD, and the second voltage VDD is greater than the third voltage GND. The fourth voltage VEE may be at a same level as the first voltage VPP. The first voltage VPP may be, for example, from 5V to 20V. The second voltage VDD may be used as input/output voltage from/to other circuits for general purposes, and, for example, may be from 0V to 5V. The third voltage GND may be the ground voltage, 0V.

During a program operation of the selected first memory cell M 1 C n , the bit line signal SBL n received by the bit line node of the selected first memory cell M 1 C n is at the third voltage GND, and the source line signal SSL n received by the source line node of the selected first memory cell M 1 C n is at the third voltage GND. Also, the first word line signal SWL 1 is at the second voltage VDD, the first select gate signal SSG 1 is at the second voltage VDD, the first control line signal SCL 1 is at the first voltage VPP, and the first erase line signal SEL 1 is at the fourth voltage VEE. Since the first control line signal SCL 1 and the first erase line signal SEL 1 are at the greater voltages VPP and VEE respectively, the FN electron tunneling injection may occur to the floating gate transistor T 2 of the selected first memory cell M 1 C n so that the first memory cell M 1 C n can store/retain electrons while being programmed.

During an erase operation of the first memory cell M 1 C n , the same voltages of the signals in the programming operation can be applied, except for the first control line signal SCL 1 and the first erase line signal SEL L . During the erase operation of the selected first memory cell M 1 C n , the first control line signal SCL 1 is at the third voltage GND and the erase line signal SEL 1 is at the fourth voltage VEE so the electrons stored/retained by the floating gate of the first memory cell M 1 C n will be ejected and the first memory cell M 1 C n can be erased. The fourth voltage VEE can be same as the first voltage VPP or can be different from the first voltage VPP, depending on the system requirements.

However, the first memory cells M 1 C 1 to M 1 C N in the first memory page MP 1 are all coupled to the first word line WL 1 , the first select gate line SG 1 , the first control line CL 1 , and the first erase line EL 1 , therefore, the bit line signal SBL n and the source line signal SSL n received by the first memory cell M 1 C n may be used to ensure that the first memory cell M 1 C n is to be program inhibited while the selected first memory cell other than the first memory cell M 1 C n in the first memory page MP 1 is being programmed. To program inhibit the unselected first memory cell M 1 C n during a programming operation of the selected first memory cell, the bit line signal received by the selected first memory cell and the bit line signal SBL n received by an unselected first memory cell M 1 C n can be at different voltages, and the source line signal received by the selected first memory cell and the source line signal SSL n received by the unselected first memory cell M 1 C n can be at different voltages.

For example, when the first memory cell M 1 C 1 is selected to be programmed, namely, during a program operation of the selected first memory cell M 1 C 1 , the first memory cell M 1 C n is under an program inhibit operation. In this case, the first control line signal SCL 1 is at the first voltage VPP and the first erase line signal SEL 1 is at the fourth voltage VEE, the first word line signal SWL 1 is at the second voltage VDD, the first select gate signal SSG 1 is at the second voltage VDD, the bit line signal SBL 1 received by the bit line node of the selected first memory cell M 1 C 1 is at the third voltage GND, and the source line signal SSL 1 received by the source line node of the selected first memory cell M 1 C 1 is at the third voltage GND so that the selected first memory cell M 1 C 1 can be programmed.

However, the bit line signal SBL n received by the bit line node of the unselected first memory cell M 1 C n is at the second voltage VDD, and the source line signal SSL n received by the source line node of the unselected first memory cell M 1 C n is at the second voltage VDD.

Since the bit line signal SBL n and the source line signal SSL n are both at the second voltage VDD as the first word line signal SWL 1 and the first select gate signal SSG 1 , the select transistors T 1 and T 3 in the first memory cell M 1 C n can be turned on. The second voltage VDD therefore passes to both the first connection node and the second connection node of the floating gate transistor T 2 of the first memory cell M 1 C n which results in that the first memory cell M 1 C n is program inhibited (because the bias condition of the floating gate transistor T 2 is unable to induce sufficient F-N program mechanism) during the program operation of the selected first memory cell M 1 C 1 in the first memory page MP 1 .

In prior art, when one memory page is selected, all memory cells in the selected memory page will be programmed or erased simultaneously. That is, the memory array of prior art is not able to program the memory cells in the same memory page individually. However, according to the memory array 100 , the first memory cells M 1 C 1 to M 1 C N of the first memory page MP 1 can be operated properly and individually with the shared first word line WL 1 , select gate line SG 1 , control line CL 1 and erase line EL 1 , and with different bit line signals and source line signals. However, if required, the first memory cells M 1 C 1 to M 1 C N of the first memory page MP 1 can, of course, be operated simultaneously as well.

Therefore, the flexibility of memory operation to the memory array 100 can be achieved in an efficient way by sharing common signal lines.

Also, in addition to the memory cell 200 , the first memory cells M 1 C 1 to M 1 C N may also adopt other types of memory cell as long as the adopted memory cell can be operated properly with similar control signals shown in Table 1.

FIG. 3 shows a top view of the layout of the first memory page MP 1 according to one embodiment of the present invention. In FIG. 3 , the first memory page MP 1 includes the first memory cell M 1 C 1 and M 1 C 2 , and each of the first memory cell M 1 C 1 and M 1 C 2 may have the same structure as the memory cell 200 .

In FIG. 3 , the first control line CL 1 can be disposed in a first well NW 1 , and the first erase line EL 1 can be disposed in a second well NW 2 . The first well NW 1 and the second well NW 2 are N-type wells disposed in a P-type substrate P-sub. In some embodiments, the P-type substrate P-sub is coupled to the third voltage GND. Control nodes CN M1C1 and CN M1C2 of the first memory cells M 1 C 1 and M 1 C 2 are disposed on the first well NW 1 above the first control line CL 1 , and erase nodes EN M1C1 and EN M1C2 of the first memory cells M 1 C 1 and M 1 C 2 are disposed on the second well NW 2 above the first erase line EL 1 .

In some embodiments of the present invention, the first control line CL 1 can be formed in an active region AA NW1 in the first well NW 1 , and the control nodes CN M1C1 and CN M1C2 can be formed by a pattern of polysilicon PLY 1 above the active region AA NW1 in the first well NW 1 . The first erase line EL 1 can also be formed in an active region AA NW2 in the second well NW 2 , and the erase nodes EN M1C1 and EN M1C2 can be formed by a pattern of polysilicon PLY 2 above the active region AA NW2 in the second well NW 2 . In this case, the first control line CL 1 and the control nodes CN M1C1 and CN M1C2 can behave as capacitors, and the first erase line EL 1 and the erase nodes EN M1C1 and EN M1C2 can also behave as capacitors. The control line signal SCL 1 and the erase line signal SEL L can be directly applied to the first well NW 1 and the second well NW 2 respectively, and the control line signal SCL 1 and the erase line signal SEL 1 will be coupled to the control nodes CN M1C1 and CN M1C2 and the erase nodes EN M1C1 and EN M1C2 through the capacitors.

Also, in FIG. 3 , rest part of the first memory cell M 1 C 1 and M 1 C 2 are disposed along a direction X and disposed in active regions AA M1C1 and AA M1C2 between the first well NW 1 and the second well NW 2 . Thus, the floating gate FG M1C1 of the first memory cell M 1 C 1 and the floating gate FG M1C2 of the first memory cell M 1 C 2 are crossing the first well NW 1 and the second well NW 2 for coupling to the control nodes CN M1C1 and CN M1C2 and the erase nodes EN M1C1 and EN M1C2 .

In some embodiments of the present invention, the first memory page MP 1 may include even more first memory cells along the direction X disposed between the first well NW 1 and the second well NW 2 . However, due to the limited circuit space of the system, the first memory cells may not be able to be disposed all in the same direction X. Therefore, in FIG. 3 , the first erase line EL 1 can further be disposed in a third well NW 3 , which can also be an N-type well. That is, the erase line signal SEL 1 can be directly applied to both the third well NW 3 and the second well NW 2 simultaneously.

In this case, control nodes CN M1C3 and CN M1C4 of the first memory cell M 1 C 3 and M 1 C 4 are disposed on the first well NW 1 above the first control line CL 1 , and erase nodes EN M1C1 and EN M1C2 are disposed on the third well NW 3 above the first erase line EL 1 . The rest part of the first memory cell M 1 C 3 and M 1 C 4 are disposed in active regions AA M1C3 and AA M1C4 between the first well NW 1 and the third well NW 3 . Thus, the floating gate FG M1C3 of the first memory cell M 1 C 3 and the floating gate FG M1C4 of the first memory cell M 1 C 4 are crossing the first well NW 1 and the third well NW 3 . Consequently, the first memory cells M 1 C 1 and M 1 C 3 can be disposed along a direction Y. In addition, by sharing the same first well NW 1 , the first memory page MP 1 can use the limited circuit area even more efficiently.

Of course, in some embodiments of the present invention, the first memory page MP 1 may dispose more first memory cells M 1 C 5 and M 1 C 6 along the direction X, or more first memory cells M 1 C 7 and M 1 C 8 along the direction Y.

In addition, the first word line nodes of the first memory cell M 1 C 1 to M 1 C 8 , ex., the gates of the second select transistors of first memory cell M 1 C 1 to M 1 C 8 , can be coupled together to the first word line WL 1 through metal layers or shared polysilicon layers, and the first select gates of the first memory cell M 1 C 1 to M 1 C 8 can be coupled together to the first select gate line SG 1 through metal layers or shared polysilicon layers.

Although in FIG. 3 , the first control line CL 1 and the first erase line EL 1 are disposed in N-type wells, the first control line CL 1 and the first erase line EL 1 may also be disposed in different types of wells. FIG. 4 shows another top view of the first memory page MP 1 according to one embodiment of the present invention. In FIG. 4 , the first memory page MP 1 includes the first memory cell M 1 C 1 to M 1 C 8 , and each of the first memory cell M 1 C 1 to M 1 C 8 may have the same structure as the memory cell 200 .

In FIG. 4 , the first control line CL 1 is disposed in a first well PW 1 , and the control nodes CN M1C1 , CN M1C2 , CN M1C5 and CN M1C6 of the first memory cells M 1 C 1 , M 1 C 2 , M 1 C 5 and M 1 C 6 are disposed on the first well PW 1 above the first control line CL 1 . Part of the first memory cells M 1 C 1 , M 1 C 2 , M 1 C 5 and M 1 C 6 are disposed in a second well PW 2 , the first erase line EL 1 is disposed between the first well PW 1 and the second well PW 2 , and the erase nodes EN M1C1 , EN M1C2 , EN M1C5 and EN M1C6 of the first memory cells M 1 C 1 , M 1 C 2 , M 1 C 5 and M 1 C 6 are disposed between the first well PW 1 and the second well PW 2 above the first erase line EL 1 . Part of the first memory cells M 1 C 3 , M 1 C 4 , M 1 C 7 and M 1 C 8 are disposed in a third well PW 3 , the first erase line EL 1 is further disposed between the first well PW 1 and the third well PW 3 , and the erase nodes EN M1C3 , EN M1C4 , EN M1C7 and EN M1C8 of the first memory cells M 1 C 3 , M 1 C 4 , M 1 C 7 and M 1 C 8 are disposed between the first well PW 1 and the third well PW 3 above the first erase line EL 1 . The first well PW 1 , the second well PW 2 , and the third well PW 3 are P-type wells disposed in a deep N-type well DNW disposed in a P-type substrate P-sub.

In this case, the first erase line EL 1 can be disposed in active regions between the first well PW 1 and the second well PW 2 and between the first well PW 1 and the third well PW 3 .

Furthermore, in some cases, a reading current generated by a single first memory cell may be rather small, which may cause the long read time of the first memory page MP 1 . To solve this issue, bit line nodes of K first memory cells in the first memory page MP 1 can be coupled together and source line nodes of the K first memory cells in the first memory page MP 1 can be coupled together, K is an integer greater than 1.

FIG. 5 shows another top view the first memory page MP 1 according to one embodiment of the present invention. In FIG. 5 , the first memory page MP 1 has the similar layout as shown in FIG. 3 , however, two bit line nodes BN M1C1 and BN M1C2 of the first memory cells M 1 C 1 and M 1 C 2 are coupled together and two source line nodes SN M1C1 and SN M1C2 of the first memory cells M 1 C 1 and M 1 C 2 are coupled together.

In this case, the first memory cells M 1 C 1 and M 1 C 2 are operated consistently, that is, the first memory cells M 1 C 1 and M 1 C 2 will be programmed, erased, and read simultaneously so that reading currents of the first memory cells M 1 C 1 and M 1 C 2 can be combined together to identify the information stored. Since the combined reading current has a greater value than a single reading current, the combined reading current can help to reduce the read time of the first memory page MP 1 .

Although in FIG. 5 , the bit line nodes BN M1C1 and BN M1C2 of the first memory cells M 1 C 1 and M 1 C 2 are coupled together through metal layer within the first memory page MP 1 and source line nodes SN M1C1 and SN M1C2 of the first memory cells M 1 C 1 and M 1 C 2 are coupled together through metal layer within the first memory page MP 1 for saving external wiring, in other embodiments of the present invention, the bit line nodes of the first memory cells M 1 C 1 and M 1 C 2 may also receive the same signal from outside of the first memory page MP 1 and source line nodes of the first memory cells M 1 C 1 and M 1 C 2 may receive same the signal from outside of the first memory page MP 1 .

Furthermore, in FIG. 1 , the memory array 100 includes the first memory page MP 1 , but in some other embodiments of the present invention, the memory array 100 may further include more memory pages for storing more information in different pages. FIG. 6 shows a memory array 300 according to one embodiment of the present invention. The memory array 300 includes a first memory page MP 1 and a second memory page MP 2 .

The second memory page MP 2 has a similar structure as the first memory page MP 1 , but may receive different signals. The second memory page MP 2 includes a second control line CL 12 , a second erase line EL 12 , and a plurality of second memory cells M 2 C 1 to M 2 C N .

The second control line CL 12 is for receiving a second control line signal SCL 12 , and the second erase line EL 12 is for receiving a second erase line signal SEL 12 .

Each of the second memory cells M 2 C 1 to M 2 C N includes a word line node, a select gate, a control node, an erase node, a bit line node, and a source line node. The word line nodes of the second memory cells M 2 C 1 to M 2 C N are coupled to the first word line WL 1 , and the select gates of the second memory cells M 2 C 1 to M 2 C N are coupled to the first select gate line SG 1 . The control nodes of the second memory cells M 2 C 1 to M 2 C N are coupled to the second control line CL 12 , and the erase nodes of the second memory cells M 2 C 1 to M 2 C N are coupled to the second erase line EL 12 . The bit line nodes of the second memory cells M 2 C 1 to M 2 C N are for receiving different bit line signals SBL 11 to SBL 1N , and the source line nodes the second memory cells M 2 C 1 to M 2 C N are for receiving different source line signals SSL 11 to SSL 1N .

That is, the first memory page MP 1 and the second memory page MP 2 can share the same word line signal SWL 1 and the same select gate signal SSG 1 . However, since the first memory page MP 1 and the second memory page MP 2 are coupled to different control lines CL 1 and CL 12 , and different erase lines EL 1 and EL 12 , the second memory cells M 2 C 1 to M 2 C N in the second memory page MP 2 can still be operated properly with the signals shown in Table 1.

For example, during a programming operation of a second memory cell M 2 C n in the second memory page MP 2 , the first word line signal SWL 1 and the first select gate signal SSG 1 are at the second voltage VDD, the source line signal and the bit line signal received by the second memory cell M 2 C n are at the third voltage GND, and the second control line signal SCL 12 and the second erase line signal SEL 12 are at the first voltage VPP and the fourth voltage VEE respectively so the selected second memory cell M 2 C n can be programmed. However, since the first memory page MP 1 is unselected during the programming operation of the second memory cell M 2 C n in the second memory page MP 2 , the first control line signal SCL 1 and the first erase line signal SEL L can be at the third voltage GND so the unselected first memory cells M 1 C 1 to M 1 C N will not be programmed even with the first word line signal SWL 1 and the first select gate signal SSG 1 being at the second voltage VDD. Also, in this case, the source line signal SSL n and the bit line signal SBL n can be at the second voltage VDD or the third voltage GND.

Similarly, when the second memory page MP 2 is selected and the first memory page MP 1 is unselected during an erase operation, the first erase line signal SEL 1 can be at the third voltage GND while the second erase line signal SEL 12 can be at the fourth voltage VEE so the unselected first memory cells M 1 C 1 to M 1 C N will not be erased during the erase operation of a second memory cell in the second memory page MP 2 .

Therefore, the memory array 300 can arrange the memory page in an efficient way by sharing signal lines while preserving the flexibility of memory operations. Also, in some embodiments of the present invention, the memory array 300 may include even more memory pages with similar connections as the second memory page MP 2 according to the system requirement.

FIG. 7 shows a memory array 400 according to one embodiment of the present invention. The memory array 400 includes a first memory page MP 1 and a second memory page MP 2 ′. The second memory page MP 2 ′ in FIG. 7 is similar to the second memory page MP 2 in FIG. 6 . However, the second memory page MP 2 ′ includes a second word line WL 12 , a second select gate line SG 12 , and a plurality of second memory cells M 2 C′ 1 to M 2 C′ N .

The second word line WL 12 is for receiving a second word line signal SWL 12 , and the second select gate line SG 12 is for receiving a second select gate signal SSG 12 .

Each of the plurality of second memory cells M 2 C′ 1 to M 2 C′ N includes a word line node, a select gate, a control node, an erase node, a bit line node, and a source line node. The word line nodes of the second memory cells M 2 C′ 1 to M 2 C′ N are coupled to the second word line WL 12 , and the select gates of the second memory cells M 2 C′ 1 to M 2 C′ N are coupled to the second select gate line SG 12 . The control nodes of the second memory cells M 2 C′ 1 to M 2 C′ N are coupled to the first control line CL 1 , and the erase nodes of the second memory cells M 2 C′ 1 to M 2 C′ N are coupled to the first erase line EL 1 . The bit line nodes of the second memory cells M 2 C′ 1 to M 2 C′ N are for receiving different bit line signals SBL 11 to SBL 1N , and the source line nodes the second memory cells M 2 C′ 1 to M 2 C′ N are for receiving different source line signals SSL 11 to SSL 1N .

That is, the first memory page MP 1 and the second memory page MP 2 ′ can share the same control line CL 1 and the same erase line EL 1 . However, since the first memory page MP 1 and the second memory page MP 2 ′ are coupled to different word lines WL 1 and WL 12 and different select gate lines SG 1 and SG 12 , the second memory cells M 2 C′ 1 to M 2 C′ N in the second memory page MP 2 ′ can still be operated properly with the signals shown in Table 1.

For example, during a programming operation of the second memory cell M 2 C′ n in the second memory page MP 2 , the source line signal and the bit line signal received by the second memory cell M 2 C′ n can be at the third voltage GND, the first control line signal SCL 1 and the first erase line signal SEL 1 can be at the first voltage VPP and the fourth voltage VEE respectively, and the second word line signal SWL 12 and the second select gate signal SSG 12 can be at the second voltage VDD so the second memory cell M 2 C′ n can be programmed. However, since the first memory page MP 1 is unselected during the programming operation of the second memory cell M 2 C′ n in the second memory page MP 2 , the source line signal and the first select gate signal received by the first memory cells M 1 C 1 to M 1 C N , the first word line signal SWL 1 , and the bit line signal SBL n can be all at the third voltage GND or all at the second voltage VDD so the unselected first memory cells M 1 C 1 to M 1 C N will not be programmed even with the first control line signal SCL 1 and the first erase line signal SEL L being at the first voltage VPP and the fourth voltage VEE respectively. Namely, in this case, the select transistors of the first memory cells M 1 C 1 to M 1 C N can be turned off so the first memory cells M 1 C 1 to M 1 C N will not be programmed.

In FIG. 6 , the first memory page MP 1 and the second memory page MP 2 are disposed along the direction X, however, in some embodiments, the memory array may include other memory pages disposed along the direction Y with respect to the first memory page MP 1 .

FIG. 8 shows a memory array 500 according to one embodiment of the present invention. The memory array 500 includes a first memory page MP 1 , a second memory page MP 2 , and a third memory page MP 3 . The first memory page MP 1 and the second memory page MP 2 are disposed along the direction X. The first memory page MP 1 and the third memory page MP 3 are disposed along the direction Y.

The third memory page MP 3 includes a third word line WL 21 , a third select gate line SG 21 , a third control line CL 21 , a third erase line EL 21 , and a plurality of third memory cells M 3 C 1 to M 3 C N .

The third word line WL 21 is for receiving a third word line signal SWL 21 , and third select gate line SG 21 is for receiving a third select gate signal SSG 21 . The third control line CL 21 is for receiving receive a third control line signal SCL 21 , and the third erase line EL 21 is for receiving a third erase line signal SEL 21 . Each of the plurality of third memory cells M 3 C 1 to M 3 C N includes a word line node, a select gate, a control node, an erase node, a bit line node, and a source line node. The word line nodes of the third memory cells M 3 C 1 to M 3 C N are coupled to the third word line WL 21 , and the select gates of the third memory cells M 3 C 1 to M 3 C N are coupled to the third select gate line SG 21 . The control nodes of the third memory cells M 3 C 1 to M 3 C N are coupled to the third control line CL 21 , and the erase nodes of the third memory cells M 3 C 1 to M 3 C N are coupled to the third erase line EL 21 . The bit line nodes of the third memory cells M 3 C 1 to M 3 C N are coupled to bit line nodes of corresponding first memory cells M 1 C 1 to M 1 C N in the first memory page MP 1 for receiving corresponding bit line signals SBL 1 to SBL N , and the source line nodes of the third memory cells M 3 C 1 to M 3 C N are coupled to source line nodes of corresponding first memory cells M 1 C 1 to M 1 C N in the first memory page MP 1 for receiving the corresponding source line signals SSL 1 to SSL N .

Since the first memory cells M 1 C 1 to M 1 C N and the third memory cells M 3 C 1 to M 3 C N receive different control line signals SCL 1 and SCL 21 , different erase line signal SEL 1 and SEL 21 , different word line signals SWL 1 and SWL 21 , and different select gate signals SSG 1 and SSG 21 , the third memory cells M 3 C 1 to M 3 C N can receive the same bit line signals SBL 1 to SBL N and the same source line signals SSL 1 to SSL N as the first memory cells M 1 C 1 to M 1 C N without being interfered by the operations of the first memory cells M 1 C 1 to M 1 C N .

Table 2 shows voltages of the signals received by the first memory cell M 1 C n of the first memory cells M 1 C 1 to M 1 C N when the first memory page MP 1 is selected or unselected for different operations.

According to Table 2, when the first memory page MP 1 is not selected, the first control line signal SCL 1 can be at the third voltage GND so that the memory cell M 1 C n in the unselected memory page MP 1 will not be program. In this case, the first select gate signal SSG 1 and the first word line signal SWL 1 can be at any voltages, such as the second voltage VDD when the second memory page MP 2 is selected. Also, the source line signal SSL n , the bit line signal SBL n , and the first erase line signal SEL 1 , can be at any voltages, such as at the third voltage GND when the third memory page MP 3 is selected. Moreover, in some embodiments, the fourth voltage VEE may be at a same level as the first voltage VPP.

For example, during a programming operation of the third memory cell M 3 C n in the third memory page MP 3 , i.e. the third memory page MP 3 is selected, the third control line signal SCL 21 and the third erase line signal SEL 21 can be at the first voltage VPP and the fourth voltage VEE respectively, the third select gate signal SSG 21 and the third word line signal SWL 21 can be at the second voltage VDD, and the source line signal SSL n and the bit line signal SBL n can be at the third voltage GND so the third memory cell M 3 C n can be programmed. However, since the first memory page MP 1 is unselected during the programming operation of the third memory cell M 3 C n in the third memory page MP 3 , the first control line signal SCL 1 can be at the third voltage GND so the unselected first memory cell M 1 C n will not be programmed.

In some embodiments of the present invention, more memory pages may be included in the memory array 500 along the direction X with respect to the first memory page MP 1 and with signal connections similar to the second memory page MP 2 . That is, memory pages disposed along the direction X with respect to the first memory page MP 1 will all be coupled to the first word line WL 1 and the first select gate line SG 1 . Similarly, more memory pages may be included in the memory array 500 along the direction Y with respect to the first memory page MP 1 and with signal connections similar to the third memory page MP 3 . That is, memory cells in the memory pages disposed along the direction Y with respect to the first memory page MP 1 will receive the same bit line signal SBL 1 to SBL N and the same source line signal SSL 1 to SSL N as the corresponding first memory cells M 1 C 1 to M 1 C N . Consequently, the memory array 500 is able to arrange even more memory pages disposed in different directions according to the system requirement.

In addition, since different memory pages in the memory array 500 can share some signal lines, the memory array 500 can use the limited circuit area efficiently while preserving the flexibility of memory operations.

Also, in some embodiments of the present invention, the memory array 500 may include the first memory page MP 1 and the third memory page MP 3 without the second memory page MP 2 if the system has no sufficient space in the direction X.

In summary, the memory array provided by the embodiments of the present invention can arrange memory cells in different memory pages along different direction, and use the limited circuit area efficiently while preserving the flexibility of memory operations.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.