Low power circuit for amplifying a voltage without using resistors

This invention relates generally to electronic circuits, and more specifically to amplification of signals in low power consumption circuits.

Low power consumption circuits (circuits consuming less than 5 μW) that amplify a small magnitude voltage typically use resistors that have very high ohmic values to maintain low currents. Examples of such low power consumption circuits are low-power voltage reference circuits and low-power temperature sensor circuits. A bandgap voltage reference circuit is a temperature-independent voltage reference circuit that outputs a fixed DC voltage at or near a bandgap voltage of a semiconductor substrate on which the voltage reference circuit resides. The extrapolated bandgap voltage of silicon at zero kelvin is 1.22V.

With most low-power bandgap voltage reference circuits, there is a need to amplify a small signal of a few to tens of millivolts into a larger signal of several hundreds of millivolts. In some known low-power bandgap voltage reference circuits, the small signal that is amplified is a proportional-to-absolute-temperature (PTAT) voltage. If resistors are used in such known circuits, a drop of several hundreds of millivolts across the resistors is needed, which requires resistors having values in the range of tens of megaohms so that the current is limited to nanoamps. Such high ohmic value resistors occupy very large areas, which result in high area cost and/or impose a minimum power constraint. This unfavorable power/area trade-off usually determines a minimum power that can be obtained at an acceptable area cost.

Several low-power bandgap voltage reference circuits that do not use resistors, and instead use metal-oxide-semiconductor (MOS) transistors, are known. However such known circuits do not provide sufficient linearity because of the presence of various error sources such as second-order effects. Furthermore, such known circuits are subject to fabrication process and spread. Also, such known circuits require extensive trimming. Consequently, such known circuits are much less accurate than conventional bandgap voltage reference circuits that employ resistors.

The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 is a schematic of a first type of cell comprising MOS transistors, in accordance with one embodiment of the present invention.

FIG. 2 is a schematic of a second type of cell comprising MOS transistors, in accordance with one embodiment of the present invention.

FIG. 3 is a graph of a family of differential outputs of a cell, such as the cell of FIG. 1 or FIG. 2 .

FIG. 4 is a schematic of a low power consumption bandgap voltage reference circuit in accordance with one embodiment of the present invention.

FIG. 5 is a schematic of a low power consumption bandgap voltage reference circuit in accordance with another embodiment of the present invention.

FIG. 6 is a schematic of a low power consumption bandgap voltage reference circuit in accordance with yet another embodiment of the present invention.

FIG. 7 is a schematic of a low power consumption temperature sensor circuit in accordance with one embodiment of the present invention.

Circuits in accordance with embodiments of the present invention employ compact structures, or cells, comprising metal-oxide-semiconductor (MOS) transistors instead of resistors to amplify a small magnitude signal. Embodiments may amplify a small magnitude PTAT voltage. However, circuits in accordance with the present invention do not use MOS transistors to produce a PTAT voltage. Instead, embodiments of the present invention use two bipolar junction transistors (BJTs) to produce the PTAT voltage, as done with high-precision bandgap voltage reference circuits. Circuits in accordance with the present invention use stacked cells of MOS transistors that are actively controlled (using a closed-loop structure) to accurately replicate the small magnitude signal.

A circuit in accordance with the present invention adjusts, through feedback, a difference between gate-to-source voltages of two MOS transistors. A feedback loop around one cell forces a difference between gate-to-source voltages of two MOS transistors in the cell to become equal to a small magnitude voltage that is inputted into the cell. A control voltage produced by the feedback loop is applied to all other cells in the circuit. Each cell then produces a copy of the small magnitude voltage input signal. The individual cells are cascaded in order to build an amplified copy of the small magnitude voltage.

FIG. 1 is a schematic of a first type of cell 102 comprising MOS transistors. The cell 102 comprises MOS transistor M 1 111 configured as a diode, MOS transistor M 2 112 , and MOS transistor M 3 113 . A drain terminal of MOS transistor M 2 112 is coupled to V DD and a source terminal of MOS transistor M 2 is coupled to a current source 115 . A voltage V m is present at the gate of MOS transistor M 2 112 . A source terminal of MOS transistor M 3 113 is coupled to V DD and a drain terminal of MOS transistor M 3 is coupled to drain and gate terminals of MOS transistor M 1 111 . A control voltage V C is inputted to the gate of MOS transistor M 3 113 . A source terminal of MOS transistor M 1 111 is coupled to the current source 115 . A voltage V p is present at the gate of MOS transistor M 1 111 . A voltage defined as a difference between V p and V m may be considered to be the output of the cell 102 . The following relationship exists in cell 102 : V p −V m =V GS1 −V GS2 =ΔV GS . The cell 102 does not include any BJTs. Advantageously, the cell 102 does not include any resistors. When used alone, the cell 102 receives, as an input, the control voltage V C , and then the cell produces, as an output, the voltage (V p −V m ). Because the gates of M 1 111 and M 2 112 are floating with respect to V DD and ground, a plurality of the cells 102 can be cascaded, or stacked, as shown in FIGS. 4-7 .

FIG. 2 is a schematic of a second type of cell 202 comprising MOS transistors. The cell 202 comprises MOS transistor M 1 221 , MOS transistor M 2 222 configured as a diode, MOS transistor M 3 223 , and MOS transistor M 4 224 . A source terminal of MOS transistor M 3 223 is coupled to a current source 225 . A drain terminal of MOS transistor M 3 223 is coupled to a node 220 . The control voltage V C is inputted at the gate of MOS transistor M 3 223 . A source terminal of MOS transistor M 4 224 is coupled to the current source 225 . A drain terminal of MOS transistor M 4 224 is coupled to gate and drain terminals of a MOS transistor M 2 222 and to a gate of a MOS transistor M 1 221 . A bias voltage V B is inputted at the gate of MOS transistor M 4 224 . A source terminal of MOS transistor M 2 222 is coupled to the node 220 . A drain terminal of MOS transistor M 1 221 is also coupled to the node 220 . A voltage V p is present at the node 220 . A voltage V m is present at a source terminal of MOS transistor M 1 221 . A voltage defined as a difference between V p and V m may be considered to be the output of the cell 202 . The following relationship exists in cell 202 : V p −V m =V GS1 −V GS2 =ΔV GS . The cell 202 does not include any BJTs. Advantageously, the cell 202 does not include any resistors. Because the gates of M 1 221 and M 2 222 are floating with respect to V DD and ground, a plurality of the cells 202 can be cascaded, or stacked. When the cell 202 is used as part of a larger circuit, as described hereinafter, the source terminal of MOS transistor M 1 221 is also coupled to other circuitry including to ground potential. When used alone, the cell 202 receives, as an input, the control voltage V C , and then the cell 202 produces, as an output, the voltage (V p −V m ).

In the illustrated embodiments, MOS transistors M 1 and M 2 are of a same size, and a gate-to-source (V GS ) voltage difference between MOS transistors M 1 and M 2 is adjusted by controlling a relationship between their drain currents, to obtain the desired ΔV GS =ΔV BE . In the illustrated embodiments, the drain current of M 1 is larger than the drain current of M 2 in order to produce V GS1 −V GS2 =ΔV BE (V GS1 is greater than V GS2 ). In another embodiment, MOS transistors M 1 and M 2 have same drain currents and have different W/L ratios to obtain the desired ΔV GS =ΔV BE . In yet another embodiment, MOS transistors M 1 and M 2 have different drain currents and different W/L ratios to obtain the desired ΔV GS =ΔV BE .

FIG. 3 is a graph of a family of differential outputs of a cell, such as cell 102 or cell 202 . In the graph of FIG. 3 , the vertical, or y-axis, represents voltage and the horizontal, or x-axis, represents temperature. FIG. 3 shows how a voltage (V p −V m ) changes with respect to temperature for eight (8) different values of I d1 /I d2 . Other values of I d1 /I d2 are possible, but only eight (8) representative values of values of I d1 /I d2 are shown in FIG. 3 , for simplicity of illustration. FIG. 3 shows that, for each representative value of I d1 /I d2 , (V p −V m ) increases with temperature. Because the graph of each voltage versus temperature appears in FIG. 3 as almost a straight line, it can be concluded that the voltage (V p −V m ) has nearly PTAT behavior for a given I d1 /I d2 . The graph of FIG. 3 shows a range 308 of values of I d1 /I d2 over which ΔV GS may be adjusted using the control voltage V. In one embodiment, the range 308 is 600 mV.

By controlling V C , the ratio I d1 /I d2 can be controlled. The ratio I d1 /I d2 , in turn, adjusts ΔV GS . There is a range 308 over which ΔV GS may be successfully adjusted through V C . For proper operation, (V p −V m ) must fall within the range 308 over which ΔV GS may be successfully adjusted. ΔV GS can be adjusted to any value within the range 308 by controlling I d1 /I d2 . A top limit of the range 308 corresponds to a ΔV GS produced with a maximum I d1 /I d2 that is practical to implement. The behavior shown on the graph of FIG. 3 is basically the same for all cases of I (for the various MOS operation region cases) with some change only in the y-axis values. Nevertheless, for any given case, provided that (V p −V m ) falls within the range 308 , ΔV GS can be made equal to (V p −V m ) by feedback, as explained hereinbelow with regard to FIGS. 4-7 .

The graph of FIG. 3 shows that V p −V m is nearly PTAT and that (V p −V m ) increases almost linearly with temperature for a given I d1 /I d2 . Provided that (V p −V m ) falls within the range 308 , the graph of FIG. 3 can be obtained even if one of M 1 and M 2 is operated in strong inversion and the other of M 1 and M 2 is operated in weak or moderate inversion.

When used in a resistor-less amplifying circuit, the cells 102 and 202 are particularly suitable to track a nearly-PTAT small magnitude input signal because a nearly-PTAT signal requires smaller variations of I d1 /I d2 over temperature compared to when a signal is not nearly-PTAT. The circuits in accordance with the embodiment are particularly suitable to track a nearly-PTAT small magnitude input signal also because the ΔV GS output of each cell 102 and 202 is, by its design, nearly-PTAT when a constant ratio between the MOS transistor currents (a mid-point in the control range) is maintained.

FIG. 4 is a schematic of a low power consumption bandgap voltage reference circuit 402 in accordance with one embodiment of the present invention. In one embodiment, the bandgap voltage reference circuit 402 is implemented as an integrated circuit 404 disposed on a silicon substrate 406 . The bandgap voltage reference circuit 402 includes BJT Q 1 421 and BJT Q 2 422 . The bandgap voltage reference circuit 402 also includes a resistor-less amplifying circuit coupled to the aforesaid BJTs. In the illustrated embodiment, the BJTs provide a small magnitude signal to the resistor-less amplifying circuit. The resistor-less amplifying circuit amplifies the small magnitude signal. The resistor-less amplifying circuit comprises a plurality of the first type of cell 102 . The resistor-less amplifying circuit also comprises a closed-loop structure, or feedback loop 420 , as described hereinbelow. In the illustrated embodiment of the bandgap voltage reference circuit 402 , three cells are shown: a first cell 411 , a second cell 412 and an n th cell 413 . Each cell 411 , 412 and 413 has an identical structure and is identically biased. The cells of the bandgap voltage reference circuit 402 are stacked, or cascaded together, such that a differential voltage that occurs at each cell can be added together. A sum of the differential voltage that occurs at each cell contributes to an output signal, V REF , of the bandgap voltage reference circuit 402 .

An emitter terminal of BJT Q 1 421 is coupled to a current source I 1 . Base and collect terminals of BJT Q 1 421 are coupled to ground. An emitter terminal of BJT Q 2 422 is coupled to a current source I 2 . Base and collect terminals of BJT Q 2 422 are coupled to ground. The base-to-emitter voltage of BJT Q 1 421 (V BE1 ) depends upon a value of I 1 and a size of Q 1 . The base-to-emitter voltage of BJT Q 2 422 (V BE2 ) depends upon a value of I 2 and a size of Q 2 . ΔV BE =V BE1 −V BE2 . In the bandgap voltage reference circuit 402 , ΔV BE has PTAT behavior. To generate a ΔV BE that has PTAT behavior, it is necessary that Q 1 and Q 2 be of different sizes and/or that I 1 and I 2 have different values. In one embodiment, Q 2 is larger than Q 1 , and I 1 =I 2 . In one such embodiment, Q 2 is 8 to 25 times larger than Q 1 .

In the bandgap voltage reference circuit 402 , the feedback loop 420 goes around the first cell 411 . The feedback loop 420 includes a differential amplifier 423 . An inverting input terminal of the differential amplifier 423 is coupled to an emitter terminal of BJT Q 1 421 at which the voltage V BE1 is obtained. A non-inverting input terminal of the differential amplifier 423 is coupled to a gate of MOS transistor M 11 . An output terminal of the differential amplifier 423 is coupled to a gate of MOS transistor M 31 . The output terminal of the differential amplifier 423 is also coupled to a gate of a MOS transistor in each of the other cells that corresponds to MOS transistor M 31 in the first cell 411 . Control voltage V C is outputted by the differential amplifier 423 . The gain of the feedback loop 420 is selected to be high enough so that a systematic offset can be neglected. A voltage difference between the non-inverting and the inverting input terminals of the amplifier 421 represents the systematic offset.

A small magnitude differential voltage is applied to the first cell 411 of the resistor-less amplifying circuit as an input signal thereto. More specifically, one end of the small magnitude differential voltage is applied at the inverting input terminal of the differential amplifier 423 and the other end of the small magnitude differential voltage is applied at the gate of MOS transistor M 21 . When an input signal is applied to the first cell 411 , the bandgap voltage reference circuit 402 produces a value of V C as a result of the feedback loop 420 . In the illustrated embodiment, BJT Q 1 421 and BJT Q 2 422 produce the small magnitude differential signal.

The small magnitude differential signal that BJT Q 1 421 and BJT Q 2 422 produce is ΔV BE . For purposes of analysis, it should be noted that the first cell 411 of the bandgap voltage reference circuit 402 has a differential voltage that consists of a difference between a gate-to-source voltage of MOS transistor M 11 and a gate-to-source voltage of MOS transistor M 12 , i.e., ΔV GS . A magnitude of ΔV GS is modifiable by a value of V C , which is coupled to the gate of M 31 of the first cell 411 . By feedback, the differential voltage ΔV GS at the first cell 411 is adjusted to become equal to ΔV BE . In other words, the feedback loop 420 determines a particular value of V C that causes ΔV GS to equal ΔV BE at the first cell 411 .

V BE2 , which has complementary-to-absolute-temperature (CTAT) behavior, is applied to the gate of MOS transistor M 21 . The feedback loop 420 causes V BE1 to occur at the gate of MOS transistor M 11 . If V BE1 is higher than the gate voltage of M 11 , then V C will decrease, which means that V GS of M 31 will increase, so that the current through M 31 will increase. As the current through M 31 increases, M 11 drains more current and produces a higher V GS for M 11 . Therefore, the gate of M 11 increases until the gate voltage of M 11 equals V BE1 .

By adjusting a gate voltage of M 31 , the feedback loop 420 forces ΔV GS between M 11 and M 21 to equal the difference between the base-to-emitter voltages of the BJTs, Q 1 421 and Q 2 422 . In other words, the feedback loop 420 forces ΔV GS to become equal ΔV BE for the first cell 411 . Therefore, as a result of feedback, a voltage at the gate of M 11 with respect to ground is V BE2 ΔV BE .

The particular value of V C that forced ΔV GS to become equal to ΔV BE in the first cell 411 is then applied to each of the other cells, including cell 412 and cell 413 , in a similar manner, and each of the other cells will create its own ΔV GS ΔV BE . By applying the particular value of V C to a gate of a MOS transistor in each cell that corresponds to M 31 , ΔV GS in all the other cells in the bandgap voltage reference circuit 402 also become equal to ΔV BE . The gate of MOS transistor M 11 of cell 411 is coupled to the gate of MOS transistor M 22 of cell 412 , thereby allowing the differential voltage that occurs across cell 411 to be added to the differential voltage that occurs across cell 412 . As a result, a voltage at the gate of M 12 with respect to ground is V BE2 +2·ΔV BE . Consequently, a voltage produced across the entire stack of cells becomes an amplified version of ΔV BE . The other cells are coupled together in an analogous manner, thereby allowing the N stacked cells of the resistor-less amplifying circuit to produce a voltage equal to N·ΔV BE . The voltage N·ΔV BE is part of the voltage outputted by the bandgap voltage reference circuit 402 . The other part of the voltage outputted by the bandgap voltage reference circuit 402 is V BE2 . When N cells are stacked, as in the bandgap voltage reference circuit 402 , the output voltage V REF of the bandgap voltage reference circuit with respect to ground becomes V BE2 plus the sum of N voltages, each voltage being ΔV BE . In other words, V REF =V BE2 +N·ΔV BE . Consequently, the output voltage V REF can be looked upon as V BE2 plus the product of ΔV BE multiplied by an integer.

Typical N=8 for low-power designs of the bandgap voltage reference circuit 402 . Because N is integer, changing only N results in a gross adjustment to the value of V REF and to the behavior of V REF with respect to temperature. After choosing an appropriate N, fine tuning of V REF is done by adjusting collector currents of BJT Q 1 421 and BJT Q 2 422 to set appropriate thermal coefficients for V BE2 and ΔV BE . ΔV BE is very linear over temperature. ΔV BE can be written as a function of the absolute temperature T as ΔV BE =C*T. V BE can also be written as a function of the absolute temperature T as V BE =A−B*T. The parameter A is a constant, i.e., it does not depend on biasing currents. The parameters B and C depend on biasing currents, and these parameters are first-order thermal coefficients. Reasonable values of biasing currents would typically make B about 2 mV/K and C about 0.2 mV/K. In other words, by adjusting the biasing currents B and C can be adjusted to any real value near the aforesaid reasonable values. Considering V BE2 =A−B*T and ΔV BE =C*T as written above, and given V REF =V BE2 +N*ΔV BE , then it follows that V REF =A+(N*C−B)*T. To have no variation over temperature, values are chosen such that N*C=B. When N*C=B is substituted into the preceding equation, the results is V REF =A (bandgap reference). Because N is an integer, B needs to be a multiple of C in order to make N*C=B. The parameter B is made a multiple of C by adjusting the biasing currents, i.e., adjusting B and C values.

When implementing bandgap voltage reference circuit 402 , I 1 and I 2 are varied so that N×ΔV BE rises with temperature (PTAT behavior) at a same rate that V BE2 decays with temperature (CTAT behavior). First, it is determined which current density values to apply to BJT Q 1 421 and BJT Q 2 422 based on technology curves, power constraints, and other factors. Then, the values of B and C are obtained from the current densities. Next, the current density values are adjusted to make B a multiple of C, i.e., B/C=N. The value of N determines the number of cells needed to produce V REF .

For minimum power consumption, BJT Q 1 421 and BJT Q 2 422 are selected to be of minimum sizes (and equal areas), and I 1 is selected to be greater than I 2 (e.g., I 1 =24×I 2 ). However, for a simple implementation I 1 =I 2 , and emitter area of Q 2 >>emitter area of Q 1 .

FIG. 5 is a schematic of a low power consumption bandgap voltage reference circuit 502 in accordance with another embodiment of the present invention. In most respects, the bandgap voltage reference circuit 502 is similar to the bandgap voltage reference circuit 402 ; therefore, only the differences will be emphasized hereinafter.

In the bandgap voltage reference circuit 402 (see FIG. 4 ), scaling of ΔV BE was by an integer factor. However, in the bandgap voltage reference circuit 502 (see FIG. 5 ), scaling is done by a non-integer factor notwithstanding N being an integer. To accomplish scaling by a non-integer factor, a single feedback loop 520 is closed around K number of cells in order to generate input signal copies scaled by (1/K), where K is an integer greater than 1 and less than N, and where N is a total number of cells in the bandgap voltage reference circuit 502 . In the bandgap voltage reference circuit 502 , the feedback loop 520 is around two cells. Therefore, for the bandgap voltage reference circuit 502 , K=2.

In the illustrated embodiment of the bandgap voltage reference circuit 502 , three cells are shown: a first cell 411 , a second cell 412 and an nth cell 413 . The bandgap voltage reference circuit 502 includes the feedback loop 520 around both the first cell 411 and the second cell 412 . The feedback loop 520 includes a differential amplifier 523 . An inverting input terminal of the differential amplifier 523 is coupled to an emitter terminal of BJT Q 1 421 at which the voltage V BE1 is obtained. A non-inverting input terminal of the differential amplifier 523 is coupled to a gate of MOS transistor M 12 of cell 412 . The output terminal of the differential amplifier 523 is coupled to a gate of MOS transistor M 31 , M 32 , . . . , M 3 N in each cell. Control voltage V C is outputted by the differential amplifier 523 . The gain of the feedback loop 520 is selected to be high enough so that the systematic offset can be neglected.

A feedback loop around K cells creates a 1/K fraction of ΔV BE . The feedback loop 520 forces ΔV GS +ΔV GS =ΔV BE . As a result, each cell 411 and 412 copies 1/2 ΔV BE . Therefore, if the total number of cells in the bandgap voltage reference circuit 502 was three, i.e., N=3, then the output V REF would be V BE2 plus 3/2 ΔV BE . Consequently, if the bandgap voltage reference circuit 502 had three (3) cells, the signal ΔV BE would be multiplied by a non-integer.

If instead, the total number of cells in the bandgap voltage reference circuit 502 was four, i.e., N=4, the output V REF would be V BE2 plus 4/2 ΔV BE . Consequently, if the bandgap voltage reference circuit 502 had four (4) cells, the signal ΔV BE would be multiplied by an integer.

If instead, the total number of cells in the bandgap voltage reference circuit 502 was five, i.e., N=5, the output V REF would be V BE2 plus 5/2 ΔV BE . Consequently, if the bandgap voltage reference circuit 502 had five cells, the signal ΔV BE would be multiplied by a non-integer.

If the total number of cells in another bandgap voltage reference circuit (not shown) was five, i.e., N=5, and if such other circuit had a similar feedback loop closed around three cells (instead of two cells) but was otherwise similar to FIG. 5 , the feedback loop would force ΔV GS +ΔV GS +ΔV GS =ΔV BE . Each cell in such other circuit would copy 1/3 ΔV BE . Therefore, the output V REF of such other circuit would be V BE2 plus 5/3 ΔV BE .

An advantage, under certain circumstances, of closing the feedback loop 520 around more than one cell is the feedback having a more accurate effect compared to when a feedback loop is closed around only one cell.

FIGS. 4 and 5 show that V REF is taken at the output of the rightmost cell. However, taking V REF from one of the nodes between the cells can be a way of implementing coarse trimming of V REF .

FIG. 6 is a schematic of a low power consumption bandgap voltage reference circuit 602 in accordance with yet another embodiment of the present invention. The bandgap voltage reference circuit 602 comprises a plurality of the second type of cell 202 each of which is described in detail hereinabove with respect to FIG. 2 . Each cell 631 , 632 , 633 , 634 and 635 of the bandgap voltage reference circuit 602 has an identical structure (except for MOS transistors M 11 , M 12 , M 13 , . . . , M 1 N) and is identically biased. In the bandgap voltage reference circuit 602 , MOS transistors M 11 , M 12 , M 13 , . . . , M 1 N conduct currents I, 2 I, 3 I, . . . , NI. Hence, parallel transistors are added (1×, 2×, 3×, . . . , N×) to maintain current I through the unitary MOS transistors of each cell.

In the illustrated embodiment of the bandgap voltage reference circuit 602 , five cells are shown, which are, from right to left in FIG. 6 : cell 631 , cell 632 , cell 633 , an n th cell 634 and an initial cell 635 . The bandgap voltage reference circuit 602 includes a feedback loop 620 around the initial cell 635 . The feedback loop 620 includes a differential amplifier 623 . A non-inverting input terminal of the differential amplifier 623 is coupled to a drain terminal of MOS transistor M 1 . An inverting input terminal of the differential amplifier 623 is coupled to an emitter terminal of BJT Q 1 641 at which V BE1 is present. An output terminal of the differential amplifier 623 is coupled to a gate of MOS transistor M 3 . The differential amplifier 623 outputs control voltage V C . For purposes of analysis, it can be considered that an input signal is applied between source and drain terminals MOS transistor M 1 of the initial cell 635 . The control voltage V C is applied to a gate of M 3 . Because of feedback, the closed-loop structure of the bandgap voltage reference circuit 602 produces a V C that has a particular value. As a result of the particular value of V C controlling a gate voltage of MOS transistor M 3 , the feedback loop forces ΔV GS between MOS transistors M 1 and M 2 to equal the difference between the base-to-emitter voltages of the BJTs, Q 1 641 and Q 2 642 . In other words, the feedback loop 620 forces ΔV GS to equal ΔV BE for the initial cell 635 . Because the particular value of V C that forced ΔV GS =ΔV BE in the initial cell 635 is also applied to each of the other cells in a similar manner, then each of the other cells creates a ΔV GS =ΔV BE of their own.

The (N−1) stacked cells (for example, cell 631 , cell 632 and cell 633 ) of FIG. 6 produce a voltage of (N−1)·ΔV BE . Therefore, V REF =V BE1 +N·ΔV BE =V BE2 +(N+1)·ΔV BE .

All the current consumed by the bandgap voltage reference circuit 602 goes eventually to the BJTs Q 1 641 and Q 2 642 . In other words, no current goes to ground without first going through the BJTs 641 and 642 . This means that the bandgap voltage reference circuit 602 consumes the lowest possible current. When designing the bandgap voltage reference circuit 602 , a first step is to determine which value of current is needed to bias Q 1 and Q 2 . Then, the biasing of the MOS transistors is determined.

For very low power designs, it is advantageous that the BJTs 641 and 642 do not have their own, additional, current sources that consume power. Compared to embodiment shown in FIGS. 4 and 5 , the embodiment shown in FIG. 6 enables lower power consumption for the same BJT bias conditions. However, if the MOS transistors are operated in strong inversion, then the bandgap voltage reference circuits 402 and 502 may be advantageous over the bandgap voltage reference circuit 602 .

Corner and mismatch simulations of the bandgap voltage reference circuit 602 shows that V REF is 1.20V+10 mV after trimming for temperatures between −40° C. and 150° C., and that the maximum current consumption is 502 nA at 150° C. and 5.5V supply. Typical-case simulation of the bandgap voltage reference circuit 602 shows that V REF is 1.201V+1.1 mV for temperatures between −40° C. and 150° C., and that the current consumption is 250 nA at 25° C. and 5V supply. The simulations reveal that V REF outputted by the bandgap voltage reference circuit 602 is almost equal to the bandgap voltage of silicon and is nearly temperature independent.

On a given technology, the bandgap voltage reference circuits 402 , 502 and 602 can be made as accurate as a conventional bandgap voltage reference circuit that employs resistors. The accuracy of the bandgap voltage reference circuits 402 , 502 and 602 is dependent upon matching of corresponding MOS transistors in each cell are matched.

FIG. 7 is a schematic of a low power consumption temperature sensor circuit 702 in accordance with one embodiment of the present invention. The temperature sensor circuit 702 uses BJTs to produce highly accurate temperature-related signals and uses cells of matched MOS transistors to amplify those signals. The temperature sensor circuit 702 comprises a plurality of the second type of cell 202 . In the illustrated embodiment of the temperature sensor circuit 702 , five cells are shown, which are, from right to left in FIG. 7 : cell 731 , cell 732 , cell 733 , an n th cell 734 and an initial cell 735 . Each cell 731 , 732 , 733 , 734 and 735 of the temperature sensor circuit 702 has an identical structure (except for MOS transistors M 11 , M 12 , M 13 , . . . , M 1 N) and is identically biased. In the temperature sensor circuit 702 , MOS transistors M 11 , M 12 , M 13 , . . . , M 1 N conduct currents I, 2 I, 3 I, . . . , NI. Hence, parallel transistors are added (indicated by 1×, 2×, 3×, . . . , N× in FIG. 7 ) to MOS transistors M 11 , M 12 , M 13 , . . . , M 1 N to maintain a same current I through the unitary MOS transistors of each cell.

The temperature sensor circuit 702 includes a feedback loop 720 around the initial cell 735 . The temperature sensor circuit 702 uses the feedback loop 720 for precise replication of a voltage created by BJT Q 1 741 and BJT Q 742 . The feedback loop 720 includes a differential amplifier 723 . A non-inverting input terminal of the differential amplifier 723 is coupled to a drain terminal of MOS transistor M 1 . An inverting input terminal of the differential amplifier 723 is coupled to an emitter terminal of BJT Q 1 741 at which V BE1 is present. An output terminal of the differential amplifier 723 is coupled to a gate of MOS transistor M 3 . The differential amplifier 723 outputs control voltage V C . The gain of the feedback loop 720 is selected to be high enough so that the systematic offset can be neglected. In most respects, the temperature sensor circuit 702 is similar to the bandgap voltage reference circuit 602 ; therefore, only the differences will be emphasized hereinafter.

In the temperature sensor circuit 702 , MOS transistor M 1 N is stacked on top of ground potential rather than stacked on top of a BJT (as in the bandgap voltage reference circuit 602 ). In the temperature sensor circuit 702 , the stack of cascaded cells is referenced to ground to create a PTAT output. As a result, the output, V PTAT , is a voltage that is proportional to temperature. In the temperature sensor circuit 702 , V PTAT =N·ΔV BE because the N stacked cells start at ground potential, i.e., the source terminal of MOS transistor M 1 N is at ground potential.

With the temperature sensor circuit 702 , a threshold is detectable at a crossing between V BE and N·ΔV BE signals.

In one embodiment, V PTAT is coupled to a non-inverting input terminal of a comparator 750 . Another voltage V CTAT , such as V BE of BJT Q 2 742 , is coupled to an inverting input terminal of the comparator 750 . The comparator 750 toggles an over-temperature flag OT FLAG when V PTAT and V CTAT have a same value.

In another embodiment (not shown), a temperature sensor circuit, which is otherwise similar to the temperature sensor circuit 702 , is built using the first type of cell 102 instead of the second type of cell 202 ; however, in such other embodiment, the MOS transistors are re-oriented and there is polarity changed in a manner known by a person skilled in the art.

To be technically accurate, V GS , used hereinabove, should be interpreted to mean |V GS |, and V BE , used hereinabove, should be interpreted to mean |V BE |. This is because, for PMOS transistors and PNP BJTs, V SG (V SG =V S −V G ) instead of V GS , and V EB (V EB =V E −V B ) instead of V BE , respectively, should be used to represent positive voltages.

Each of the circuits in accordance with the present invention is implemented, in one embodiment, as an integrated circuit disposed on a silicon substrate.

In another embodiment (not shown), the circuits in accordance with the present invention can be used to amplify any differential voltage signal including those that are not related to BJTs, provided that such differential voltage signal falls within the range 308 shown in FIG. 3 .

In another embodiment (not shown), the circuits in accordance with the present invention can be used to amplify a single-ended signal because a single-ended signal can be viewed as a differential voltage with respect to ground potential or V DD .

Advantageously, the behavior of the output of the circuits in accordance with the present invention is not significantly dependent on MOS transistor operation region or process corners provided that a magnitude of ΔV BE is within a range over which ΔV GS may adjusted through control voltage V C .

Advantageously, the circuits in accordance with the present invention are not sensitive to MOS transistor parameters other than matching of MOS transistors, and, therefore, are not subject to some of the sources of distortion that adversely affect known circuits.

Advantageously, the circuits in accordance with the present invention compensate for systematic offsets (process deviations, model inaccuracies, etc.).

Compared to known circuits that employ resistors, the circuits in accordance with the present invention improve a power/area trade-off for low-power circuits. This results in lower cost (lower area usage for given power) or better performance (lower power for a given area). For example, when fabricated using 180 nm process, a circuit in accordance with the present invention encompasses an area one-eight the size of a similar circuit that employs resistors. Compared with known resistor-less circuits, the circuits in accordance with the present invention enable higher accuracy figures because such circuits are insensitive to process and other systematic sources of error.

Cascodes and/or other similar techniques may be added to the circuits in accordance with the invention, if needed, to reduce systematic offset.

To further improve accuracy, trimming structures may be added to the circuits in accordance with the present invention.

The term “coupled”, as used herein, is defined as “connected”, and encompasses the coupling of devices that may be physically, electrically or communicatively connected, although the coupling may not necessarily be directly, and not necessarily be mechanically. The term “configured to” describes hardware, software or a combination of hardware and software that is adapted to, set up, arranged, built, composed, constructed, designed or that has any combination of these characteristics to carry out a given function. The term “adapted to” describes hardware, software or a combination of hardware and software that is capable of, able to accommodate, to make, or that is suitable to carry out a given function.

The terms “a” or “an”, as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an”. The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The term “coupled”, as used herein, is not intended to be limited to a direct coupling or a mechanical coupling, and that one or more additional elements may be interposed between two elements that are coupled. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

The Detailed Description section, and not the Abstract section, is intended to be used to interpret the claims. The Abstract section may set forth one or more but not all embodiments of the invention, and the Abstract section is not intended to limit the invention or the claims in any way.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.