Cross-domain electrostatic discharge protection device

1. Field of the Invention

The present invention relates to an electrostatic discharge protection device, and in particular to a cross-domain electrostatic discharge protection device for integrated circuits.

2. Description of the Related Art

Generally, integrated circuits will include multiple power domains. A device may, for instance, include an input/output (I/O) circuit along with a core circuit, each of which may be associated with a different power domain (e.g., the I/O circuit may be associated with a high-voltage power domain, the core circuit may be associated with a low-voltage power domain, etc.). Thus, signals may travel from a high-voltage power domain to a low-voltage power domain. Typically, from an electrostatic discharge (ESD) protection design point of view, one of the most critical issues of cross-domain interface circuits is gate oxide breakdown of low-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs). For cross-power-domain ESD protection, ESD protection devices are required to be set between any pin-to-pin combination of voltage supplies or power nodes.

FIG. 1 shows an ESD protection scheme for cross-power-domain ESD protection. FIG. 2 shows an example of simple ESD protection for cross-power-domain. For example, two power domains VDD 1 -VSS 1 and VDD 2 -VSS 2 are applied in an integrated circuit (for brevity, the main portion and peripheral of the integrated circuit are not shown in FIGS. 1 and 2 ). In FIG. 1 , using six ESD cells 11 ˜ 16 can provide full ESD protection for any path of VDD 1 -VSS 1 , VDD 1 -VSS 2 , VDD 1 -VDD 2 , VDD 2 -VSS 1 , VDD 2 -VSS 2 and VSS 1 -VSS 2 , but it consumes too large an area. As a trade-off for area and cost requirements, some of the ESD cells may be removed. Thus, in FIG. 2 , a simple ESD protection scheme is provided. The simple scheme consumes a smaller area, but its ESD protection is degraded since some direct paths (such as VDD 1 -to-VSS 2 and VDD 2 -to-VSS 1 ) are not protected.

Accordingly, it is desirable to propose a cross-domain ESD protection cell (device) with a novel structure capable of providing sufficient ESD discharge paths and consuming less of an area.

According to an aspect of the invention, a cross-domain electrostatic discharge (ESD) protection device comprises: a deep n-well formed in a substrate; a first p-well and a second p-well formed in the deep n-well; a first n-well formed in the deep n-well and between the first p-well and the second p-well, the first n-well contacting the first p-well and the second p-well; a first p-type doped region and a second p-type doped region formed in the first n-well; a third P-type doped region and a fourth P-type doped region respectively formed in the first p-well and the second p-well; a first n-type doped region formed in the first p-well and between the third and first p-type doped regions; and a second n-type doped region formed in the second p-well and between the second and fourth P-type wells. The first p-type doped region is connected to a first voltage supply of a first power domain, the third p-type doped region and the first n-type doped region are connected to a second voltage supply of the first power domain. The second p-type doped region is connected to a third voltage supply of a second power domain, and the fourth p-type doped region and the second n-type doped region are connected to a fourth voltage supply of the second power domain, wherein the first and second power domains are different domains.

According to another aspect of the invention, the cross-domain electrostatic discharge protection device further comprises: a third n-type doped region formed in a first boundary region of the first p-well and the first n-well, and between the first n-type doped region and the first p-type doped region; a first gate structure formed on the first p-well and between the first n-type doped region and the third n-type doped region; a fourth n-type doped region formed in a second boundary region of the second p-well and the first n-well, and between the second n-type doped region and the second p-type doped region; and a second gate structure formed on the second p-well and between the second n-type doped region and the fourth n-type doped region. The first and second gate structures are respectively connected to the second voltage supply and the fourth voltage supply.

According to another aspect of the invention, the cross-domain electrostatic discharge protection device further comprises: a p-type bias region formed in the first n-well and between the first p-type doped region and the second p-type doped region; a fifth p-type doped region and a seventh p-type doped region respectively formed in the first p-well and the first n-well, and disposed between the first n-type doped region and the first p-type doped region; a sixth p-type doped region and an eighth p-type doped region respectively formed in the second p-well and the first n-well, and disposed between the second n-type doped region and the second p-type doped region; a third gate structure formed on the first n-well and between the first and seventh p-type doped regions; a fourth gate structure formed on the first n-well and between the second and eighth p-type doped regions. The fifth and seventh p-type doped regions are electrically connected and the sixth and eighth p-type doped regions are electrically connected, the third and fourth gate structures are connected to a detection node and the p-type bias region is connected to a bias voltage.

According to another aspect of the invention, the cross-domain electrostatic discharge protection device further comprises: an ESD detection and trigger circuit, connected to the first, second, third and fourth p-type doped region, the p-type bias region, and the third and fourth gate structures. It should be noted that the ESD detection and trigger circuit may comprise: a first diode having an anode and a cathode respectively connected to the third p-type doped region and the fourth p-type doped region; a second diode having a cathode and an anode respectively connected to the third p-type doped region and the fourth p-type doped region; a third diode and a fourth diode having anodes connected together and cathodes respectively connected to the third p-type doped region and the fourth p-type doped region; a capacitor connected between the anodes of the third and fourth diodes and the detection node; and a resistor connected between the detection node and the p-type bias region.

Furthermore, the cross-domain electrostatic discharge protection device may further comprise: a first PMOS transistor and a second PMOS transistor, connected in series, and the serially connected first and second PMOS transistors are further connected between the first voltage supply and the third voltage supply. The first and second PMOS transistors respectively connected to the third voltage supply and the first voltage supply, and bulks and a connection node of the first and second PMOS transistors are connected to the p-type bias region.

According to another aspect of the invention, a cross-domain electrostatic discharge protection device, comprises: a deep n-well formed in a substrate; a first p-well and a second p-well formed in the deep n-well; a first n-well formed in the deep n-well and between the first p-well and the second p-well, the first n-well contacting the first p-well and the second p-well; a first p-type doped region and a second p-type doped region formed in the first n-well; a third P-type doped region and a fourth P-type doped region respectively formed in the first p-well and the second p-well; a first n-type doped region formed in the first p-well and between the third and first p-type doped regions; and a second n-type doped region formed in the second p-well and between the second and fourth P-type wells (p 2 , p 4 ); a p-type bias region formed in the first n-well and between the first p-type doped region and the second p-type doped region; a fifth p-type doped region and a seventh p-type doped region respectively formed in the first p-well and the first n-well, and disposed between the first n-type doped region and the first p-type doped region; a sixth p-type doped region and an eighth p-type doped region respectively formed in the second p-well and the first n-well, and disposed between the second n-type doped region and the second p-type doped region; a third gate structure formed on the first n-well and between the first and seventh p-type doped regions; a fourth gate structure formed on the first n-well and between the second and eighth p-type doped regions; and an ESD detection and trigger circuit, connected to the first, second, third and fourth p-type doped region, the p-type bias region, and the third and fourth gate structures. The first p-type doped region is connected to a first voltage supply of a first power domain, the third p-type doped region and the first n-type doped region are connected to a second voltage supply of the first power domain. The second p-type doped region is connected to a third voltage supply of a second power domain, the fourth p-type doped region and the second n-type doped region are connected to a fourth voltage supply of the second power domain; and wherein the first and second power domains are different domains. The fifth and seventh p-type doped regions are electrically connected and the sixth and eighth p-type doped regions are electrically connected, the third and fourth gate structures are connected to a detection node and the p-type bias region is connected to a bias voltage. The ESD detection and trigger circuit generates a detection voltage to the third and fourth gate structures to activate the cross-domain ESD protection device when an ESD event occurs at any of the first, second, third and fourth voltage supply.

Furthermore, the ESD detection and trigger circuit comprises: a first diode having an anode and a cathode respectively connected to the third p-type doped region and the fourth p-type doped region; a second diode having a cathode and an anode respectively connected to the third p-type doped region and the fourth p-type doped region; a third diode and a fourth diode having anodes connected together and cathodes respectively connected to the third p-type doped region and the fourth p-type doped region; a capacitor connected between the anodes of the third and fourth diodes and the detection node; and a resistor connected between the detection node and the p-type bias region.

In addition, the bias circuit comprises: a first PMOS transistor and a second PMOS transistor, connected in series, and the serially connected first and second PMOS transistors are further connected between the first voltage supply and the third voltage supply; wherein gates of the first and second PMOS transistors respectively connected to the third voltage supply and the first voltage supply, and bulks and a connection node of the first and second PMOS transistors are connected to the p-type bias region.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows an ESD protection scheme for cross-power-domain ESD protection.

FIG. 2 shows an example of simple ESD protection for cross-power-domain.

FIG. 3 shows a cross section of a cross-domain ESD (electrostatic discharge) protection cell (device) according to a first exemplary embodiment of the invention.

FIG. 4 shows a QSCR structure embedded in the cross-domain ESD protection cell according to the invention.

FIG. 5 shows a cross section of a cross-domain ESD protection cell (device) according to a second exemplary embodiment of the invention.

FIG. 6A shows a cross-sectional view of a cross-domain ESD protection device according to a third exemplary embodiment of the invention.

FIG. 6B shows an exemplary implement of the ESD detection and trigger circuit 63 of FIG. 6A .

FIG. 6C shows an exemplary implement of the dynamic n-well bias circuit 62 of FIG. 6A .

FIG. 7A shows arrangement of diode strings to the cross-domain ESD protection cell having QSCR structure according to the invention.

FIG. 7B shows arrangement of diode strings to the conventional cross-domain ESD protection cell without QSCR structure.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 3 shows a cross section of a cross-domain ESD (electrostatic discharge) protection cell (device) according to a first exemplary embodiment of the invention. The cross-domain ESD cell 30 comprises a deep n-well DNW formed in a substrate, a first p-well PW 1 and a second p-well PW 2 formed in the deep n-well DNW, and a first n-well NW 1 formed in the deep n-well DNW and between the first p-well PW 1 and the second p-well PW 2 , where the first n-well contacting the first p-well P 1 and the second p-well P 2 .

Referring to FIG. 3 , the cross-domain ESD protection cell 30 further comprises a first p-type doped region P 1 and a second p-type doped region P 2 formed in the first n-well NW 1 ; a third P-type doped region P 3 and a fourth P-type doped region P 4 respectively formed in the first p-well PW 1 and the second p-well PW 2 ; a first n-type doped region N 1 formed in the first p-well PW 1 and between the third and first p-type doped regions P 3 and P 1 ; and a second n-type doped region N 2 formed in the second p-well PW 2 and between the second and fourth P-type wells P 2 and P 4 .

The first p-type doped region P 1 is connected to a first voltage supply VDD 1 of a first power domain, the third p-type doped region P 3 and the first n-type doped region N 1 are connected to a second voltage supply (VSS 1 ) of the first power domain. Moreover, the second p-type doped region P 2 is connected to a third voltage supply VDD 2 of a second power domain, the fourth p-type doped region P 4 and the second n-type doped region N 2 are connected to a fourth voltage supply VSS 2 of the second power domain. Here, the first and second power domains are different power domains.

In view of the structure described in FIG. 3 , the cross-domain ESD protection cell 31 comprises (or embeds) four SCR (silicon-controlled rectifier) structures (hereinafter is referred to as QSCR). The four embedded SCR structures of SCR 1 ˜SCR 4 are respectively made of P 1 -NW 1 -PW 1 -N 1 (path VDD 1 -to-VSS 1 ), P 1 -NW 1 -PW 2 -N 2 (path VDD 1 -to-VSS 2 ), P 2 -NW 1 -PW 1 -N 1 (path VDD 2 -to-VSS 1 ) and P 2 -NW 1 -PW 2 -N 2 (path VDD 2 -to-VSS 2 ), and are schematically shown in FIG. 4 . Accordingly, the cross-domain ESD protection cell 30 in FIG. 3 provides sufficient paths for cross-power-domain ESD protection with single cell layout, and therefore meet the requirements for small area utilization and compact layout.

The cross-domain ESD protection cell 30 of FIG. 3 may further comprise a fifth n-type doped region N 5 and a sixth n-type doped region N 6 respectively formed in the first p-well P 1 and the second p-well P 2 and respectively connected to the fourth voltage supply VSS 2 and the second voltage supply VSS 1 , to provide diode connection 41 ( FIG. 4 ) between the second voltage supply VSS 1 and the fourth voltage supply VSS 2 . The fifth and sixth n-type doped regions N 5 and N 6 are optional arrangement for the cross-domain ESD protection cell 30 .

FIG. 5 shows a cross section of a cross-domain ESD protection cell (device) according to a second exemplary embodiment of the invention. Compared with FIG. 3 , the cross-domain ESD protection cell 50 of FIG. 5 further comprises a third n-type doped region N 3 , a first gate structure G 1 , a fourth n-type doped region N 4 and a second gate structure G 2 . The third n-type doped region N 3 is formed in a first boundary region of the first p-well P 1 and the first n-well N 1 , and between the first n-type doped region N 1 and the first p-type doped region P 1 . The first gate structure G 1 is formed on the first p-well P 1 and between the first n-type doped region N 1 and the third n-type doped region N 3 . The fourth n-type doped region N 4 is formed in a second boundary region of the second p-well P 2 and the first n-well N 1 , and between the second n-type doped region N 2 and the second p-type doped region P 2 . The second gate structure G 2 is formed on the second p-well P 2 and between the second n-type doped region N 2 and the fourth n-type doped region N 4 . Furthermore, the first and second gate structures G 1 and G 2 are respectively connected to the second voltage supply VSS 1 and the fourth voltage supply VSS 2 . The cross-domain ESD protection cell 50 also has four embedded SCR (silicon-controlled rectifier) structures (QSCR) as described in FIG. 4 .

It should be noted that the first gate structure G 1 , the first n-type doped region N 1 and the third n-type doped region N 3 constitute a first NMOS transistor MN 1 and the second gate structure G 2 , the second n-type doped region N 2 and the third n-type doped region N 4 constitute a second NMOS transistor MN 2 . Therefore, the cross-domain ESD protection cell 50 embeds two grounded-gate NMOS (GGNMOS) transistors (MN 1 , MN 2 ) to provide the trigger mechanism, and thus can further reduce the trigger voltage of the QSCR structure to a safe level. In short, to trigger or activate the cross-domain ESD protection cell for an ESD event, the trigger voltage of the ESD protection cell 50 is lower than that of the ESD protection cell 30 .

The fifth and sixth n-type doped regions N 5 and N 6 in FIG. 5 are optional arrangement for the cross-domain ESD protection cell 50 .

FIG. 6A shows a cross-sectional view of a cross-domain ESD protection device according to a third exemplary embodiment of the invention. The cross-domain ESD protection device 60 comprise a cross-domain ESD protection cell 61 , a dynamic n-well bias circuit 62 and an ESD detection and trigger circuit 63 .

Compared to FIG. 3 , the cross-domain ESD protection cell 61 further comprises a p-type (doped) bias region NB, a fifth p-type doped region P 5 , a sixth p-type doped region P 6 , a seventh p-type doped region P 7 , an eighth p-type doped region P 8 , a third gate structure G 3 and a fourth gate structure G 4 .

The p-type bias region NB is formed in the first n-well N 1 and between the first p-type doped region P 1 and the second p-type doped region P 2 . The fifth p-type doped region P 5 and the seventh p-type doped region P 7 are respectively formed in the first p-well P 1 and the first n-well N 1 , and both are disposed between the first n-type doped region N 1 and the first p-type doped region P 1 . The sixth p-type doped region P 6 and the eighth p-type doped region P 8 are respectively formed in the second p-well P 2 and the first n-well N 1 , and both are disposed between the second n-type doped region N 2 and the second p-type doped region P 2 . The third gate structure G 3 is formed on the first n-well N 1 and between the first and seventh p-type doped regions P 1 and P 7 . The fourth gate structure G 4 is formed on the first n-well N 1 and between the second and eighth p-type doped regions P 2 and P 8 .

The fifth and seventh p-type doped regions P 5 and P 7 are electrically connected, and the sixth and eighth p-type doped regions P 6 and P 8 are electrically connected. Furthermore, the third and fourth gate structures G 3 and G 4 are connected to the ESD detection and trigger circuit 63 , and the p-type bias region NB is connected to a bias voltage VB provided by the dynamic n-well bias circuit 62 . It should be noted that the third gate structures G 3 , the first and seventh n-type doped regions P 1 and P 7 constructs a first PMOS transistor MP 1 , and the fourth gate structures G 4 , the second and eighth n-type doped regions P 2 and P 8 constructs a second PMOS transistor MP 2 .

The ESD detection and trigger circuit 63 generates an detection voltage to the third and fourth gate structures to activates the cross-domain ESD protection cell 61 when an ESD event occurs at any of the first, second, third and fourth voltage supply VDD 1 , VSS 1 , VDD 2 and VSS 2 .

FIG. 6B shows an exemplary implement of the ESD detection and trigger circuit 63 of FIG. 6A . The exemplary ESD detection and trigger circuit 63 comprises a first diode D 1 having an anode and a cathode respectively connected to the third p-type doped region P 3 and the fourth p-type doped region P 4 , a second diode D 2 having a cathode and an anode respectively connected to the third p-type doped region P 3 and the fourth p-type doped region P 4 , a third diode D 3 and a fourth diode D 4 having anodes connected together and cathodes respectively connected to the third p-type doped region P 3 and the fourth p-type doped region P 4 , a capacitor C connected between the anodes of the third and fourth diodes D 3 , D 4 and a detection node Nd, and a resistor R connected between the detection node Nd and the p-type bias region NB.

The cross-domain ESD protection cell 61 has four embedded SCR structures SCR 1 ˜SCR 4 , which are respectively made of P 1 -NW 1 -PW 1 -N 1 (path VDD 1 -to-VSS 1 ), P 1 -NW 1 -PW 2 -N 2 (path VDD 1 -to-VSS 2 ), P 2 -NW 1 -PW 1 -N 1 (path VDD 2 -to-VSS 1 ) and P 2 -NW 1 -PW 2 -N 2 (path VDD 2 -to-VSS 2 ). Therefore, the cross-domain ESD protection cell 61 comprises the QSCR structure as that schematically shown in FIG. 4 . When an ESD event occurs at any of the first, second, third and fourth voltage supply VDD 1 , VSS 1 , VDD 2 and VSS 2 , the gate structures G 3 and G 4 receive the detection voltage Vd in response to the ESD event, thereby generating trigger voltage to the fifth and/or sixth p-type doped regions P 5 , P 6 to trigger or activate the corresponding SCR 1 ˜SCR 4 for ESD protection. The ESD detection and trigger circuit 63 of FIG. 6B serves as an external trigger circuit to reduce trigger voltage of the QSCR (SCR 1 ˜SCR 4 ) structure of the cross-domain ESD protection cell 61 . For certain applications, the trigger voltage provided by the GGNMOS transistors (such as the ESD protection cell 50 described in FIG. 5 ) is not adequate, and thus the external trigger circuit as described in FIG. 6B can be applied to further reducing trigger voltage of SCR structures.

The dynamic n-well bias circuit 62 provides the bias voltage VB to the p-type bias region NB based on the first voltage supply VDD 1 and the third voltage supply VDD 2 , to reduce leakage current of the cross-domain ESD protection cell 61 when no ESD event occurs (i.e., when the integrated circuit under ESD protection normally operates). FIG. 6C shows an exemplary implement of the dynamic n-well bias circuit 62 of FIG. 6A . In FIG. 6C , the dynamic n-well bias circuit 62 comprises a third PMOS transistor MP 3 and a fourth PMOS transistor MP 4 , connected in series. The serially connected third and fourth PMOS transistors MP 3 , MP 4 are further connected between the first voltage supply VDD 1 and the third voltage supply VDD 2 . Gates of the third and fourth PMOS transistors MP 3 , MP 4 are respectively connected to the third voltage supply VDD 2 and the first voltage supply VDD 1 , and bulks and a connection node NC of the third and fourth PMOS transistors MP 3 , MP 4 are connected to the p-type bias region NB. That is, the bias voltage VB corresponding to the maximum of VDD 1 and VDD 2 , is output at the connection node NC.

The fifth and sixth n-type doped regions N 5 and N 6 in FIGS. 6A and 6B are an optional arrangement for the cross-domain ESD protection cell 61 .

To increase holding voltage of the QSCR structures in FIGS. 3, 5, 6A and 6B , two diode strings may be arranged between the third p-type doped regions (P 3 ) and the second voltage supply VSS 1 , and between the fourth p-type doped regions (P 4 ) and the fourth voltage supply VSS 2 . Such an arrangement to increase holding voltage is schematically shown in FIG. 7A , where each of the diode strings DS 1 and DS 2 may comprise one or more diodes (connected in series, in parallel or in both ways). Without the QSCR structure, the conventional way to increase holding voltage requires four diode strings D 1 ˜D 4 respectively connected to the corresponding SCRs SCR 1 ˜SCR 4 , as shown in FIG. 7B . Based on the QSCR structure of the invention, only two diode strings are required, and thus the silicon footprint and leakage current are reduced.

In view of the above descriptions, the QSCR structure of the invention can provide robust ESD protection for cross-power-domain application with low area consumption.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.