Utilization of block-mask and cut-mask for forming metal routing in an IC device

The present disclosure relates to fabrication of semiconductor devices, and more specifically, to a photolithography (lithography) process (e.g., self-aligned double patterning (SADP)) process to form metal lines in a metal layer of an IC device. The present disclosure is particularly applicable to static random access memory (SRAM) bit cells for 10 nanometer (nm) and 7 nm technology nodes and beyond.

Generally, in fabrication of an IC device, lithography processes may be utilized to print/pattern cavities, trenches, and/or recessed-areas for creating various components, elements, and circuits. A lithography process includes forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate. The radiation-sensitive material is selectively exposed to a light generated by a light source (such as a deep ultraviolet or extreme ultraviolet source) to transfer a pattern defined by a mask to the radiation-sensitive material. The exposed layer of radiation-sensitive material is developed to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.

With advancements in processes utilized to manufacture IC devices as well as industry demand for more efficient and smaller sized devices, physical dimensions of the patterns that are to be formed in the devices are reduced. In some instances, a single patterning lithography process may be incompatible for defining a compact layer, such as a metal layer in a memory cell, where multiple lithography steps (e.g., SADP) may need to be utilized for creating a single target pattern in a layer of material. For example, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, simplified/less-dense patterns. The simplified patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the simplified patterns, and the other mask is utilized to image the other simplified pattern). However, with reduced device and layout geometries, the sizes of masks (e.g., block-mask) utilized in the process are also reduced; however, this may result in undesired effects on patterns produced through the masks.

FIG. 1A schematically illustrates an example layout diagram of a metal layer 100 for a SRAM cell where a 2-by-2 array of bitcells 101 a , 101 b , 101 c , and 101 d includes connectivity to various active regions. For example, the metal layer in bitcell 101 a includes connectivity lines/segments 103 a and 103 b for a ground voltage (VSS); 105 a and 105 b for a positive voltage (VDD); 107 a for a bitline-bar- 0 (BLB 0 ); 109 a for a bitline- 0 (BL 0 ); and 111 for a wordline- 2 (WL 2 ). Geometry of a bitcell (e.g., 101 a ) includes contact-poly pitch (CPP) 113 and bitcell height 115 dimensions. In a SADP process utilized to pattern the layout of the metal layer 100 , a side-to-side spacing 117 between two connecting parallel lines/segments, e.g., 103 a and 111 or 109 a and 111 , may be determined by a thickness of a spacer (not shown) that was used in the process of creating the parallel lines/segments, whereas a tip-to-tip spacing 119 , along the bitcell height dimension 115 may be determined by a width of a block-mask (not shown) that was also used in the process.

As shown in FIG. 1B , a block-mask pitch 121 between adjacent block-masks; e.g., 123 a and 123 b , is a function of the bitcell height 115 ; therefore, if the bitcell height 115 in a smaller SRAM is further reduced, a double patterning process may be necessary for the block-mask layer. Additionally, as the size of a block-mask is reduced, its geometry may become similar to a contact shape 125 , as shown in FIG. 1C , which may be inefficient in cutting metal segments/lines. Still, even if a cut is made, the shape (e.g., sharply curved) of the tip edges 127 of the cut metal lines (e.g., 103 a and 105 a ), as shown in FIG. 1D , may adversely impact the electrical functionality/characteristics (e.g., electrical field) of the segments. Moreover, a smaller block-mask utilized in fabrication of an IC device may reduce fabrication process margins and adversely impact manufacturing yield, time, cost, etc. of an IC device.

A need therefore exists for methodology enabling formation of metal routing in an IC device utilizing SADP with a block-mask without double patterning the block mask.

An aspect of the present disclosure is a method and process for utilizing block-mask and cut-mask, with improved geometries for better lithographic printability, in metal routing in an IC device.

Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.

According to the present disclosure, some technical effects may be achieved in part by a method including forming a hard-mask layer on an upper surface of a silicon oxide layer; forming spaced parallel mandrels on an upper surface of the hard-mask layer; forming spacers on opposite sides of each mandrel and removing the mandrels, forming alternating mandrel and non-mandrel spaces; forming block-mask portions over the mandrel and non-mandrel spaces, over the upper surface of the hard-mask layer; removing exposed sections of the hard-mask layer exposing sections of an upper surface of the silicon oxide layer, and removing the block-mask portions; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask layer in areas where the block-mask portions had been; removing the hard-mask layer through the cut-mask openings, and removing the cut-mask; forming cavities in exposed regions of the silicon oxide layer; removing the spacers and any remaining hard-mask layer; and forming metal lines in the cavities.

In one aspect, the forming of the spacers includes conformally forming a spacer material layer over the mandrels and the upper surface of the hard-mask layer; and removing the spacer material layer from all horizontal surfaces.

In a further aspect, the block-mask portions are wider and longer than the cut-mask openings. In some aspects, a length of each block-mask portion equals a length of a metal line plus a width of a space between the metal line and an adjacent metal line on each side of the metal line.

In one aspect, a length of each cut-mask opening equals a length of a metal line. In some aspects, tip-to-tip edges of adjacent cavities in the silicon oxide layer include smooth concave and convex tip edges.

In another aspect, the metal lines include a metal layer of a SRAM device. In one aspect, metal lines formed in the mandrel spaces include word lines. One aspect includes forming adjacent block-mask portions in a tip-to-tip layout formation.

Another aspect of the present disclosure is a method including forming a hard-mask on an upper surface of a silicon oxide layer; forming a patterning template including a plurality of spaced parallel channels on an upper surface of the hard-mask, wherein the upper surface of the hard-mask is exposed between adjacent parallel channels; forming block-mask portions over and extending in a same direction as a parallel channel, over the upper surface of the hard-mask layer; removing exposed sections of the hard-mask layer exposing sections of an upper surface of the silicon oxide layer; removing the block-mask portions and the patterning template; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask layer in areas where the block-mask portions had been; removing the hard-mask layer through the cut-mask openings, and removing the cut-mask; forming cavities in exposed regions of the silicon oxide layer; and forming metal lines in the cavities.

In some aspects, the forming of the channels includes forming spaced parallel dielectric lines on an upper surface of the hard-mask layer; and forming spacers on opposite sides of each of the dielectric lines and removing the dielectric lines, forming alternating dielectric and non-dielectric spaces. In a further aspect, metal lines formed in dielectric spaces include word lines.

Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

FIG. 1A schematically illustrates an example layout of a metal layer in an IC device;

FIG. 1B schematically illustrates the size, shape, and positioning of a block mask layer is forming the layout of FIG. 1A ;

FIGS. 1C and 1D schematically illustrate example block-mask and tip-edge shapes of metal lines, respectively, in a metal layer of the IC device illustrated in FIG. 1A ;

FIGS. 2A through 2J schematically illustrate cross sectional views of a process flow for using a block-mask and a cut-mask to form metal lines in a metal layer of an IC device, in accordance with exemplary embodiments; and

FIGS. 3A and 3B schematically the block mask and cut mask in illustrate layout diagrams of a metal layer in a memory cell formed by the process of FIGS. 2A through 2J , and FIG. 3C illustrates tip-edge shapes of adjacent metal lines in the metal layer in the memory cell, in accordance with exemplary embodiments.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

The present disclosure addresses and solves problems of sharp metal tip shapes causing a degradation of the electric field in spaces between metal segments and a need for double exposure of a block mask layer attendant upon fabrication of compact bitcells by using compact block-masks on a metal layer. The present disclosure addresses and solves such problems, for instance, by, inter alia, utilizing a block-mask and a cut-mask to define spaces at opposite tips of metal lines in metal routing in an IC device.

FIG. 2A illustrates a stack of different material layers to form an IC device. A hard-mask layer 201 is formed on an upper surface of a silicon oxide layer 203 . The silicon oxide layer 203 may be an interlayer dielectric (ILD) formed over transistors and other circuit elements of an IC device. A material of the hard-mask layer 201 may include titanium nitride, silicon nitride, or the like. Additionally, a mandrel layer 205 may be formed on an upper surface of the hard-mask layer 201 where the mandrel layer 205 may be a layer of a dielectric material. The mandrel layer 205 may be utilized to create sacrificial patterns that can be used to form other patterns in the process flow. For instance, a mandrel mask/patterning template may be used to remove sections of the mandrel/dielectric layer 205 to form spaced parallel mandrels or dielectric lines 205 a and 205 b , as shown in FIG. 2B , on the upper surface of the hard-mask layer 201 , wherein sections of the hard-mask layer 201 in spaces 201 a , 201 b , and 201 c are exposed between the adjacent mandrels 205 a and 205 b.

FIG. 2C illustrates deposition of a layer of spacer material 207 (e.g., silicon dioxide) over the mandrels 205 a and 205 b , and on the upper surface of the exposed hard-mask layer 201 in spaces 201 a , 201 b , and 201 c . In FIG. 2D , portions of the spacer layer 207 are removed (e.g., by a dry etch process) from all horizontal surfaces such as the upper surfaces of the mandrels 205 a and 205 b as well as from the upper surface of the hard-mask layer 201 in spaces 201 a , 201 b , and 201 c . Remaining sections of the spacer material 207 can provide spacers 207 a , 207 b , 207 c , and 207 d , where spacers 207 a and 207 b are formed on opposite sides of the mandrel 205 a , and spacers 207 c and 207 d are formed on opposite sides of the mandrel 205 b . As illustrated in FIG. 2E , by removing the mandrels 205 a and 205 b , additional sections of the hard-mask layer 201 in spaces 201 d and 201 e are exposed, which create alternating mandrel ( 201 d and 201 e ) and non-mandrel ( 201 a , 201 b , and 201 c ) spaces on the upper surface of the hard-mask layer 201 .

Referring to FIG. 2F , block-mask (e.g., photoresist) portions 209 may be formed over mandrel (e.g., 201 e ) and non-mandrel (e.g., 201 c ) spaces, over the upper surface of the hard-mask layer 201 . In FIG. 2G , exposed sections of the hard-mask layer 201 in spaces 201 a , 201 b , and 201 d are removed to expose sections of the upper surface of the silicon oxide layer 203 in the spaces 201 a , 201 b , and 201 d . Also, the block-mask portions 209 are removed.

As illustrated in FIG. 2H , a cut-mask 211 is formed over the upper surface of the hard-mask layer 201 with openings shorter than the block-mask portions 209 in areas where the block-mask portions 209 had been previously formed (e.g., in space 201 c ). (Although shown as a block over space 201 c for illustrative convenience, the cut-mask covers the whole substrate with the opening over space 201 c .) FIG. 2I illustrates removing a section of the hard-mask layer 201 through the cut-mask 211 openings in space 201 c . Next, the cut mask 211 is removed. Then, exposed sections of the silicon oxide layer 203 in spaces 201 a , 201 b , 201 c , and 201 d are removed/etched to form cavities 213 a , 213 b , 213 c , and 213 d in the silicon oxide layer 203 . In FIG. 2J , the spacers 207 a , 207 b , 207 c , and 207 d as well as the remaining sections of the hard-mask layer 201 under said spacers and in the mandrel space 201 e are removed. Next, a metal/conductive material (e.g., copper) layer is deposited in the cavities to form metal/conductive lines 215 a , 215 b , 215 c , and 215 d.

FIG. 3A schematically illustrates a layout diagram of a metal layer in a memory (e.g., SRAM) cell 300 , with block-mask portions and cut-mask openings which are utilized to create metal lines/segments. For example, to create the metal line 103 a in the memory bitcell 101 a , a block-mask portion 209 a may be formed in a linear space over the hard mask layer as in FIG. 2F . Further, a cut-mask with an opening 211 a may be formed within the same region as the block-mask portion 209 a as in FIG. 2H . As illustrated, the block-mask portion 209 a is wider and longer than the cut-mask opening 211 a . The length of the cut-mask opening 211 a equals the length of the metal line segment 103 a . The length of a block-mask portion (e.g., 209 b ) may be equal to the length of a metal line 107 a plus a width of spaces 301 between the metal line 107 a and adjacent metal lines (e.g., 105 a and 303 a ) on opposite sides of the metal line 107 a . Additionally, adjacent block-mask portions (e.g., 209 a and 209 b ) are arranged in a tip-to-tip layout formation. As noted earlier, a metal line formed in a mandrel space may be a word line such as WL 2 , 111 .

FIG. 3B illustrates the memory cell 300 where an example area 305 highlights tip-to-tip edges of the metal line segments 103 a and 105 a . FIG. 3C further highlights the area 305 , which illustrates smooth convex and concave tip edges 307 and 309 , respectively, of tip-to-tip edges of adjacent cavities that were previously formed in a silicon oxide layer and used to create the metal line segments 103 a and 105 a . It is noted that the convex and concave tip edges 307 and 309 have a smoother profile compared to the tip edges 127 illustrated in FIG. 1D .

The embodiments of the present disclosure can achieve several technical effects, such as eliminating the need for double exposure of block masks in an SADP process for forming metal lines and improving the electrical field in spaces between metal line tips. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in the manufacture of any of various types of highly integrated semiconductor devices by way of a self-aligned double patterning process, particularly for the 10 and 7 nm technology nodes and beyond.

In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.