Inventor

Jongwook Kye

Inventor

Pleasanton, CA, US

Overview

2002–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 88 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices17%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

H01LSemiconductor devices16%

G06FElectric digital data processing15%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices14%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

H10BElectronic memory devices3%

G03BApparatus or arrangements for taking photographs or for projecting or viewing them1%

G01RMeasuring electric variables1%

A61LMethods or apparatus for sterilising materials or objects in general1%

PatentTitleYear

10,559,503Methods, apparatus and system for a passthrough-based architecture2020 10,366,917Methods of patterning variable width metallization lines2019 10,347,546Integrated circuit structure including power rail and tapping wire with method of forming same2019 10,204,861Structure with local contact for shorting a gate electrode to a source/drain region2019 10,147,714Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell2018 10,056,373Transistor contacts self-aligned in two dimensions2018 9,818,651'Methods, apparatus and system for a passthrough-based architecture'2017 9,798,852'Methods of design rule checking of circuit designs'2017 9,727,685'Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability'2017 9,679,809'Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines'2017 9,660,040'Transistor contacts self-aligned two dimensions'2017 9,613,177'Methods of generating circuit layouts that are to be manufactured using SADP routing techniques'2017 9,582,629'Methods of generating circuit layouts using self-alligned double patterning (SADP) techniques'2017 9,536,778'Self-aligned double patterning process for metal routing'2017 9,536,035'Wide pin for improved circuit routing'2017 9,519,745'Method and apparatus for assisted metal routing'2016 9,472,464'Methods to utilize merged spacers for use in fin generation in tapered IC devices'2016 9,466,604'Metal segments as landing pads and local interconnects in an IC device'2016 9,437,588'Middle of-line architecture for dense library layout using M0 hand-shake'2016 9,437,481'Self-aligned double patterning process for two dimensional patterns'2016 9,431,300'MOL architecture enabling ultra-regular cross couple'2016 9,400,863'Color-insensitive rules for routing structures'2016 9,330,221'Mask-aware routing and resulting device'2016 9,324,722'Utilization of block-mask and cut-mask for forming metal routing in an IC device'2016 9,292,647'Method and apparatus for modified cell architecture and the resulting device'2016 9,287,131'Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules'2016 9,268,897'Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devices'2016 9,202,751'Transistor contacts self-aligned in two dimensions'2015 9,158,879'Color-insensitive rules for routing structures'2015 9,159,724'Cross-coupling-based design using diffusion contact structures'2015 9,147,653'Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology'2015 9,122,830'Wide pin for improved circuit routing'2015 9,105,510'Double sidewall image transfer process'2015 9,041,087'Semiconductor devices having dielectric caps on contacts and related fabrication methods'2015 9,035,679'Standard cell connection for circuit routing'2015 9,006,100'Middle-of-the-line constructs using diffusion contact structures'2015 8,966,423'Integrating optimal planar and three-dimensional semiconductor design layouts'2015 8,966,412'Methods of generating circuit layouts that are to be manufactured using SADP techniques'2015 8,962,483'Interconnection designs using sidewall image transfer (SIT)'2015 8,954,913'Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules'2015 8,921,225'Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology'2014 8,918,746'Cut mask aware contact enclosure rule for grating and cut patterning solution'2014 8,916,441'FinFET device and methods of fabrication'2014 8,889,561'Double sidewall image transfer process'2014 8,881,083'Methods for improving double patterning route efficiency'2014 8,843,869'Via insertion in integrated circuit (IC) designs'2014 8,839,168'Self-aligned double patterning via enclosure design'2014 8,815,748'Method of forming semiconductor device with multiple level patterning'2014 8,809,184'Methods of forming contacts for semiconductor devices using a local interconnect processing scheme'2014 8,802,574'Methods of making jogged layout routings double patterning compliant'2014 8,791,577'Bit cell with triple patterned metal layer structures'2014 8,789,000'Variable power rail design'2014 8,765,599'Semiconductor devices having dielectric caps on contacts and related fabrication methods'2014 8,741,763'Layout designs with via routing structures'2014 8,735,050'Integrated circuits and methods for fabricating integrated circuits using double patterning processes'2014 8,719,757'Method to enhance double patterning routing efficiency'2014 8,689,154'Providing timing-closed FinFET designs from planar designs'2014 8,679,911'Cross-coupling-based design using diffusion contact structures'2014 8,677,291'Double patterning compatible colorless M1 route'2014 8,637,214'Photomask sets for fabricating semiconductor devices'2014 8,598,633'Semiconductor device having contact layer providing electrical connections'2013 8,581,348'Semiconductor device with transistor local interconnects'2013 8,367,430'Shape characterization with elliptic fourier descriptor for contact or any closed structures on the chip'2013 8,361,335'Methods for fabricating semiconductor devices'2013 8,324,106'Methods for fabricating a photolithographic mask and for fabricating a semiconductor integrated circuit using such a mask'2012 8,236,592'Method of forming semiconductor device'2012 8,153,351'Methods for performing photolithography using BARCs having graded optical properties'2012 7,855,048'Wafer assembly having a contrast enhancing top anti-reflecting coating and method of lithographic processing'2010 7,829,266'Multiple exposure technique using OPC to correct distortion'2010 7,422,829'Optical proximity correction (OPC) technique to compensate for flare'2008 7,384,725'System and method for fabricating contact holes'2008 7,315,033'Method and apparatus for reducing biological contamination in an immersion lithography system'2008 7,125,652'Immersion lithographic process using a conforming immersion medium'2006 6,977,717'Method and device for determining projection lens pupil transmission distribution and illumination intensity distribution in photolithographic imaging system'2005 6,906,777'Pellicle for a lithographic lens'2005 6,831,451'Method for adjusting a Weibull slope for variations in temperature and bias voltage'2004 6,829,040'Lithography contrast enhancement technique by varying focus with wavelength modulation'2004 6,784,992'Polarization measurement device and method'2004 6,710,853'Phase grating focus monitor using overlay technique'2004 6,696,847'Photo assisted electrical linewidth measurement method and apparatus'2004 6,646,326'Method and system for providing source/drain-gate spatial overlap engineering for low-power devices'2003 6,602,794'Silylation process for forming contacts'2003 6,556,286'Inspection system for the pupil of a lithographic tool'2003 6,555,274'Pupil filtering for a lithographic tool'2003 6,535,280'Phase-shift-moir focus monitor'2003 6,489,068'Process for observing overlay errors on lithographic masks'2002 6,459,480'Measurement method of Zernike coma aberration coefficient'2002 6,399,401'Test structures for electrical linewidth measurement and processes for their formation'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2014Patents assigned to ADVANCED MICRO DEVICES INC (20)· patent assignee history

2002–2019Based in Pleasanton, CA, US· patent location history

2010–2020Patents assigned to GLOBALFOUNDRIES INC (66)· patent assignee history

2012–2016Patents assigned to KYE JONGWOOK (21)· patent assignee history

2012–2016Patents assigned to YUAN LEI (8)· patent assignee history

2013–2015Patents assigned to RASHED MAHBUB (8)· patent assignee history

2014Based in Seou, KR· patent location history

2017–2020Based in Sunnyvale, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
GLOBALFOUNDRIES INC	66	2010–2020
KYE JONGWOOKself	21	2012–2016
ADVANCED MICRO DEVICES INC	20	2002–2014
RASHED MAHBUB	8	2013–2015
YUAN LEI	8	2012–2016

Locations

Location	Patents	Span
Pleasanton, California, US	83	2002–2019
Sunnyvale, California, US	4	2017–2020
Seou, KR	1	2014