Resistive memory system, driver circuit thereof and method for setting resistance thereof

This application claims the priority benefits of U.S. provisional application Ser. No. 62/068,764, filed on Oct. 27, 2014 and Taiwan application serial no. 103142435, filed on Dec. 5, 2014. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

The disclosure relates to a memory system, and a resistive memory system, a driver circuit thereof and a method for setting resistance thereof.

As a non-volatile memory has an advantage that data stored therein is not disappeared after power-off, it is a necessary memory element in many electronic products for maintaining a normal operation thereof. Presently, a resistive random access memory (RRAM) is one type of the non-volatile memory that is actively developed in the industry, and since it has advantages of low writing operation voltage, short write and erase time, long retention time, non-destructive reading, multi-level capability, simple structure and small cell area, etc., it has a great application potential in future personal computers and electronic equipment.

A resistive memory cell is a memory that stores data through a resistance level, for example, a low resistance state represents logic level 0, and a high resistance state represents logic level 1. Further, if a positive voltage is applied to the resistive memory cell, the resistive memory cell can be transferred from the high resistance state to the low resistance state, which is referred to as a set operation. Conversely, if a negative voltage is applied to the resistive memory cell, the resistive memory cell is transferred from the low resistance state to the high resistance state, which is referred to as a reset operation. However, since electrical conditions of the set operation and the reset operation are different (for example, set currents are different), the set operation and the reset operation generally cannot be simultaneously applied to a plurality of resistive memory cells of a same row, which influences the write speed and the array efficiency of a resistive memory system.

The disclosure provides a driver circuit, which is adapted to drive a memory array having a plurality of resistive memory cells. The driver circuit includes a row selection circuit, a first control circuit and a second control circuit. The row selection circuit is coupled to the resistive memory cells, and is used for activating the resistive memory cells. The first control circuit is coupled to the resistive memory cells, and is used for providing a set voltage and a ground voltage. The second control circuit is coupled to the resistive memory cells, and is used for providing a reset voltage and the ground voltage. When each of the resistive memory cells is set, the first control circuit provides the set voltage to the each of the resistive memory cells, and the second control circuit provides the ground voltage to the each of the resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.

The disclosure provides a resistive memory system including a memory array and the aforementioned driver circuit, wherein the memory array has a plurality of resistive memory cells, and the driver circuit is used for driving the resistive memory cells.

In an embodiment of the disclosure, the resistive memory cells are coupled to the row selection circuit through a plurality of row selection lines, the resistive memory cells are coupled to the first control circuit through a plurality of bit lines, and the resistive memory cells are coupled to the second control circuit through a plurality of source lines, wherein the row selection circuit is used for enabling one of the row selection lines.

The disclosure provides a method for setting resistance of a resistive memory system, which is adapted to the resistive memory system having a plurality of resistive memory cells, and the method for setting resistance includes following steps. It is determined whether each of the resistive memory cells is set. When each of the resistive memory cells is set, a set voltage is provided to each of the resistive memory cells through a first control circuit, and a ground voltage is provided to each of the resistive memory cells through a second control circuit to form a set current, wherein the set current is clamped by at least one of the first control circuit and the second control circuit. When each of the resistive memory cells is not set, the first control circuit is controlled not to provide the set voltage to each of the resistive memory cells.

In order to make the aforementioned and other features and advantages of the disclosure comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1A is a system schematic diagram of a resistive memory system according to an embodiment of the disclosure.

FIG. 1B is a circuit schematic diagram of a memory array of FIG. 1A according to an embodiment of the disclosure.

FIG. 2A is a circuit schematic diagram of a first control circuit and a second control circuit of FIG. 1A according to an embodiment of the disclosure.

FIG. 2B is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure.

FIG. 3A is a circuit schematic diagram of a first control circuit and a second control circuit of FIG. 1A according to another embodiment of the disclosure.

FIG. 3B is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure.

FIG. 3C is a circuit schematic diagram of the first control circuit of FIG. 3A according to an embodiment of the disclosure.

FIG. 3D is a circuit schematic diagram of the first control circuit of FIG. 3A according to an embodiment of the disclosure.

FIG. 3E is a driving waveform diagram of the first control circuit of FIG. 3D according to an embodiment of the disclosure.

FIG. 4A is a circuit schematic diagram of a first control signal and a second control signal of FIG. 1A according to an embodiment of the disclosure.

FIG. 4B is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure.

FIG. 5 is a circuit schematic diagram of a memory array of FIG. 1A according to an embodiment of the disclosure.

FIG. 6 is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure.

The disclosure is a resistive memory system, a driver circuit thereof and a method for setting resistance thereof, by which a set operation and a reset operation can be simultaneously applied to a plurality of resistive memory cells of a same row, so as to improve a write speed and an array efficiency of the resistive memory system.

The resistive memory system, the driver circuit and the method for setting resistance of the disclosure, when the resistive memory cell is set, the set current is clamped by at least one of the first control circuit and the second control circuit other than the switch transistor of the resistive memory cell. In this way, the set operation and the reset operation can be simultaneously implemented to the resistive memory cells of the same row, so as to improve the write speed and the array efficiency of the resistive memory system.

FIG. 1A is a system schematic diagram of a resistive memory system according to an embodiment of the disclosure. Referring to FIG. 1A , in the present embodiment, the resistive memory system 100 , for example, includes a memory array 110 and a driver circuit 120 , wherein the driver circuit 120 is coupled to the memory array 110 to drive the memory array 110 , and includes a row selection circuit 121 , a first control circuit 123 , a second control circuit 125 and a third control circuit 127 , for instance.

The row selection circuit 121 is coupled to the memory array 110 , and provides a row selection voltage VRS to the memory array 110 . The first control circuit 123 is coupled to the memory array 110 , and provides a set voltage Vset or a pound voltage GND to the memory array 110 . The second control circuit 125 is coupled to the memory array 110 , and provides a reset voltage Vreset or the ground voltage GND to the memory array 110 . The third control circuit 127 is coupled to the memory array 110 , and provides a bulk control voltage VBC to the memory array 110 .

FIG. 1B is a circuit schematic diagram of the memory array of FIG. 1A according to an embodiment of the disclosure. Referring to FIG. 1A and FIG. 1B , the same or like reference numerals in the drawings denote the same or like elements. In one embodiment, the memory array 110 a , for example, includes a plurality of resistive memory cells RMx, a plurality of row selection lines 111 , a plurality of bit lines 113 and a plurality of source lines 115 . Each of the resistive memory cells RMx, for example, includes a resistive memory element RMe and a switch transistor TS.

In each of the resistive memory cells RMx, one end of the resistive memory element RMe is coupled to the corresponding bit line 113 for coupling to the first control circuit 123 , and receives the set voltage Vset or the ground voltage GND provided by the first control circuit 123 , wherein the set voltage Vset is used for setting the resistive memory element RMe. A drain (corresponding to a first terminal) of the switch transistor TS is coupled to another end of the resistive memory element RMe, a gate (corresponding to a control terminal) of the switch transistor TS is coupled to the corresponding row selection line 111 for coupling to the row selection circuit 121 , and receives the row selection voltage VRS provided by the row selection circuit 121 , and a source (corresponding to a second terminal) of the switch transistor TS is coupled to the corresponding source line 115 for coupling to the second control circuit 125 , and receives the reset voltage Vreset or the ground voltage GND provided by the second control circuit 125 , wherein the reset voltage Vreset is used for resetting the resistive memory element RMe. The resistive memory cell RMx can be regarded as a resistive memory cell having three control terminals.

In one embodiment, the row selection circuit 121 is used for enabling one of the row selection lines 111 to activate the resistive memory cells RMx of a row, and performs the set operation and the reset operation to the activated resistive memory cells RMx. In other words, when the resistive memory cell RMx is set (for example, shown as a resistive memory cell RMx_ 1 ), the first control circuit 123 provides the set voltage Vset to the resistive memory cell RMx_ 1 , and the second control circuit 125 provides the ground voltage GND to the resistive memory cell RMx_ 1 to form a set current Iset, wherein the set current Iset is clamped by at least one of the first control circuit 123 and the second control circuit 125 , such that the resistive memory cell RMx_ 1 can normally implement the set operation.

When the resistive memory cell RMx is reset (for example, shown as a resistive memory cell RMx_ 2 ), the first control circuit 123 provides the ground voltage GND to the resistive memory cell RMx_ 2 , and the second control circuit 125 provides the reset voltage Vreset to the resistive memory cell RMx_ 2 , so as to perform the reset operation to the resistive memory cell RMx_ 2 .

According to the above description, through the first control circuit 123 and/or the second control circuit 125 having the a current clamping function, the resistive memory cells RMx of the same row can simultaneously implement the set operation and the reset operation, so as to improve a write speed and an array efficiency of the resistive memory system 100 .

Moreover, the third control circuit 127 can be coupled to a bulk (not shown) of the switch transistor TS of the activated resistive memory cell RMx through a trace (not shown), and controls a threshold voltage Vth of the switch transistor TS by changing a bulk voltage V SB (i.e. the bulk control voltage VBC) of the switch transistor TS. Taking an N-type transistor as an example, a relationship between the bulk voltage V SB of the switch transistor TS and the threshold voltage Vth is as follow:

V th =V T0 +γ(√{square root over ( V SB +2φ)}−√{square root over (2φ)})

Wherein, V T0 is a threshold voltage between the bulk and the source without a potential difference, γ is a substrate effect parameter, 2φ is a parameter related to a semiconductor energy level (a difference between bandgap midline and Fermi level). According to the above equation, the smaller the bulk voltage V SB is, the smaller the threshold voltage Vth is, and decrease of the threshold voltage Vth may cause decrease of an equivalent resistance of the switch transistor TS, i.e. the resistive memory cell RMx is more easy to be written, so as to increase of successfully writing the resistive memory cell RMx.

FIG. 2A is a circuit schematic diagram of the first control circuit and the second control circuit of FIG. 1A according to an embodiment of the disclosure. Referring to FIG. 1A , FIG. 1B and FIG. 2A , the same or like reference numerals in the drawings denote the same or like elements. In an embodiment, the first control circuit 123 a , for example, includes a first current clamping unit 210 and a first N-type transistor MN 1 , wherein the first current clamping unit 210 is used for providing the set voltage Vset and clamping the set current Iset.

Further, the first current clamping unit 210 includes a first P-type transistor MP 1 and a first multiplexer MX 1 , wherein the first P-type transistor MP 1 can be regarded as a clamp transistor. A source (corresponding to a first terminal) of the transistor MP 1 receives the set voltage Vset, a drain (corresponding to a second terminal) of the transistor MP 1 is coupled to the corresponding bit line 113 . An output terminal of the multiplexer MX 1 is coupled to a gate (corresponding to a control terminal) of the transistor MP 1 , input terminals of the multiplexer MX 1 receive a first current clamping voltage VBP and an operation voltage VDD, and a control terminal of the multiplexer MX 1 receives a set signal SST. A drain (corresponding to a first terminal) of the transistor MN 1 is coupled to the corresponding bit line 113 , a source (corresponding to a second terminal) of the transistor MN 1 receives the ground voltage GND, and a gate (corresponding to a control terminal) of the transistor MN 1 receives an inverted signal SST of the set signal SST.

According to the above description, the multiplexer MX 1 provides the first current clamping voltage VBP or the operation voltage VDD to the gate of the transistor MP 1 according to the set signal SST, wherein the first current clamping voltage VBP is used for clamping the set current Iset. In other words, when the resistive memory cell RMx is set, the set signal SST is enabled (for example, has a high voltage level). Now, the transistor MN 1 is turned off, and the multiplexer MX 1 provides the first current clamping voltage VBP to the gate of the transistor MP 1 according to the set signal SST, so as to provide the set voltage Vset through the transistor MP 1 and clamp the set current Iset. When the resistive memory cell RMx is not set, the set signal SST is disabled (for example, has a low voltage level). Now, the transistor MN 1 is turned on, so as to provide the ground voltage GND through the transistor MN 1 , and the multiplexer MX 1 provides the operation voltage VDD to the gate of the transistor MP 1 according to the set signal SST, so as to turn off the transistor MP 1 .

In one embodiment, the second control circuit 125 a , for example, includes a second P-type transistor MP 2 and a second N-type transistor MN 2 . A source (corresponding to a first terminal) of the transistor MP 2 receives the reset voltage Vreset, a drain (corresponding to a second terminal) of the transistor MP 2 is coupled to the corresponding source line 115 , and a gate (corresponding to a control terminal) of the transistor MP 2 receives an inverted signal RST of the reset signal RST. A drain (corresponding to a first terminal) of the transistor MN 2 is coupled to the corresponding source line 115 , a source (corresponding to a second terminal) of the transistor MN 2 receives the ground voltage GND, and a gate (corresponding to a control terminal) of the transistor MN 2 receives the inverted signal RST of the reset signal RST.

In other words, when the resistive memory cell RMx is reset, the reset signal RST is enabled (for example, has the high voltage level). Now, the transistor MP 2 is turned on, and the transistor MN 2 is turned off, so as to provide the reset voltage Vreset through the transistor MP 2 . When the resistive memory cell RMx is not reset, the reset signal RST is disabled (for example, has the low voltage level). Now, the transistor MN 2 is turned on, so as to provide the ground voltage GND through the transistor MN 2 , and the transistor MP 2 is turned off.

FIG. 2B is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure. Referring to FIG. 2A and FIG. 2B , in an embodiment, the method for setting resistance of the resistive memory system includes following steps. First, all of the row selection lines, the sources lines and the bit lines are connected to the ground (step S 210 ). Then, the set voltage is applied to the selected bit line through the first current clamping unit (step S 220 ). Finally, a write level is applied to the selected row selection line and the source line is connected to the ground (step S 230 ).

FIG. 3A is a circuit schematic diagram of the first control circuit and the second control circuit of FIG. 1A according to another embodiment of the disclosure. Referring to FIG. 1A , FIG. 1B , FIG. 2A and FIG. 3A , the same or like reference numerals in the drawings denote the same or like elements, and the second control circuit 125 a may refer to FIG. 2A , and detail thereof is not repeated. In one embodiment, the first control circuit 123 b , for example, includes a first current clamping unit 310 and a fourth N-type transistor MN 4 .

Further, the first current clamping unit 310 , for example, includes a third P-type transistor MP 3 , a voltage comparison unit 311 and a current control circuit 313 , wherein the third P-type transistor MP 3 can be regarded as a clamp transistor. A source (corresponding to a first terminal) of the transistor MP 3 receives the set voltage Vset, a drain (corresponding to a second terminal) of the transistor MP 3 is coupled to the corresponding bit line 113 . The current control circuit 313 is coupled to a gate (corresponding to a control terminal) of the third P-type transistor MP 3 , and receives the first current clamping voltage VBP, the ground voltage GND, the operation voltage VDD and a comparison result voltage VRC 1 , and when each of the resistive memory cells RMx is not set (i.e. the set operation is not performed), the current control circuit 313 provides the operation voltage VDD to the gate of the third P-type transistor MP 3 to turn off the third P-type transistor MP 3 . When each of the resistive memory cells RMx is set (i.e. the set operation is performed), the current control circuit 313 provides the first current clamping voltage VBP or the ground voltage GND to the gate of the third P-type transistor MP 3 according to the comparison result voltage VRC 1 , wherein the first current clamping voltage VBP is used for clamping the set current Iset.

The voltage comparison unit 311 is coupled to the corresponding bit line 113 and the current control circuit 313 , receives a reference voltage Vrf and the set signal SST, is activated in response to the set signal SST, and compares a voltage level of the corresponding bit line 113 and the reference voltage Vrf to determine whether the voltage level of the corresponding bit line 113 reaches a write level. The voltage comparison unit 311 provides the comparison result voltage VRC 1 to the current control circuit 313 according to a comparison result. A drain (corresponding to a first terminal) of the transistor MN 4 is coupled to the corresponding bit line 113 , a source (corresponding to a second terminal) of the transistor MN 4 receives the ground voltage GND, and a gate (corresponding to a control terminal) of the transistor MN 4 receives the inverted signal SST of the set signal SST.

According to the above description, when the resistive memory cell RMx is set, the set signal SST is enabled (for example, has the high voltage level). Now, the transistor MN 4 is turned off, and the voltage comparison unit 311 is activated. Then, when the voltage level of the corresponding bit line 113 does not reach the write level, i.e. the reference voltage Vrf is greater than the voltage level of the corresponding bit line 113 , the voltage comparison unit 311 provides the comparison result voltage VRC 1 with the low voltage level. Now, the current control circuit 313 provides the ground voltage GND to the gate of the transistor MP 3 to turn on the transistor MP 3 according to the comparison result voltage VRC 1 with the low voltage level, so as to accelerate an increasing speed of the voltage level of the corresponding bit line 113 .

When the voltage level of the corresponding bit line 113 reaches or exceeds the write level, i.e. the reference voltage Vrf is smaller than or equal to the voltage level of the corresponding bit line 113 , the voltage comparison unit 311 provides the comparison result voltage VRC 1 with the high voltage level. Now, the current control circuit 313 provides the first current clamping voltage VBP to the gate of the transistor MP 3 according to the comparison result voltage VRC 1 with the high voltage level, so as to provide the set voltage Vset through the transistor MP 3 and clamp the set current Iset.

When the resistive memory cell RMx is not set, the set signal SST is disabled (for example, has the low voltage level). Now, the voltage comparison unit 311 is turned off, and the transistor MN 4 is turned on, so as to provide the ground voltage GND through the transistor MN 4 , and the current control circuit 313 provides the operation voltage VDD to the gate of the transistor MP 3 to turn off the transistor MP 3 . Therefore, the voltage level of the corresponding bit line 113 is equal to the ground voltage GND.

FIG. 3B is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure. Referring to FIG. 3A and FIG. 3B , in an embodiment, the method for setting resistance of the resistive memory system includes following steps. First, the bit line is connected to the ground (step S 310 ), a gate of a clamp transistor is connected to the ground through a control circuit, so as to accelerate a charging speed of the bit line (step S 320 ). Then, the voltage comparison unit is used to detect whether a voltage level of the bit line is increased to reach a write level (step S 330 ), and when the voltage level of the bit line is increased to reach the write level, the control circuit provides a first current clamping voltage to the gate of the clamp transistor (step S 340 ).

FIG. 3C is a circuit schematic diagram of the first control circuit of FIG. 3A according to an embodiment of the disclosure. Referring to FIG. 3A and FIG. 3C , the same or like reference numerals in the drawings denote the same or like elements, and the second control circuit may refer to the second control circuit 125 a of FIG. 2A , and detail thereof is not repeated. In one embodiment, the first control circuit 123 c is substantially the same to the first control circuit 123 b , and a difference therebetween lies in the first current clamping unit 310 a . In the first current clamping unit 310 a , the voltage comparison unit 311 a , for example, includes a comparator CR 1 , and the current control circuit 313 a , for example, includes a fourth P-type transistor MP 4 , a third N-type transistor MN 3 and a second multiplexer MX 2 .

An output terminal of the multiplexer MX 2 is coupled to a gate (corresponding to a control terminal) of the transistor MP 3 , input terminals of the multiplexer MX 2 receive the first current clamping voltage VBP and the inverted signal SST of the set signal SST, and a control terminal of the multiplexer MX 2 receives a control signal SC 1 . A source (corresponding to a first terminal) of the transistor MP 4 receives the operation voltage VDD, a drain (corresponding to a second terminal) of the transistor MP 4 is used for providing the control signal SC 1 , and a gate of the transistor MP 4 is coupled to an output terminal of the comparator CR 1 . A drain (corresponding to a first terminal) of the transistor MN 3 is coupled to the drain of the transistor MP 4 , a source (corresponding to a second terminal) of the transistor MN 3 receives the ground voltage GND, and a gate (corresponding to a control terminal) of the transistor MN 3 receives the inverted signal SST of the set signal SST.

A negative input terminal of the comparator CR 1 is coupled to the corresponding bit line 113 , a positive input terminal of the comparator CR 1 receives the reference voltage Vrf, and an enable terminal of the comparator CR 1 receives the set signal SST, and the comparator CR 1 is enabled in response to the set signal SST. When the comparator CR 1 is enabled, the comparator CR 1 compares the voltage level of the corresponding bit line 113 and the reference voltage Vrf to determine whether the voltage level of the corresponding bit line 113 reaches the write level, and accordingly provides the comparison result voltage VRC 1 to the gate of the transistor MP 4 .

According to the above description, when the resistive memory cell RMx is not set, the multiplexer MX 2 provides the inverted set signal SST with a level of the operation voltage VDD to the gate of the transistor MP 3 according to the control signal SC 1 . When the resistive memory cell is set, the multiplexer MX 2 provides the first current clamping voltage VBP or the inverted set signal SST with a level of the ground voltage GND to the gate of the transistor MP 3 according to the control signal SC 1 . In other words, when the resistive memory cell RMx is set, the set signal SST is enabled (for example, has the high voltage level), and now the transistors MN 3 and MN 4 are turned off. Moreover, when the voltage level of the corresponding bit line 113 does not reach the write level, i.e. the reference voltage Vrf is greater than the voltage level of the corresponding bit line 113 , the comparator CR 1 provides the comparison result voltage VRC 1 with the high voltage level to turn off the transistor MP 4 . Now, the multiplexer MX 2 provides the inverted set signal SST with a level of the ground voltage GND to the gate of the transistor MP 3 according to the control signal SC 1 with a level of the ground voltage GND, so as to turn on the transistor MP 3 to accelerate the increasing speed of the voltage level of the corresponding bit line 113 .

When the voltage level of the corresponding bit line 113 reaches or exceeds the write level, i.e. the reference voltage Vrf is smaller than or equal to the voltage level of the corresponding bit line 113 , the comparator CR 1 provides the comparison result voltage VRC 1 with the low voltage level to turn on the transistor MP 4 , so as to increase the control signal SC 1 to the operation voltage VDD. The multiplexer MX 2 provides the first current clamping voltage VBP to the gate of the transistor MP 3 according to the control signal SC 1 with a level of the operation voltage VDD (which is equivalent to the high voltage level), so as to provide the set voltage Vset through the transistor MP 3 and clamp the set current Iset.

When the resistive memory cell RMx is not set, the set signal SST is disabled (for example, has the low voltage level). Now, the comparator CR 1 is turned off, and the transistors MN 3 and MN 4 are turned on, so as to provide the ground voltage GND through the transistor MN 4 , and the multiplexer MX 2 provides the inverted set signal SST with a level of the operation voltage VDD to the gate of the transistor MP 3 according to the control signal SC 1 , so as to turn off the transistor MP 3 . Therefore, the voltage level of the corresponding bit line 113 is decreased to the ground voltage GND.

According to the above description, when the voltage level of the corresponding bit line 113 does not reach the write level, the transistor MP 3 is turned on to provide a larger current to the corresponding bit line 113 , so as to accelerate increasing of the voltage level of the corresponding bit line 113 . When the voltage level of the corresponding bit line 113 reaches or exceeds the write level, the set current Iset is clamped through the transistor MP 3 . In this way, a time for setting the resistive memory cell RMx may be shortened.

FIG. 3D is a circuit schematic diagram of the first control circuit of FIG. 3A according to an embodiment of the disclosure. Referring to FIG. 3A , FIG. 3C and FIG. 3D , the same or like reference numerals in the drawings denote the same or like elements, and the second control circuit may refer to the second control circuit 125 a of FIG. 2A , and detail thereof is not repeated. In an embodiment, a circuit structure of the first control circuit 123 d is substantially the same to that of the first control circuit 123 c , and a difference therebetween lies in the first current clamping unit 310 b , and the first current clamping unit 310 b further includes an inverter INT 1 . In the first current clamping unit 310 b , the voltage comparison unit 311 b , for example, includes a comparator CR 2 , and the current control circuit 313 b , for example, includes a fourth P-type transistor MP 4 , a third N-type transistor MN 3 , an N-type transistor MNa, transmission gates TG 1 , TG 2 , inverters INT 2 , INT 3 and an NAND gate NAD 1 . Here, the inverter INT 1 is, for example, configured in the first current clamping unit 310 b , though in other embodiments, the inverter INT 1 can be configured outside the first current clamping unit 310 b , which is not limited by the disclosure.

A source (corresponding to a first terminal) of the transistor MP 3 receives the set voltage Vset, a drain (corresponding to the second terminal) of the transistor MP 3 is coupled to the corresponding bit line 113 . An input terminal of the transmission gate TG 1 receives the first current clamping voltage VBP, a positive control terminal of the transmission gate TG 1 receives a control signal SC 2 , a negative control terminal of the transmission gate TG 1 receives an inverted signal SC 2 of the control signal SC 2 , and an output terminal of the transmission gate TG 1 is coupled to the gate of the transistor MP 3 . An input terminal of the transmission gate TG 2 receives the inverted signal SST of the set signal SST, a positive control terminal of the transmission gate TG 2 receives the inverted signal SC 2 of the control signal SC 2 , a negative control terminal of the transmission gate TG 2 receives the control signal SC 2 , and an output terminal of the transmission gate TG 2 is coupled to the gate of the transistor MP 3 , wherein the transmission gates TG 1 and TG 2 have a function similar to that of the multiplexer MX 2 .

A source of the transistor MP 4 receives the operation voltage VDD, and a gate of the transistor MP 4 receives the set signal SST. A drain of the transistor MN 3 is coupled to a drain of the transistor MP 4 , a source of the transistor MN 3 receives the ground voltage GND, and a gate of the transistor MN 3 is coupled to an output terminal of the comparator CR 2 . A positive input terminal of the comparator CR 2 is coupled to the corresponding bit line 113 , a negative input terminal of the comparator CR 2 receives the reference voltage Vrf, an enable terminal of the comparator CR 2 receives the set signal SST, and the output terminal of the comparator CR 2 provides a comparison result voltage VRC 2 . A drain of the transistor MNa is coupled to the gate of the transistor MN 3 , a source of the transistor MNa receives the ground voltage GND, and a gate of the transistor MN 3 receives the inverted signal SST of the set signal SST.

An input terminal of the inverter INT 1 receives the set signal SST, and an output terminal of the inverter INT 1 provides the inverted signal SST of the set signal SST. An input terminal of the inverter INT 2 is coupled to the drain of the MP 4 . Input terminals of the NAND gate NAD 1 are coupled to an output terminal of the inverter INT 2 and received the set signal SST, and an output terminal of the NAND gate NAD 1 provides the inverted signal SC 2 of the control signal SC 2 . An input terminal of the inverter INT 3 receives the inverted signal SC 2 of the control signal SC 2 , and an output terminal of the inverter INT 3 provides the control signal SC 2 .

A drain of the transistor MN 4 is coupled to the corresponding bit line 113 , a source of the transistor MN 4 receives the ground voltage GND, and a gate of the transistor MN 4 receives the inverted signal SST of the set signal SST.

FIG. 3E is a driving waveform diagram of the first control circuit of FIG. 3D according to an embodiment of the disclosure. Referring to FIG. 3D and FIG. 3E , before a time point T 1 , it is assumed that the resistive memory cell RMx is not set, such that the set signal SST is disabled (for example, has a low voltage level L). Now, the comparator CR 2 is turned off (i.e. output the low voltage level L), and the transistor MNa, the transistor MP 4 and the transistor MN 4 are turned on, so as to provide the ground voltage (i.e. the low voltage level L) to the corresponding bit line 113 through the transistor MN 1 . Moreover, the control signal SC 2 has a high voltage level H, such that the inverted signal SST of the high voltage level H is provided to the gate of the transistor MP 3 (a gate voltage VGP 3 ) through the transmission gate TG 2 , so as to turn off the transistor MP 3 .

After the time point T 1 , it is assumed that the resistive memory cell RMx is set, so that the set signal SST is enabled (for example, has the high voltage level H). Now, the comparator CR 2 is activated to compare the voltage level of the corresponding bit line 113 and the reference voltage Vrf, and provides the comparison result voltage VRC 2 according to a comparison result. Moreover, the transistor MNa, the transistor MP 4 and the transistor MN 4 are turned off.

During a period between the time point T 1 and a time point T 2 , the voltage level V 113 of the corresponding bit line 113 does not reach a write level VWL, i.e. the reference voltage Vrf is greater than the voltage level V 113 of the corresponding bit line 113 , so that the comparator CR 2 provides the comparison result voltage VRC 2 with the low voltage level L to turn off the transistor MN 3 , such that the control signal SC 2 still has the high voltage level H. Now, the inverted signal SST with the low voltage level L is transmitted to the gate of the transistor MP 3 (i.e. the gate voltage VGP 3 ) to turn on the transistor MP 3 .

After the time point T 2 , the voltage level V 113 of the corresponding bit line 113 reaches or exceeds the write level VWL, i.e. the reference voltage Vrf is smaller than the voltage level of the corresponding bit line 113 , such that the comparator CR 2 provides the comparison result voltage VRC 2 with the high voltage level H to turn on the transistor MN 3 , and the control signal SC 2 is switched to the low voltage level L. Now, the first current clamping voltage VBP is provided to the gate of the transistor MP 3 (i.e. the gate voltage VGP 3 ) through the transmission gate TG 1 , so as to clamp the set current Iset. At a time point T 3 , the resistive memory cell RMx that is set successfully is transferred to a low resistance state, such that the set current Iset is greatly increased.

FIG. 4A is a circuit schematic diagram of the first control signal and the second control signal of FIG. 1A according to an embodiment of the disclosure. Referring to FIG. 1A , FIG. 1B and FIG. 4A , the same or like reference numerals in the drawings denote the same or like elements. In an embodiment, the second control circuit 125 b , for example, includes a second current clamping unit 410 and a fifth P-type transistor MP 5 , wherein the second current clamping unit 410 is used for providing the ground voltage GND and clamping the set current Iset.

Further, the second current clamping unit 410 , for example, includes a fifth N-type transistor MN 5 and a third multiplexer MX 3 . A drain (corresponding to a first terminal) of the transistor MN 5 is coupled to the corresponding source line 115 , and a source (corresponding to a second terminal) of the transistor MN 5 receives the ground voltage GND. An output terminal of the multiplexer MX 3 is coupled to a gate (corresponding to a control terminal) of the transistor MN 5 , input terminals of the multiplexer MX 3 receives a second current clamping voltage VBN and the ground voltage GND, and a control terminal of the multiplexer MX 3 receives the set signal SST. A source (corresponding to a first terminal) of the transistor MP 5 receives the reset voltage Vreset, a drain (corresponding to a second terminal) of the transistor MP 5 is coupled to the corresponding source line 115 , and a gate (corresponding to a control terminal) of the transistor MP 5 receives the inverted signal RST of the reset signal RST.

According to the above description, the multiplexer MX 3 provides the second current clamping voltage VBN or the ground voltage GND to the gate of the transistor MN 5 according to the set signal SST, wherein the second current clamping voltage VBN is used for clamping the set current Iset. In other words, when the resistive memory cell RMx is set, the set signal SST is enabled (for example, has the high voltage level), and the reset signal RST is disabled. Now, the transistor MP 5 is turned off, and the multiplexer MX 3 provides the second current clamping voltage VBN to the gate of the transistor MN 5 according to the set signal SST, so as to provide the ground voltage GND through the transistor MN 5 and clamp the set current Iset. When the resistive memory cell RMx is not set, the set signal SST is disabled (for example, has the low voltage level), and it is assumed that the reset signal RST is still disabled. Now, the transistor MP 5 is still turned off, and the multiplexer MX 5 provides the ground voltage GND to the gate of the transistor MN 5 according to the set signal SST, so as to turn off the transistor MN 5 .

In one embodiment, the first control circuit 123 e , for example, includes a sixth P-type transistor MP 6 and a sixth N-type transistor MN 6 . A source (corresponding to a first terminal) of the transistor MP 6 receives the set voltage Vset, a drain (corresponding to a second terminal) of the transistor MP 6 is coupled to the corresponding bit line 113 , and a gate (corresponding to a control terminal) of the transistor MP 6 receives the inverted signal SST of the set signal SST. A drain (corresponding to a first terminal) of the transistor MN 6 is coupled to the corresponding bit line 113 , a source (corresponding to a second terminal) of the transistor MN 6 receives the ground voltage GND, and a gate (corresponding to a control terminal) of the transistor MN 6 receives the inverted signal SST of the set signal SST.

In other words, when the resistive memory cell RMx is set, the set signal SST is enabled (for example, has the high voltage level). Now, the transistor MP 6 is turned on and the transistor MN 6 is turned off, so as to provide the set voltage Vset through the transistor MP 6 . When the resistive memory cell RMx is not set, the set signal SST is disabled (for example, has the low voltage level). Now, the transistor MN 6 is turned on, so as to provide the ground voltage GND through the transistor MN 6 , and the transistor MP 6 is turned off.

FIG. 4B is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure. Referring to FIG. 4A and FIG. 4B , in an embodiment, the method for setting resistance of the resistive memory system includes following steps. First, all of the row selection lines, the sources lines and the bit lines are connected to the ground (step S 410 ). Then, the selected source line is connected to the ground through the second current clamping unit (step S 420 ). Finally, a write level is applied to the selected row selection line and the set voltage is applied to the bit line (step S 430 ).

FIG. 5 is a circuit schematic diagram of the memory array of FIG. 1A according to an embodiment of the disclosure. Referring to FIG. 1A , FIG. 1B and FIG. 5 , wherein the same or like reference numerals in the drawings denote the same or like elements, and the memory array 110 b is substantially the same to the memory array 110 a , and a difference therebetween is that in the memory array 110 b , the resistive memory cells RMx, the row selection lines 111 , the bit lines 113 and the source lines 115 are grouped into a plurality of groups (for example, groups GP 1 , GP 2 ). Moreover, the source lines 115 of each of the groups (for example, the groups GP 1 , GP 2 ) are coupled to each other first and are then coupled to the second control circuit 125 .

In the aforementioned embodiment, the set current Iset is clamped by one of the first control circuit 123 and the second control circuit 125 , though in other embodiments, the first control circuit 123 and the second control circuit 125 are simultaneously used to clamp the current Iset, i.e. the second control circuit 125 b can be paired to one of the first control circuit 123 a - 123 d to drive the memory array 110 .

FIG. 6 is a flowchart illustrating a method for setting resistance of a resistive memory system according to an embodiment of the disclosure. Referring to FIG. 6 , in an embodiment, the method for setting resistance of the resistive memory system includes following steps. In step S 610 , it is determined whether each of the resistive cells is set, and when each of the resistive memory cells is set, i.e. when a determination result of the step S 610 is “yes”, the set voltage is provided to each of the resistive memory cells through the first control circuit, and the ground voltage is provided to each of the resistive memory cells through the second control circuit to form a set current, wherein the set current is clamped by at least one of the first control circuit and the second control circuit (step S 620 ). When each of the memory cells is not set, i.e. when the determination result of the step S 610 is “no”, the first control circuit is controlled not to provide the set voltage to each of the resistive memory cells (step S 630 ). A sequence of the steps S 610 , S 620 and S 630 is an example, and the disclosure is not limited thereto, and details of the steps S 610 , S 620 and S 630 may refer to the descriptions of the embodiments of FIG. 1A , FIG. 1B , FIG. 2A , FIG. 2B , FIG. 3A to FIG. 3E , FIG. 4A , FIG. 4B and FIG. 5 , which are not repeated.

Further, when the first control circuit includes a first current clamping unit, the step S 620 may include providing the set voltage to each of the resistive memory cells through the first current clamping unit of the first control circuit, so as to clamp the set current. Moreover when the first current clamping unit is coupled to each of the resistive memory cells through a bit line, the method for setting resistance further includes following steps. A voltage level of the bit line is detected. When the voltage level of the bit line is smaller than a write level, the first current clamping unit is controlled not to clamp the set current. When the voltage level of the bit line is greater than or equal to the write level, the first current clamping unit is controlled to clamp the set current.

When the second control circuit includes a second current clamping unit, the step S 620 may include providing the ground voltage to each of the resistive memory cells through the second current clamping unit of the second control circuit, so as to clamp the set current.

In summary, in the resistive memory system, the driver circuit and the method for setting resistance of the disclosure, when the resistive memory cell is set, the set current is clamped by at least one of the first control circuit and the second control circuit other than the switch transistor of the resistive memory cell. In this way, the set operation and the reset operation can be simultaneously implemented to the resistive memory cells of the same row, so as to improve the write speed and the array efficiency of the resistive memory system. Moreover, the voltage of the bulk of the switch transistor can be changed through the third control circuit, so as to control the threshold voltage of the switch transistor and accordingly improve a chance of successfully writing the resistive memory. Moreover, when the voltage level of the corresponding bit line does not reach the write level, a larger current is provided to the corresponding bit line through the first control circuit, and when the voltage level of the corresponding bit line reaches or exceeds the write level, the set current is clamped through the first control circuit. In this way, the time for setting the resistive memory cells may be shortened.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.