Sense amplifier

1. Field of Invention

The present invention generally relates to a sense amplifier, and more particularly to a small-offset voltage-mode sense amplifier.

2. Description of Prior Art

In recently years, a memory with lower operation power, high operation speed, and high storage density is needed for using in mobile devices, medical electrical equipment, and portable storage devices, etc.

By using a power source with low voltage level, a larger read margin is necessary for against process, voltage and temperature (PVT) variation. In conventional art, a data read scheme of a sense amplifier is suffered from slow margin developing. Such as that, a longer read access time is needed for the sense amplifier.

Referring to FIG. 1A and FIG. 1B , FIGS. 1A and 1B illustrate waveform diagrams of bit line voltages for a memory cell during a data reading operation with standard power voltage and a low power voltage, respectively. Voltages on bit lines BL 1 and BL 2 are compared for sensing out data stored in a memory cell, wherein the bit line BL 1 is corresponding to stored data “1”, and the bit line BL 2 is corresponding to stored data “0”. In FIG. 1A , at a time point T 1 , a voltage difference dV 1 is large enough for sensing out the stored in the memory cell, and the data reading operation can be completed at the time point T 1 . On the other hand, in FIG. 1B , a voltage difference dV 2 is large enough for sensing out the stored in the memory cell till a time point T 2 , and the data reading operation can be completed with a longer time period when the memory is operated in a lower power voltage.

The present disclosure provides a sense amplifier for improving performance of reading operation on a memory cell.

The present disclosure provides a sense amplifier. The sense amplifier includes a first inverting circuit, a second inverting circuit, a pre-charge circuit, a voltage adjusting circuit, and a discharge circuit. The first inverting circuit has a first input end and a first output end, and the second inverting circuit has a second input end and a second output end, wherein the first input end is coupled to the second output end, and the second input end is coupled to the first output end. The pre-charge circuit is coupled to the first and second output ends, wherein the pre-charge circuit pulls up the voltage levels on the first and second ends according to a power voltage during a pre-charge time period. The voltage adjusting circuit is coupled to the first and second output ends, respectively receives a bit line voltage and a reference voltage during the pre-charge time period by a first receiving end and a second receiving end, and adjusts voltages on the first and second output ends respectively according to the voltage on the second and first receiving ends. The discharge circuit is coupled to the control ends of the first and second transistors, wherein the discharge circuit pulls down voltage levels on the first and second receiving ends of the voltage adjusting circuit during a discharge time period. The first and second inverting circuits are enabled for a sensing operation after the discharge time period, and the pre-charge time period is before the discharge time period.

According to an embodiment of present disclosure, the sense amplifier further includes an initial circuit. The initial circuit is coupled to the first and second output ends, and the initial circuit pulls down voltage levels on the first and second output ends to a reference ground during an initial time period, wherein the initial time period is before the pre-charge time period.

According to an embodiment of present disclosure, the voltage adjusting circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor has a control end coupled to the first receiving end, and a first end coupled to the first output end. The second transistor has a control end coupled to the second receiving end, and a first end coupled to the second output end.

The first capacitor is coupled between a second end of the first transistor and the second receiving end. The second capacitor is coupled between a second end of the second transistor and the first receiving end.

According to an embodiment of present disclosure, the voltage adjusting circuit further includes a first switch and a second switch. The first switch has a first end receiving the reference voltage, and a second end coupled to the first receiving end, and the first switch is controlled by a read enable signal. The second switch has a first end receiving the bit line voltage, and a second end coupled to the second receiving end, and the second switch is controlled by the read enable signal.

According to an embodiment of present disclosure, the first and second transistors are N-type transistors.

According to an embodiment of present disclosure, the pre-charge circuit includes a first transistor and a second transistor. The first transistor has a first end receiving a power voltage, a second end coupled to a first output end, and a control end for receiving a pre-charge enable signal. The second transistor has a first end receiving the power voltage, a second end coupled to a second output end, and a control end for receiving the pre-charge enable signal.

According to an embodiment of present disclosure, the discharge circuit includes a first transistor, and a second transistor. The first transistor has a first end coupled to the first receiving end, a second end coupled to a reference ground, and a control end for receiving a discharge enable signal. The second transistor has a first end coupled to the second receiving end, a second end coupled to the reference ground, and a control end for receiving the discharge enable signal.

According to an embodiment of present disclosure, the first inverting circuit includes a first transistor and a second transistor. The second inverting circuit includes a third transistor and a fourth transistor. The first transistor has a first end receiving a power voltage, a second end coupled to the first output end, and a control end coupled to the first input end. The second transistor has a first end coupled to the first output end, a second end coupled to a reference ground, and a control end coupled to the first input end. The third transistor has a first end receiving the power voltage, a second end coupled to the second output end, and a control end coupled to the second input end. The fourth transistor has a first end coupled to the second output end, a second end coupled to the reference ground, and a control end coupled to the second input end.

According to an embodiment of present disclosure, the sense amplifier further includes a first switch, and a second switch. The first switch has a first end receiving the power voltage, and a second end coupled to the first ends of the first and third transistors. The second switch has a first end coupled to the second ends of the second and fourth transistors, and a second end coupled to the reference ground. Wherein the first and second switches are merely turned on during the sense time period.

According to an embodiment of present disclosure, wherein the first and second switches are two transistor switches.

Accordingly, the sense amplifier provides the discharge circuit for pulling down voltage levels on the first and second receiving ends of the voltage adjusting circuit during a discharge time period, and a voltage difference between the bit line voltage and the reference voltage can be enlarged during the discharge time period. Such as that, the data stored in the memory cell can be sensed out more quickly. Even in the memory with low power voltage, the performance of the memory can be promoted by using the sensing amplifier of present disclosure.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIGS. 1A and 1B illustrate waveform diagrams of bit line voltages for a memory cell during a data reading operation with standard power voltage and a low power voltage, respectively.

FIG. 2 is a circuit diagram of a sense amplifier according to an embodiment of the present disclosure.

FIG. 3 illustrates a waveform plot of the sense amplifier 200 .

Reference will now be made in detail to the present preferred embodiment of the invention, examples of which are illustrated in the accompanying drawings.

Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

Referring to FIG. 2 , FIG. 2 is a circuit diagram of a sense amplifier according to an embodiment of the present disclosure. The sense amplifier 200 includes a first inverting circuit 211 , a second inverting circuit 212 , pre-charge circuit 220 , a voltage adjusting circuit 230 , a discharge circuit 250 , an initial circuit 240 and switches SW 1 and SW 2 . The first inverting circuit 211 has a first input end IE 1 and a first output end OE 1 , and the second inverting circuit 212 has a second input end 1 E 2 and a second output end OE 2 . Wherein, the first input end IE 1 is coupled to the second output end OE 2 , and the first output end OE 1 is coupled to the second input end 1 E 2 .

The first inverting circuit 211 includes transistors M 11 and M 12 . A first end of the transistor M 11 receives a power voltage VDD through the switch SW 1 , a second end of the transistor M 11 is coupled to the first output end OE 1 of the first inverting circuit 211 , and a control end of the transistor M 11 is coupled to the first input end IE 1 of the first inverting circuit 211 . A first end of the transistor M 12 is coupled to the first output end OE 1 of the first inverting circuit 211 , a second end of the transistor M 12 is coupled to a reference ground GND through the switch SW 2 , and a control end of the transistor M 12 is coupled to the first input end IE 1 of the first inverting circuit 211 . The second inverting circuit 212 includes transistors M 13 and M 14 . A first end of the transistor M 13 receives a power voltage VDD through the switch SW 1 , a second end of the transistor M 13 is coupled to the second output end OE 2 of the second inverting circuit 212 , and a control end of the transistor M 13 is coupled to the second input end 1 E 2 of the second inverting circuit 212 . A first end of the transistor M 14 is coupled to the second output end OE 2 of the second inverting circuit 212 , a second end of the transistor M 14 is coupled to a reference ground GND through the switch SW 2 , and a control end of the transistor M 14 is coupled to the second input end 1 E 2 of the second inverting circuit 212 .

The switches SW 1 and SW 2 are controlled by a sense enable signal SAEN and an inverted sense enable signal SAENB, and are used to enable or disable the first and second inverting circuits 211 and 212 . In detail, when the switches SW 1 and SW 2 are turned on respectively according to the inverted sense enable signal SAENB and the sense enable signal SAEN, the first and second inverting circuits 211 and 212 are enable for a data sensing operation. On the contrary, when the switches SW 1 and SW 2 are cut off respectively according to the inverted sense enable signal SAENB and the sense enable signal SAEN, the first and second inverting circuits 211 and 212 are disabled and the data sensing operation is stopped.

In this embodiment, the switches SW 1 and SW 2 are respectively formed by transistors MSW 1 and MSW 2 . A first and second ends of the transistor MSW 1 are respectively coupled to the power voltage VDD and the first ends of the transistors M 11 and M 13 , and a control end of the transistor MSW 1 receives the inverted sense enable signal SAENB. A first and second ends of the transistor MSW 2 are respectively coupled to the second ends of the transistors M 12 and M 14 and the reference ground GND, and a control end of the transistor MSW 2 receives the sense enable signal SAEN. Wherein, the sense enable signal SAEN is inverted to the inverted sense enable signal SAENB.

The pre-charge circuit 220 includes a first pre-charge circuit 220 - 1 and a second pre-charge circuit 220 - 2 . The first pre-charge circuit 220 - 1 and the second pre-charge circuit 220 - 2 respectively coupled to the first and second output ends OE 1 and OE 2 , and the first pre-charge circuit 220 - 1 and the second pre-charge circuit 220 - 2 respectively pull up the voltage levels on the first and second ends OE 1 and OE 2 to the power voltage VDD during a pre-charge time period. The first pre-charge circuit 220 - 1 and the second pre-charge circuit 220 - 2 respectively include transistors M 21 and M 22 . A first end of the transistor M 21 receive the power voltage VDD, the second end of the transistor M 21 is coupled to the first output end OE 1 , and a control end of the transistor M 21 receives the pre-charge enable signal PRE. A first end of the transistor M 22 receive the power voltage VDD, the second end of the transistor M 22 is coupled to the second output end OE 2 , and a control end of the transistor M 22 receives the pre-charge enable signal PRE.

Both of the transistors M 21 and M 22 are turned on according to the pre-charge enable signal PRE during the pre-charge time period, and voltage levels of the first and second output end OE 1 and OE 2 may be pulled up toward to the power voltage VDD during the pre-charge time period.

The voltage adjusting circuit 230 includes a first voltage adjusting circuit 230 - 1 and a second voltage adjusting circuit 230 - 2 . The first voltage adjusting circuit 230 - 1 includes a switch SW 31 , a transistor M 31 , and a capacitor C 1 . A first end of the switch SW 31 receives a reference voltage VREF, and a control end of the switch SW 31 receives read enable signal RON. A first end of the transistor M 31 is coupled to the first output end OE 1 , a control end of the transistor M 31 is coupled to a second end of the switch SW 31 , and a second end of the transistor M 31 is coupled to a first end of the capacitor C 1 . The second end of the switch SW 31 is a first receiving end for receiving the reference voltage VREF when the switch SW 31 is turned on. Further, a second end of the capacitor C 1 is coupled to a control end of a transistor M 32 disposed in the second voltage adjusting circuit 230 - 2 .

The second voltage adjusting circuit 230 - 2 further includes a switch SW 32 and a capacitor C 2 . A first end of the switch SW 32 receives a bit-line voltage VBL from a selected memory cell, and a control end of the switch SW 32 receives read enable signal RON. The second end of the switch SW 32 is a second receiving end for receiving the bit-line voltage VBL when the switch SW 32 is turned on. A first end of the transistor M 32 is coupled to the second output end OE 2 , a control end of the transistor M 32 is further coupled to a second end of the switch SW 32 , and a second end of the transistor M 32 is coupled to a first end of the capacitor C 2 . Further, a second end of the capacitor C 2 is coupled to the control end of a transistor M 31 disposed in the first voltage adjusting circuit 230 - 1 .

By the first and second voltage adjusting circuits 230 - 1 and 230 - 2 , the voltage level on the first output end OE 1 may be adjusted by a voltage applied on the second end of the capacitor C 1 , and the voltage level on the second output end OE 2 may be adjusted by a voltage applied on the second end of the capacitor C 2 .

In this embodiment, the switches SW 31 and SW 32 are turned on during the pre-charge time period according to the read enable signal RON. That is, during the pre-charge time period, the reference voltage VREF and the bit-line voltage VBL are respectively transported to the first and second receiving ends through the switches SW 31 and SW 32 , respectively.

The discharge circuit 250 includes a first discharge circuit 250 - 1 and a second discharge circuit 250 - 2 . The first discharge circuit 250 - 1 is coupled between the first receiving end and the reference ground GND, and controlled by a discharge enable signal CP. The second discharge circuit 250 - 2 is coupled between the second receiving end and the reference ground GND, and controlled by the discharge enable signal CP.

The first and second discharge circuits 250 - 1 and 250 - 2 respectively include transistors M 51 and M 52 . A first end of the transistor M 51 is coupled to the first receiving end, a second end of the transistor M 51 is coupled to the reference ground, and a control end of the transistor M 51 receives the discharge enable signal CP. A first end of the transistor M 52 is coupled to the second receiving end, a second end of the transistor M 52 is coupled to the reference ground, and a control end of the transistor M 52 receives the discharge enable signal CP.

During the discharge time period, the transistors M 51 and M 52 are turned on according to the discharge enable signal CP, and the voltage levels of the first and second receiving ends are pulled down to the reference ground by the transistors M 51 and M 52 . Then, a voltage drop on the first receiving end may be induced to a voltage drop on the second output end OE 2 through the second voltage adjusting circuit 230 - 2 , and a voltage drop on the second receiving end may be induced to a voltage drop on the first output end OE 1 through the first voltage adjusting circuit 230 - 1 .

The initial circuit 240 includes a first initial circuit 240 - 1 and a second initial circuit 240 - 2 . The first initial circuit 240 - 1 is coupled to the first output end OE 1 , and the second initial circuit 240 - 2 is coupled to the second output end OE 2 . The first and second initial circuits 240 - 1 and 240 - 2 respectively include transistors M 41 and M 42 . First and second ends of the transistor M 41 are respectively coupled to the first output end OE 1 and the reference ground GND, first and second ends of the transistor M 42 are respectively coupled to the second output end OE 2 and the reference ground GND, and the control ends of the transistors M 41 and M 42 receive an initial enable signal DIS. During an initial time period, the transistors M 41 and M 42 are turned on according to the initial enable signal DIS, and the voltage levels of the first and second output end OE 1 and OE 2 are pulled down to equal to the reference ground GND.

About the detail action of the operation of the sense amplifier 200 , referring to FIG. 2 , and FIG. 3 , wherein FIG. 3 illustrates a waveform plot of the sense amplifier 200 .

During the initial time period TINT, the switches SW 1 and SW 2 are turned off, and the first and second inverting circuits 211 and 212 are disabled. Moreover, the transistors M 41 and M 42 are turned on according to the initial enable signal DIS, and the voltages VQB and VQ of the first and second output ends OE 1 and OE 2 are pulled to equal to the reference ground GND (ex. 0V). The switches SW 31 and SW 32 are turned on according to the read enable signal RON, and the first and second voltage adjusting circuits 230 - 1 and 230 - 2 respectively receive the reference voltage VREF and the bit-line voltage VBL. Besides, the transistors M 21 and M 22 are cut off according to the pre-charge enable signal PRE during the initial time period TINT. Additional, the transistors M 51 and M 52 are cut off during the initial time period TINT.

During the initial time period TINT, since the reference voltage VREF and the bit line voltage VBL gradually rise to a high voltage level simultaneously, voltages VDAGB and VDAG may gradually rise to a high voltage level simultaneously accordingly. On the other hand, voltages VQB and VQ are held on equal to the reference ground GND, and voltages VDCB and VDC may also be held on equal to the reference ground GND. That is, during the initial time period TINT, both of the voltage drops of the capacitors C 1 and C 2 are reset to zero.

During the pre-charge time period TPRE, the transistors M 41 and M 42 are cut off, and the paths for pulling down the voltages VQB and VQ on the first and second output ends OE 1 and OE 2 are cut off. Further, the transistors M 21 and M 22 are turned on, and the voltages VQB and VQ on the first and second output ends OE 1 and OE 2 are pulled up toward to the power voltage VDD. During the same time period, the reference voltage VREF and the bit line voltage VBL are gradually reduced. If the bit line voltage VBL corresponding to a stored data “0”, the bit line voltage VBL is smaller than the reference voltage VREF (ex. The bit line voltage VBL 0 ), and if the bit line voltage VBL corresponding to a stored data “1”, the bit line voltage VBL is larger than the reference voltage VREF (ex. The bit line voltage VBL 1 ).

On the other hand, during the pre-charge time period TPRE, after the time point which the transistors M 21 and M 22 are turned on, the voltages VDC and VDCB are respectively gradually pulled up toward to VBL-VTH 2 and VREF-VTH 1 , wherein VTH 2 is a threshold voltage of the transistor M 32 and VTH 1 is a threshold voltage of the transistor M 31 . The increasing of the voltages VDC and VDCB are respectively corresponding to the reducing of the bit line voltage VBL and the reference voltage VREF. At an end time point of the pre-charge time period TPRE, the voltage VDC may be equal to VBL-VTH 2 , and the voltage VDCB may be equal to VREF-VTH 1 . Such as that, the voltage VDC may be the voltage VDC 0 which is corresponding to the bit line voltage VBL 0 , and the voltage VDC may be the voltage VDC 1 which is corresponding to the bit line voltage VBL 1 .

Similar to the voltages VDCB and VDC, the voltages VDAGB and VDAG are gradually reduced according to the reducing of the bit line voltage VBL and the reference voltage VREF. If the bit line voltage VBL is corresponding to the stored data “1”, the voltage VDAG may be varied such as voltage VDAG 1 , and if the bit line voltage VBL is corresponding to the stored data “0”, the voltage VDAG may be varied such as voltage VDAG 0 .

Please be noted here, the voltage VDAG 1 is held on larger than the voltage VDAGB during the pre-charge time period TPRE after the voltages VDAG and VDAGB are reduced, and the voltage VDAG 0 is held on smaller than the voltage VDAGB during the pre-charge time period TPRE after the voltages VDAG and VDAGB are reduced.

During the discharge time period TDIS, the transistors M 51 and M 52 are turned on, and the voltages VDAGB and VDAG are pulled down to the reference ground GND suddenly. Additional, during the discharge time period TDIS, the transistors MSW 1 , MSW 2 , M 21 , M 22 , M 41 and M 42 are cut off, and the switches SW 31 , SW 32 are all cut off at this time too.

Accordingly, during the discharge time period TDIS, the voltages VQB and VQ are respectively pulled down through the capacitors C 1 and C 2 based on the voltage drops on the voltages VDAGB and VDAG. If the bit line voltage VBL of the selected memory cell is corresponding to the stored data “1”, since the voltage VDAG 1 is larger than the voltage VDAGB at the end time point of the pre-charge time period TPRE, a pulled down amount of the voltage VQB is larger than a pulled down amount of the voltage VQ (ex. VQ 1 and VQB 1 ). That is, the voltage difference between the voltages VQ and VQB can be enlarged, and the stored data can be sensed easily and quickly during the sense time period TSEN. On the contrary, If the bit line voltage VBL of the selected memory cell is corresponding to the stored data “0”, since the voltage VDAG 0 is smaller than the voltage VDAGB at the end time point of the pre-charge time period TPRE, a pulled down amount of the voltage VQB is smaller than a pulled down amount of the voltage VQ (ex. VQ 0 and VQB 0 ). That is, the voltage difference between the voltages VQ and VQB can also be enlarged, and the stored data can be sensed easily and quickly during the sense time period TSEN.

It should be noted here, since the transistors M 31 and M 32 are operated on a saturation region. The currents of transistor M 31 and M 32 can be respectively presented by the formulas (1) and (2) shown as below:

Id 1=½ μ n Cox*W/L* ( VGS 1 −VTH 1) 2   (1)

Id 2=½ μ n Cox*W/L* ( VGS 2 −VTH 2) 2   (1)

Wherein, μ n is carrier mobility, Cox is a capacitance of a gate oxide of the transistors M 31 and M 32 , W/L is a ratio of channel width and length of the transistors M 31 and M 32 , VGS 1 is a voltage drop of gate and source of the transistor M 31 , VTH 1 is a threshold voltage of the transistor M 31 , VGS 2 the a voltage drop of gate and source of the transistor M 32 , and VTH 2 is a threshold voltage of the transistor M 32 .

The VGS 1 −VTH 1 of the formula (1) can be presented by VBL−VREF+VTH 1 −VTH 1 =BL−VREF, and the VGS 2 −VTH 2 of the formula (2) can be presented by VREF−VBL+VTH 2 −VTH 2 =VREF−BL. That is, the terms VTH 1 and VTH 2 are eliminated, and the device mismatch effect between the transistor M 31 and M 32 can be ignored in the sense amplifier 200 . Furthermore, a voltage differences of the voltages VQ and VQB is effected by a discharged effect caused by the transistors M 31 and M 32 . From the formula “VBL−VREF−(VREF−VBL)=2*(VBL−VREF)”, a doubled sense margin of the sense amplifier 200 can be obtained.

Additional, at a beginning time point of the discharge time period TDIS, the voltages VDC and VDCQ are pulled down to smaller than the reference ground GND.

During the sense time period TSEN, the switches SW 31 and SW 32 are cut off, and the switches MSW 1 and MSW 2 are turned on. Further, the transistors M 21 , M 22 , M 41 , M 42 , M 51 and M 52 are all turned off. The first and second inverting circuits 211 and 212 receive the power voltage VDD through the switch MSW 1 and coupled to the reference ground GND through the switch MSW 2 , and the first and second inverting circuits 211 and 212 are enabled to sense the data stored in the selected memory cell according to the voltages VQ and VQB. Since the difference of the voltages VQ and VQB is enlarged, the data stored in the selected memory cell can be quickly sensed, and the performance can be promoted.

In summary, in present disclosure, the discharge circuit and the voltage adjusting circuit are provided, and the voltage difference between the two input ends of the first and second inverting circuit can be enlarged efficiency. Such as that, the voltage difference for data sensing can be enlarged, and the data sensing operation can be completely quickly. Further, in some embodiment of present disclosure, the device mismatch in the sense amplifier can be reduced, and the performance of the sense amplifier can be promoted.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.