Substrate, semiconductor package thereof and process of making same

This application claims the benefit of and priority to P.R.C. (China) Patent Application No. 201410186379.X filed on May 5, 2014, the contents of which are incorporated herein by reference in their entirety.

1. Field of the Disclosure

The subject application relates to a substrate for semiconductor package and a process of making the same.

2. Description of the Related Art

With miniaturization of integrated circuit (IC) products, and increasing demands on the number of available input/output (I/O) connections, new packaging types are sought.

An embodiment of the subject application relates to a substrate with an upper circuit layer and a lower circuit layer. The upper circuit layer includes at least one trace and at least one pad, and the lower circuit layer includes at least one trace and at least one pad. The trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.

Another embodiment of the subject application relates to a semiconductor package including a substrate with an upper circuit layer and a lower circuit layer. The upper circuit layer includes at least one trace and at least one pad, and the lower circuit layer includes at least one trace and at least one pad. The upper circuit layer and the trace of the lower circuit layer are not aligned. A die is electrically connected to the upper circuit layer.

A further embodiment of the subject application relates to a process of making a substrate, including: providing a conductive layer with a first surface and a second surface, patterning the first surface to form at least one first trace and at least one first pad, and patterning the second surface to form at least one second trace and at least one second pad.

FIG. 1 is a cross-sectional diagram of a substrate, which is a profile along C-C′ of FIG. 6 according to an embodiment of the subject application;

FIG. 2 is a cross-sectional diagram of a substrate, which is a profile along D-D′ of FIG. 6 according to an embodiment of the subject application;

FIG. 3 is a cross-sectional diagram of an embodiment of a substrate according to the subject application;

FIG. 4 is a top-view diagram of an embodiment of an upper circuit layer;

FIG. 5 is a top-view diagram of an embodiment of a lower circuit layer;

FIG. 6 is a top-view diagram of an embodiment of a circuit pattern formed through a combination of a lower circuit layer and an upper circuit layer;

FIG. 7A is a top-view diagram of an embodiment of relative positions of two adjacent traces of a substrate according to the subject application; FIG. 7B is a front-view diagram, relative to the direction of FIG. 7A , of an embodiment of upper traces 12 and pads 24 of the substrate of FIG. 7A ; FIG. 7C is a front-view diagram, relative to the direction of FIG. 7A , of an embodiment of lower traces 10 and pads 18 of the substrate of FIG. 7A ; and FIG. 7D is a side-view diagram, relative to the direction of FIG. 7A , of an embodiment of two adjacent traces 10 and 12 of the substrate of FIG. 7A ;

FIG. 8A is a diagram of an embodiment of a single-layer circuit pattern;

FIG. 8B is a diagram of an embodiment of a two layer circuit pattern;

FIG. 9 is a diagram of an embodiment of a semiconductor package according to the subject application;

FIG. 10 is a diagram of another embodiment of a semiconductor package according to the subject application;

FIG. 11 is a diagram of a further embodiment of a semiconductor package according to the subject application; and

FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12I, 12J, 12K, 12L, 12M, 12N, 12O, 12P, 12Q and 12R are diagrams of an embodiment of a process of making a substrate according to the subject application.

FIG. 1 is a cross-sectional diagram of a substrate, which is a profile along C-C′ of FIG. 6 according to an embodiment of the subject application. As shown in FIG. 1 , a substrate 8 includes a lower circuit layer 1 with lower traces 10 and pads 24 . The lower traces 10 are electrically isolated from each other. The substrate 8 also includes an upper circuit layer 2 with upper traces 12 and pads (not shown) located above the lower circuit layer 1 . The upper traces 12 are electrically isolated from each other. The lower circuit layer 1 and the upper circuit layer 2 are formed from a single conductive layer, such as, for example, copper. Each upper trace 12 of the upper circuit layer 2 has an upper surface 12 a and a lower surface 12 b . Each lower trace 10 of the lower circuit layer 1 has an upper surface 10 a and a lower surface 10 b . The lower surface 12 b and the lower surface 10 b are substantially in the same plane.

The lower traces 10 and the upper traces 12 are not aligned in the illustration of FIG. 1 ; in other words, a minimum distance D 1 between a lower trace 10 and an upper trace 12 is greater than zero. The minimum distance D 1 is less than a minimum distance D 2 (e.g., trace spacing or pitch) between two upper traces 12 (or a minimum trace spacing or pitch between two lower traces 10 ).

Traces generally may be formed as lower traces 10 or upper traces 12 . The formation of the traces as lower traces 10 or upper traces 12 may, in some instances, be based upon process capabilities, such as trace line width and trace line spacing. For example, when a distance between adjacent pads 24 is a fixed value (e.g., 310 μm), and trace line width and trace line spacing are respectively 50 μm and 70 μm, the number of lower traces 10 passing between two adjacent pads 24 may be selected as one lower trace 10 to allow for process variation (the use of two lower traces 10 at 50 μm each, plus three spaces at 70 μm each, adds to 310 μm, which does not allow for process variation). In such a case, additional traces may be routed as upper traces 12 . As illustrated for the portion of the embodiment illustrated in FIG. 1 (and as can be seen in the top view in FIG. 6 along line C-C′), two traces are routed between adjacent pads 24 , where one trace is routed as a lower trace 10 , and one trace is routed as an upper trace 12 . Some upper traces 12 of the upper circuit layer 2 and some lower traces 10 of the lower circuit layer 1 may be staggered.

In one or more embodiments, a sidewall contour of each of the lower traces 10 and upper traces 12 is a result of an etching technology used to form the lower circuit layer 1 and the upper circuit layer 2 from a single conductive layer, as described below. In one or more embodiments, as illustrated in FIG. 1 , a sidewall contour of the upper traces 12 of the upper circuit layer 2 may be arcuate, such that a width of the upper surface 12 a is less than a width of the lower surface 12 b . In one or more embodiments, a sidewall contour of the lower traces 10 of the lower circuit layer 2 may be arcuate, such that a width of the upper surface 10 a is less than a width of the lower surface 10 b , as illustrated in FIG. 1 .

In one or more embodiments, the upper traces 12 of the upper circuit layer 2 and the pads (ball pads) 24 of the lower circuit layer 1 may overlap, as illustrated in FIG. 1 (and see also Region B in FIG. 6 ). For example, an upper trace 12 and a pad 24 may overlap so as to electrically connect the pad 24 to a position on the substrate 8 at a distance from the pad 24 .

The substrate 8 may include a protective material surrounding the upper traces 12 of the upper circuit layer 2 and the lower traces 10 of the lower circuit layer 1 . The protective material may include an upper protective layer 31 surrounding and covering the upper traces 12 , and a lower protective layer 21 surrounding and covering the lower traces 10 . The lower protective layer 21 may have openings to expose the pads 24 , as illustrated in FIG. 1 , such as to allow solder balls to be formed thereon.

In one or more embodiments, the lower protective layer 21 and the upper protective layer 31 may be made of photosensitive materials such as photosensitive polymers, which, for example, may be selected from, but are not limited to, polyparaphenylene benzobisoxazole (PBO), polyimide, benzocyclobutene or a combination thereof. By using photosensitive materials and a lithography process, the lower protective layer 21 can include openings through which the lower circuit layer 1 (e.g., pads 24 ) is exposed, and the upper protective layer 31 can include openings through which the upper circuit layer 2 is exposed (e.g., pads 18 in FIG. 2 ). In other embodiments, one or both of the lower protective layer 21 and the upper protective layer 31 are solder resist layers. A solder resist layer may include, for example, photosensitive polymers.

FIG. 2 is a cross-sectional diagram of a substrate, which is a profile along D-D′ of FIG. 6 according to an embodiment of the subject application. Similarly to the profile view along C-C′ as illustrated in FIG. 1 , the substrate 8 of FIG. 2 includes the lower circuit layer 1 with lower traces 10 and pads (not shown), where the lower traces 10 are electrically isolated from each other; and the upper circuit layer 2 with upper traces 12 is located above the lower circuit layer 1 , where the upper traces 12 are electrically isolated from each other. The upper circuit layer 2 further includes pads 18 . The pads 18 may have a surface finish layer 35 thereon; for example, a surface finish layer 35 of nickel, gold, or a combination thereof, or stacked nickel/gold layers. The surface finish layer 35 serves as a wire bond contact, for example, for wire bonding to a semiconductor chip. In one or more embodiments, the pads (fingers) 18 of the upper circuit layer 2 and the lower traces 10 of the lower circuit layer 1 may overlap, as illustrated in FIG. 2 (and see also Region A of FIG. 6 ). For example, a lower trace 10 and a pad 18 may overlap so as to electrically connect the pad 18 to a position on the substrate 8 at a distance from the pad 18 .

FIG. 3 is a cross-sectional diagram of another embodiment of a substrate according to the subject application. The substrate 8 ′ is different from the substrate 8 of FIGS. 1 and 2 in that a reinforcing layer 20 is included, and portions of the reinforcing layer 20 are positioned below some of the pads 18 , to enhance the strength of the pads 18 where wires bond. The lower circuit layer 1 and the upper circuit layer 2 are formed of conductive materials, such as, for example, copper. In one or more embodiments, the reinforcing layer 20 may be a conductive layer made of the same material as that of the lower traces 10 . The lower traces 10 and the reinforcing layer 20 may be formed in the same process. A shape and size of the reinforcing layer may vary according to design needs. For example, a width or a length of portions of the reinforcing layer 20 may be less than those of the lower traces 10 .

In one or more embodiments, a lower protective layer 21 and an upper protective layer 31 may be made of photosensitive materials such as photosensitive polymers, which, for example, may be selected from, but are not limited to, polyparaphenylene benzobisoxazole (PBO), polyimide, benzocyclobutene or a combination thereof. By using photosensitive materials and a lithography process, the lower protective layer 21 can include openings through which the lower circuit layer 1 (e.g., pads 24 ) is exposed, and the upper protective layer 31 can include openings through which the upper circuit layer 2 (e.g., pads 18 ) is exposed. In other embodiments, one or both of the lower protective layer 21 and the upper protective layer 31 are solder resist layers. A solder resist layer may include, for example, photosensitive polymers.

FIGS. 4 to 6 illustrate examples of circuit layer designs: FIG. 4 is a top-view diagram of an embodiment of an upper circuit layer 2 ; FIG. 5 is a top-view diagram of an embodiment of a lower circuit layer 1 ; and FIG. 6 is a top-view diagram of an embodiment of a circuit pattern formed through a combination of the upper circuit layer 2 of FIG. 4 and the lower circuit layer 1 of FIG. 5 . Many other designs are also possible, and are within the scope of this disclosure. As shown in FIG. 4 , in some embodiments, the pads 18 (e.g., as shown as lighter-shaded shapes) may be positioned on the upper circuit layer 2 to accommodate, for example, connection to a particular pad arrangement of a semiconductor die; and as shown in FIG. 5 , in some embodiments, the pads 24 (shown as circular, lighter-colored shapes) may be positioned on the lower circuit layer 1 to connect, for example, to another device or to a circuit board. As can be seen in FIG. 6 , with the pattern of the upper circuit layer 2 of FIG. 4 overlaid on the pattern of the lower circuit layer 1 of FIG. 5 , the techniques of this disclosure provide for a dense routing of traces. For example, trace X 1 in upper circuit layer 2 ( FIG. 4 ) and trace Y 1 in lower circuit layer 1 ( FIG. 5 ) are both positioned between two adjacent pads 18 (and between two adjacent pads 24 —the adjacent pads 18 are aligned with the adjacent pads 24 in this example); and trace X 2 in circuit layer 2 ( FIG. 4 ) and trace Y 2 in circuit layer 1 ( FIG. 5 ) are both positioned between two adjacent pads 18 (and between two adjacent pads 24 —the adjacent pads 18 are aligned with the adjacent pads 24 in this example). Routing in this manner, using an upper circuit layer 2 and a lower circuit layer 1 , allows for more traces through a cross-sectional area than could be implemented with a single circuit layer; consequently, more I/O connections may be made. Further, because the traces are dispersed on two layers (lower circuit layer 1 and upper circuit layer 2 ), etching tolerances may be increased, yield may be improved, and manufacturing costs may be reduced.

Also shown in FIG. 6 is that traces of the lower circuit layer 1 (e.g., lower traces 10 in FIG. 2 ) and pads of the upper circuit layer 2 (e.g., pads 18 in FIG. 2 ) may at least partially overlap, and traces of the upper circuit layer 2 (e.g., upper traces 12 in FIG. 1 ) and pads of the lower circuit layer 1 (e.g., pads 24 in FIG. 1 ) may at least partially overlap, allowing for electrical connection between the lower circuit layer 1 and the upper circuit layer 2 .

FIGS. 7A to 7D illustrate relative trace and pad positioning according to an embodiment of the subject application. FIG. 7A is a top-view diagram of relative positions of two adjacent traces (e.g., traces X 1 , Y 1 or X 2 , Y 2 of FIG. 6 ): an upper trace 12 of upper circuit layer 2 and a lower trace 10 of lower circuit layer 1 . FIG. 7B is a front-view diagram, relative to the direction of FIG. 7A , of the upper trace 12 and the pad 24 of FIG. 7A . FIG. 7C is a front-view diagram, relative to the direction of FIG. 7A , of the lower traces 10 and the pad 18 of FIG. 7A . FIG. 7D is a side-view diagram, relative to the direction of FIG. 7A , of the two adjacent traces (lower trace 10 and upper trace 12 ) of FIG. 7A . As shown in FIG. 7B , some of the pads 24 may overlap with the upper traces 12 . As shown in FIG. 7C , some of the pads 18 may overlap with the lower traces 10 . As shown in FIG. 7D , adjacent traces 10 and 12 may be designed as part of the upper circuit layer 1 and part of the lower circuit layer 2 , respectively.

FIGS. 8A and 8B illustrate a comparison of a single circuit layer implementation versus a two circuit layer implementation, showing the benefits of implementation in two circuit layers. FIG. 8A is a cross-section diagram of an embodiment of a single-layer circuit pattern 37 . FIG. 8B is a cross-section diagram of an embodiment of a two-layer circuit pattern including an upper circuit layer 37 a and a lower circuit layer 37 b . In this comparison, a total thickness of the two layers 37 a and 37 b is equivalent to a thickness of the single-layer circuit pattern 37 . However, the same number of traces (three) is illustrated in both FIG. 8A and FIG. 8B . Therefore, a spacing W 2 between two adjacent circuits on the upper circuit layer 37 a (or between two adjacent circuits on the lower circuit layer 37 b ) may be greater than a spacing W 1 between two adjacent circuits in the single-layer embodiment of FIG. 8A (i.e. W 2 >W 1 ). Accordingly, etching tolerance increases, and yield in etching may be improved. Alternatively, if etching tolerances of the two-layer circuit implementation are the same as for the single-layer circuit implementation, the spacing W 2 between a first and a third trace in the two-layer circuit implementation may be less than a spacing W 3 between a first and third trace in the single-layer circuit implementation. In other words, a spacing W 4 between two adjacent circuits in the upper circuit layer 37 a and the lower circuit layer 37 b may be less than the spacing W 1 ; hence, wiring design flexibility may be improved, circuit density may be improved, and process yield may be improved.

FIG. 9 is a diagram of an embodiment of a semiconductor package according to the subject application. A semiconductor package 14 comprises a substrate 8 with a lower circuit layer 1 and an upper circuit layer 2 , a die 3 , an adhesive 9 , pads 18 , wires 7 and a package material 5 . The die 3 is attached to the substrate 8 with adhesive 9 , and the pads 18 are formed in an opening of an upper protective layer 31 of substrate 8 , for connection with the wires 7 . The package material 5 is located on the upper protective layer 31 , and encapsulates the die 3 and the adhesive 9 . In one or more embodiments, solder balls 11 are formed on the lower circuit layer 1 (pads) exposed from openings of a lower protective layer 21 of substrate 8 to serve as an external connection. In other embodiments, electroplating tin may also be formed on the lower circuit layer 1 (pads) exposed in the openings of the lower protective layer 21 to serve as an external connection.

FIG. 10 is a diagram of another embodiment of a semiconductor package according to the subject application. A semiconductor package 14 ′ is different from the semiconductor package 14 shown in FIG. 9 , in that the die 3 of FIG. 10 is electrically connected with the upper circuit layer 2 of the substrate 8 through solder balls 36 in a flip chip form. In one or more embodiments, solder balls 11 may be formed on the lower circuit layer 1 (pads) exposed in the openings of a lower protective layer 21 to serve as an external connection.

FIG. 11 is a diagram of a further embodiment of a semiconductor package according to the subject application. The semiconductor package is different from the semiconductor package 14 shown in FIG. 9 , in that the semiconductor package of FIG. 11 includes a second substrate 8 . The two substrates 8 are electrically connected by, for example, a conductive adhesive 22 , which may be patterned. The two substrates 8 may be formed in the same manner, and each substrate 8 may include an upper circuit layer 2 and a lower circuit layer 1 . In one or more embodiments, a minimum distance D 3 between an upper trace 12 included in the upper circuit layer 2 of a substrate 8 and a lower trace 10 included in the lower circuit layer 1 of the substrate 8 is greater than zero. The minimum distance D 3 may be less than minimum trace spacing (pitch) corresponding to the process used to form the lower circuit layer 1 and the upper circuit layer 2 . In one or more embodiments, solder balls (not shown) may be formed on a lower circuit layer 1 (pads) exposed in openings of a lower protective layer 21 of one substrate 8 to serve as an external connection for the one substrate 8 .

FIGS. 12A to 12R are diagrams of an embodiment of a process of making a substrate according to the subject application.

Referring to FIG. 12A , a conductive layer 13 is provided. Conductive layer 13 may be a metal, such as, for example, copper, or may be another conductive material. Referring to FIG. 12B , a first dry film 15 is formed on the conductive layer 13 . Referring to FIG. 12C , the first dry film 15 is patterned into a patterned first dry film 17 , to expose part of the conductive layer 13 , and to define positions for traces and pads of a circuit layer to be subsequently formed. The patterning process may include, for example, a lithographic technique.

Referring to FIG. 12D , part of the conductive layer 13 is removed, to form traces and pads 19 of a lower circuit layer 1 . The conductive layer 13 may be removed by etching or by other techniques. In one or more embodiments, the conductive layer 13 is removed by etching, such that a sidewall contour of traces of the lower circuit layer 1 is not a plane. For example, as shown in FIG. 12D , the sidewall contour may be arcuate. Referring to FIG. 12E , the patterned first dry film 17 is removed, to expose the traces and pads 19 of the lower circuit layer 1 .

Referring to FIG. 12F , a lower protective layer 21 is formed on the lower circuit layer 1 . The lower protective layer 21 surrounds and covers the traces and pads 19 of the lower circuit layer 1 . In some embodiments, the lower protective layer 21 may be formed through spin coating, spray coating or lamination. Referring to FIG. 12G , the lower protective layer 21 is patterned, to form openings 23 and thereby define positions in the lower circuit layer 1 where pads are to be formed. The patterning process may include a lithographic technique.

Referring to FIG. 12H , a second dry film 25 is formed on a surface of the conductive layer 13 opposite where the lower circuit layer 1 is formed. Referring to FIG. 12I , the second dry film 25 is patterned to form a patterned second dry film 27 , to expose part of the conductive layer 13 , and to define positions for traces and pads to be subsequently formed. The patterning process may include a lithographic technique. Referring to FIG. 12J , a part of the conductive layer 13 not covered by the patterned second dry film 27 is removed from the conductive layer 13 , to form an upper circuit layer 2 with traces and pads 29 , including upper traces 12 . The conductive layer 13 may be removed through etching or by other techniques. As shown in FIG. 12J , sidewalls of the traces and pads 29 of the upper circuit layer 2 generated by removing the conductive layer 13 through etching may be arcuate.

Referring to FIG. 12K , the patterned second dry film 27 is removed. Referring to FIG. 12L , an upper protective layer 31 is formed, and the upper protective layer 31 surrounds and covers the traces and pads 29 of the upper circuit layer 2 . In some embodiments, the upper protective layer 31 may be formed through spin coating, spray coating or lamination. The region within the dotted line in FIG. 12L is enlarged in FIG. 12M . As shown in FIG. 12M (and FIGS. 12J to 12L ), in embodiments in which etching is used to remove portions of the conductive layer 13 to form the traces and pads 19 of the circuit layer 1 and the traces and pads 29 of the circuit layer 2 , the sidewalls of the traces and pads 19 of the lower circuit layer 1 and the sidewalls of the traces and pads 29 of the upper circuit layer 1 arc such that a width of a top surface of the traces and pads 19 , 29 is less than a width of a bottom surface of the traces and pads 19 , 29 . Referring to FIG. 12N , the upper protective layer 31 is patterned, to form openings 33 , and to define positions in the upper circuit layer 2 where pads or fingers are to be formed. The patterning process may include a lithographic technique. Referring to FIG. 12O , a conductive surface finish layer 35 (e.g., nickel, gold, or a combination thereof, or a stacked nickel/gold layer) may be formed on the pads in the upper circuit layer 1 , to facilitate subsequent wire bonding. The surface finish layer 35 may be formed at an opening of the upper protective layer 31 through immersion, plating, chemical plating, printing, or with other techniques.

Referring to FIG. 12P , a die 3 may be attached to the upper circuit layer 2 by means of an adhesive 9 , and may be electrically connected with the surface finish layer 35 of the upper circuit layer 2 by way of wires 7 . Referring to FIG. 12Q , the die 3 is covered with a package material 5 , forming a semiconductor package 14 . Referring to FIG. 12R , solder balls 11 may be formed at openings in the protective layer 21 (e.g., on pads of the lower circuit layer 1 ), available for an external connection.

Thus has been described a substrate including a conductive layer with two circuit layers formed therein, where the techniques described provide for more dense trace routing, increased I/O connections, improved yield in circuit etching, and greater design flexibility.

As used herein and not otherwise defined, the term “substantially” is used to describe and account for small variations. For example, the terms can refer to less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

Two surfaces can be deemed to be coplanar or substantially in the same plane if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.