Memory device with stable writing and/or reading operation

Static random access memory (SRAM) is a kind of memory which uses bistable latching circuit for storing each bit. The term “static” random access memory is different from “dynamic” random access memory (DRAM) which must be periodically refreshed. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.

However, due to capability difference among transistors of SRAM, a writing operation of SRAM may fail. On the other hand, due to a bias generated among transistors of SRAM thereby making one of memory cells in SRAM flip, a reading operation of SRAM may fail.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of a static random access memory (SRAM) in accordance with some embodiments.

FIG. 2 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 1 in accordance with some embodiments.

FIG. 3 is a schematic diagram of the SRAM as illustrated in FIG. 1 in accordance with some embodiments.

FIG. 4 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 3 in accordance with some embodiments.

FIG. 5 is a schematic diagram of a SRAM in accordance with some embodiments.

FIG. 6 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 5 in accordance with some embodiments.

FIG. 7 is a schematic diagram of the SRAM as illustrated in FIG. 5 in accordance with some embodiments.

FIG. 8 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 7 in accordance with some embodiments.

FIG. 9 is a schematic diagram of the SRAM as illustrated in FIG. 5 in accordance with some embodiments.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.

It will be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.

Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, uses of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1 is a schematic diagram of a static random access memory (SRAM) in accordance with some embodiments.

As illustratively shown in FIG. 1 , the SRAM 100 includes a complementary metal oxide semiconductor (CMOS) inverter C 1 , a CMOS inverter C 2 , an accessing unit 110 , and a switching unit 120 . The CMOS inverter C 1 includes a p-type metal oxide semiconductor (PMOS) transistor P 1 and a N-type metal oxide semiconductor (NMOS) transistor N 1 . Each of the PMOS transistor P 1 and the NMOS transistor N 1 includes a first terminal, a second terminal, and a control terminal. The second terminal of the PMOS transistor P 1 is coupled to the first terminal of the NMOS transistor N 1 at a node S 1 which indicates an output of the CMOS inverter C 1 .

In addition, the CMOS inverter C 2 includes a PMOS transistor P 2 and a NMOS transistor N 2 . Each of the PMOS transistor P 2 and the NMOS transistor N 2 includes a first terminal, a second terminal, and a control terminal. The second terminal of the PMOS transistor P 2 is coupled to the first terminal of the NMOS transistor N 2 at a node S 2 which indicates an output of the CMOS inverter C 2 . The CMOS inverter C 2 is cross-coupled with the CMOS inverter C 1 . The accessing unit 110 is coupled to a word line WWL, a word line WWLB, the node S 1 , and the node S 2 . The switching unit 120 is coupled to a power voltage VDD, the word line WWL, the first terminal of the PMOS transistor P 1 , and the first terminal of the PMOS transistor P 2 .

In some embodiments, the SRAM 100 further includes a reading unit 130 . The reading unit 130 is coupled to a word line RWL, a bit line RBL, and the output of the CMOS inverter C 1 .

FIG. 2 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 1 in accordance with some embodiments. For illustration, the operations of the SRAM 100 in FIG. 1 are described with reference to the method 200 .

In operation 210 , the accessing unit 110 discharges the node S 1 and charges the node S 2 according to signals provided by the word line WWL and the word line WWLB, during a writing operation. Hereinafter, the accessing unit 110 charging the node S 2 indicates that the voltage at the node S 2 is successfully pulled up through the accessing unit 110 to the voltage (e.g., the power voltage VDD) on a bit line WBLB. As a result, a write recovery failure during the writing operation is prevented.

In operation 220 , the switching unit 120 is configured to disconnect the power voltage VDD from the first terminal of the PMOS transistor P 1 and the first terminal of the PMOS transistor P 2 according to a signal provided by the word line WWL, during the writing operation. Since the power voltage VDD is disconnected from the first terminal of the PMOS transistor P 1 and the first terminal of the PMOS transistor P 2 , the power voltage VDD does not affect the node S 1 through the PMOS transistor P 1 . Accordingly, the switching unit 120 prevents a write failure.

In operation 230 , the switching unit 120 is configured to connect the power voltage VDD to the first terminal of the PMOS transistor P 1 and the first terminal of the PMOS transistor P 2 according to a signal provided by the word line WWL, during a reading operation.

In operation 240 , the reading unit 130 is configured to discharge the bit line RBL according to a signal provided by the word line RWL and the node S 1 , during the reading operation. Hereinafter, the reading unit 130 discharging the bit line RBL indicates that the voltage of the bit line RBL is successfully pulled down through the reading unit 130 to ground. Since the reading unit 130 is operated as an independent read port, the reading operation is executed independently and will not be affected by other part of the SRAM 100 . Therefore, the signal provided by the bit line RBL is detected by a sense amplifier (not shown), and a read disturbance issue is prevented.

In other approaches, during a write “0” operation, the accessing unit 110 discharges the node S 1 ; meanwhile, the PMOS transistor P 1 is turned on, and the power voltage VDD affects the node S 1 through the PMOS transistor P 1 , which will cause a write connection failure. On the other hand, if the PMOS transistor P 2 is too weak, the node S 2 is not successfully pulled up to the power voltage VDD, which will cause a write recovery failure. During the read operation, the accessing unit 110 discharges the bit line WBL through the node S 1 and the NMOS transistor N 1 to ground, and the voltage stored in the node S 1 raise up to ΔV. The voltage ΔV stored in the node S 1 causes the CMOS inverter C 2 flip and lead to a read disturbance issue.

Compared to the approaches described above, the voltage at the node S 2 is successfully pulled up through the accessing unit 110 to the power voltage VDD as described in the method of FIG. 2 . As a result, the write recovery failure during the writing operation is prevented. On the other hand, the switching unit 120 disconnects the power voltage VDD from the first terminal of the PMOS transistor P 1 during the writing operation as described in the method of FIG. 2 ; and therefore, the power voltage VDD does not affect the node S 1 through the PMOS transistor P 1 . Accordingly, the switching unit 120 prevents the write connection failure. In addition, since the reading unit 130 is operated as an independent read port, the read disturbance issue is prevented.

FIG. 3 is a schematic diagram of the SRAM as illustrated in FIG. 1 in accordance with some embodiments. As illustratively shown in FIG. 3 , the accessing unit 110 includes a CMOS transmission gate 112 and a CMOS transmission gate 114 . The CMOS transmission gate 112 includes an input 112 A, an output 112 B, a control terminal 112 C, and a control terminal 112 D. The input 112 A is coupled to a bit line WBL, the output 112 B is coupled to the node S 1 , the control terminal 112 C is coupled to the word line WWL, and the control terminal 112 D is coupled to the word line WWLB. The CMOS transmission gate 114 includes an input 114 A, an output 114 B, a control terminal 114 C, and a control terminal 114 D. The input 114 A is coupled to the node S 2 , the output 114 B is coupled to a bit line WBLB, the control terminal 114 C is coupled to the word line WWL, and the control terminal 114 D is coupled to the word line WWLB.

In some embodiments, the switching unit 120 includes a transistor P 5 and a transistor P 6 . Each of the transistors P 5 , P 6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor P 5 is coupled to the power voltage VDD. The second terminal of the transistor P 5 is coupled to the first terminal of the PMOS transistor P 1 . The control terminal of the transistor P 5 is coupled to the word line WWL and the CMOS transmission gate 112 of the accessing unit 110 . The first terminal of the transistor P 6 is coupled to the power voltage VDD. The second terminal of the transistor P 6 is coupled to the first terminal of the PMOS transistor P 2 . The control terminal of the transistor P 6 is coupled to the word line WWL and the CMOS transmission gate 114 of the accessing unit 110 .

In some embodiments, the reading unit 130 includes a transistor N 5 and a transistor N 6 . Each of the transistors N 5 , N 6 includes a first terminal, a second terminal, and a control terminal. The second terminal of the transistor N 5 is coupled to the bit line RBL. The control terminal of the transistor N 5 is coupled to the word line RWL. The first terminal of the transistor N 6 is coupled to the first terminal of the transistor N 5 . The second terminal of the transistor N 6 is coupled to ground. The control terminal of the transistor N 6 is coupled to the node S 1 .

In some embodiments, the control terminal of the PMOS transistor P 1 is coupled to the control terminal of the NMOS transistor N 1 . The control terminal of the PMOS transistor P 2 is coupled to the control terminal of the NMOS transistor N 2 . The node S 1 is coupled to the control terminals of the PMOS transistor P 2 and the second NMOS transistor N 2 . The node S 2 is coupled to the control terminals of the PMOS transistor P 1 and the NMOS transistor N 1 .

FIG. 4 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 3 in accordance with some embodiments. For illustration, the operations of the SRAM 100 A in FIG. 3 are described with reference to the method 400 .

In operation 410 , during a writing operation, the CMOS transmission gate 112 is configured to be controlled with the signals provided by the word line WWL and the word line WWLB, to discharge the node S 1 in response to a signal provided by the bit line WBL. Hereinafter, the CMOS transmission gate 112 discharging the node S 1 indicates that the voltage at the node S 1 is successfully pulled down through the CMOS transmission gate 112 to the voltage (e.g., a reference voltage) on the bit line WBL. In some embodiments, the signals provided by the word line WWL and the word line WWLB are opposite.

In operation 420 , during the writing operation, the CMOS transmission gate 114 is configured to be controlled with the signals provided by the word line WWL and the word line WWLB, to charge the node S 2 in response to a signal provided by the bit line WBLB. Hereinafter, the CMOS transmission gate 114 charging the node S 2 indicates that the voltage at the node S 2 is successfully pulled up through the CMOS transmission gate 114 to the voltage (e.g., a power voltage VDD) on the bit line WBLB. Since the node S 2 is charged by the bit line WBLB through the CMOS transmission gate 114 , the voltage stored in the node S 2 is successfully pulled up to the power voltage VDD so as to prevent the write recovery failure.

In operation 430 , during the writing operation, the transistor P 5 is configured to be controlled with the signal provided by the word line WWL, to disconnect the power voltage VDD from the CMOS inverter C 1 . Since the power voltage VDD is disconnected from and the CMOS inverter C 1 , a current path between the PMOS transistor P 1 and the CMOS transmission gate 112 is disconnected so as to prevent the write connection failure.

In operation 440 , during the writing operation, the transistor P 6 is configured to be controlled with the signal provided by the word line WWL, to disconnect the power voltage VDD from the CMOS inverter C 2 .

In operation 450 , during a reading operation, the transistor N 5 is turned on according to the signal provided by the word line RWL, and the transistor N 6 is turned on according to the signal stored in the node S 1 for discharging the bit line RBL. The transistors N 5 , N 6 discharging the bit line RBL indicates that the voltage of the bit line RBL is successfully pulled down through the transistors N 5 , N 6 to ground. Since the reading unit 130 including the transistors N 5 , N 6 is operated as an independent read port, the reading operation can be executed independently and will not be affected by other part of the SRAM 100 A. Therefore, the read disturbance issue during the reading operation can be prevented.

Compared to the approaches described above, the voltage at the node S 2 is successfully pulled up through the CMOS transmission gate 114 to the power voltage VDD as described in the method of FIG. 4 . As a result, the write recovery failure during the writing operation is prevented. On the other hand, the transistor P 5 disconnects the power voltage VDD from the first terminal of the PMOS transistor P 1 during the writing operation as described in the method of FIG. 4 ; and therefore, the power voltage VDD does not affect the node S 1 through the PMOS transistor P 1 . Accordingly, the transistor P 5 prevents the write connection failure. In addition, since the reading unit 130 including the transistors N 5 , N 6 is operated as an independent read port, the read disturbance issue is prevented.

FIG. 5 is a schematic diagram of a SRAM in accordance with some embodiments. As illustratively shown in FIG. 5 , the SRAM 500 includes a CMOS inverter C 1 , a CMOS inverter C 2 , a transistor N 3 , a transistor N 4 , a switching unit 510 , a switching unit 520 , and a switching unit 530 . The CMOS inverter C 1 includes a PMOS transistor P 1 and a NMOS transistor N 1 . Each of the PMOS transistor P 1 and the NMOS transistor N 1 includes a first terminal, a second terminal, and a control terminal. The second terminal of the PMOS transistor P 1 is coupled to the first terminal of the NMOS transistor N 1 at a node S 1 which indicates an output of the CMOS inverter C 1 . The CMOS inverter C 2 is cross-coupled with the CMOS inverter C 1 .

In addition, the CMOS inverter C 2 includes a PMOS transistor P 2 and a NMOS transistor N 2 . Each of the PMOS transistor P 2 and the NMOS transistor N 2 includes a first terminal, a second terminal, and a control terminal. The second terminal of the PMOS transistor P 2 is coupled to the first terminal of the NMOS transistor N 2 at a node S 2 which indicates an output of the CMOS inverter C 2 . Each of the transistors N 3 , N 4 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor N 3 is coupled to a bit line BL. The control terminal of the transistor N 3 is coupled to a word line WL. The second terminal of the transistor N 4 is coupled to a bit line BLB. The control terminal of the transistor N 4 is coupled to the word line WL.

Besides, the switching unit 510 is coupled to the second terminal of the transistor N 3 , the first terminal of the transistor N 4 , the node S 1 , the node S 2 , and a selecting line SEL. The switching unit 520 is coupled to a power voltage VDD, the first terminals of the PMOS transistor P 1 and the PMOS transistor P 2 , and data lines D, DB. The switching unit 530 is coupled to the second terminal of the transistor N 3 , the node S 1 , and the node S 2 .

FIG. 6 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 5 in accordance with some embodiments. For illustration, the operations of the SRAM 500 in FIG. 5 are described with reference to the method 600 .

In operation 610 , during a writing operation, the switching unit 510 is configured to discharge the node S 2 of the CMOS inverter C 2 in response to a signal provided by the bit line BLB through the transistor N 4 , and charge the node S 1 in response to a signal provided by the bit line BL through the transistor N 3 . Hereinafter, the switching unit 510 charging the node S 1 indicates that the voltage at the node S 1 is successfully pulled up through the switching unit 510 to the voltage (e.g., the power voltage VDD) on the bit line BL. As a result, the write recovery failure during the writing operation is prevented.

In operation 620 , during the writing operation, the switching unit 520 is configured to disconnect the power voltage VDD from the CMOS inverter C 2 according to a signal provided by the data line D. Since the power voltage VDD is disconnected from the CMOS inverter C 2 , the power voltage VDD does not affect the node S 2 through the PMOS transistor P 2 . Accordingly, the switching unit 520 prevents the write failure.

In operation 630 , during a reading operation, the switching unit 530 is configured to connect the transistor N 3 to the reference voltage (e.g., ground) according to the signal provided by the node S 2 .

FIG. 7 is a schematic diagram of the SRAM as illustrated in FIG. 5 in accordance with some embodiments. As illustratively shown in FIG. 7 , the switching unit 510 includes a transistor N 5 and a transistor N 6 . Each of the transistors N 5 , N 6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor N 5 is coupled to the second terminal of the transistor N 3 . The second terminal of the transistor N 5 is coupled to the node S 1 . The control terminal of the transistor N 5 is coupled to the selecting line SEL. The first terminal of the transistor N 6 is coupled to the node S 2 . The second terminal of the transistor N 6 is coupled to the first terminal of the transistor N 4 . The control terminal of the transistor N 6 is coupled to the selecting line SEL.

In some embodiments, the switching unit 530 includes a transistor N 7 and a transistor N 8 . Each of the transistors N 7 , N 8 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor N 7 is coupled to the second terminal of the transistor N 3 . The second terminal of the transistor N 7 is coupled to ground. The control terminal of the transistor N 7 is coupled to the node S 2 . The first terminal of the transistor N 8 is coupled to the first terminal of the transistor N 4 . The second terminal of the transistor N 8 is coupled to ground. The control terminal of the transistor N 8 is coupled to the node S 1 .

In some embodiments, the switching unit 520 includes a transistor P 3 and a transistor P 4 . Each of the transistors P 3 , P 4 includes a first terminal, a second terminal, and a control terminal. The first terminals of the transistors P 3 , P 4 are coupled to the power voltage VDD. The second terminal of the transistor P 3 is coupled to the first terminal of the PMOS transistor P 1 . The control terminal of the transistor P 3 is coupled to a data line DB. The second terminal of the transistor P 4 is coupled to the first terminal of the PMOS transistor P 2 . The control terminal of the transistor P 4 is coupled to a second data line D.

In some embodiments, the switching unit 520 further includes a transistor P 5 which is operated as an equalizer. The transistor P 5 is coupled to the first terminals of the PMOS transistor P 1 and the PMOS transistor P 2 .

FIG. 8 is a flow diagram of a method for controlling the SRAM as illustrated in FIG. 7 in accordance with some embodiments. For illustration, the operations of the SRAM 500 A in FIG. 7 are described with reference to the method 800 .

In operation 810 , during a writing period, the transistor N 6 is configured to be controlled with a signal provided by the selecting line SEL, to connect the transistor N 4 with the node S 2 and discharge the node S 2 in response to the signal provided by the bit line BLB through the transistor N 4 . Hereinafter, the transistor N 6 discharging the node S 2 indicates that the voltage of the node S 2 is successfully pulled down through the transistor N 6 to ground.

In operation 820 , during the writing period, the transistor N 5 is configured to be controlled with the signal provided by the selecting line SEL, to connect the transistor N 3 with the node S 1 and charge the node S 1 in response to the signal provided by the bit line BL through the transistor N 3 . Hereinafter, the transistor N 5 charging the node S 1 indicates that the voltage at the node S 1 is successfully pulled up through the transistor N 5 to the voltage (e.g., the power voltage VDD) on the bit line BL. A plurality of the SRAMs 500 A of FIG. 7 can be arranged as an array, and one of the SRAMs 500 A in columns of the array can be selected by the signals provided from the selecting line SEL, such that an array interleaving design can be achieved.

In operation 830 , during the writing period, the transistor P 4 is configured to be controlled with the signal provided by the data line D, to disconnect the power voltage VDD from the CMOS inverter C 2 . Since the power voltage VDD is disconnected from and the CMOS inverter C 2 , a current path between the PMOS transistor P 2 of the CMOS inverter C 2 and the transistor N 4 is disconnected so as to prevent the write connection failure.

In operation 840 , during a reading period, the transistor N 5 is turned off according to the signal provided by the selecting line SEL for disconnecting the second terminal of the transistor N 3 and the node S 1 , and the transistor N 7 is turned on according to the signal provided the node S 2 for discharging the bit line BL. Hereinafter, the transistor N 7 discharging the bit line BL indicates that the voltage of the bit line BL is successfully pulled down through the transistor N 7 to ground.

FIG. 9 is a schematic diagram of the SRAM as illustrated in FIG. 5 in accordance with some embodiments. Compared to the SRAM 500 A in FIG. 7 , the switching unit 520 in the SRAM 500 B of FIG. 9 includes transistors P 3 -P 6 . Each of the transistors P 3 -P 6 includes a first terminal, a second terminal, and a control terminal. The first terminals of the transistors P 3 -P 6 are coupled to the power voltage VDD. The second terminals of the transistors P 3 , P 5 are coupled to the first terminal of the PMOS transistor P 1 . The second terminals of the transistors P 4 , P 6 are coupled to the first terminal of the PMOS transistor P 2 . The control terminal of the transistor P 3 is coupled to the first data line DB. The control terminal of the transistor P 4 is coupled to the second data line D. The control terminals of the transistor P 5 , P 6 are coupled to the word line WL.

Also disclosed is a memory device that includes a first inverter, a second inverter, an accessing unit, and a switching unit. The second inverter is cross-coupled with the first inverter. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.

Also disclosed is a memory device that includes a first inverter, a second inverter, a first transistor, a second transistor, a first switching unit, a second switching unit, and a third switching unit. The second inverter is cross-coupled with the first inverter. The first transistor is coupled to a first bit line. The second transistor is coupled to a second bit line. The first switching unit is configured to discharge an output of the first inverter in response to a signal provided by the first bit line through the first transistor, and charge an output of the second inverter in response to a signal provided by the second bit line through the second transistor. The second switching unit is configured to disconnect a power from the first inverter and the second inverter according to signals provided by data lines. The third switching unit is configured to connect the second transistor to a reference voltage according to a signal provided by the output of the first inverter.

Also disclosed is a method that includes the operations below. During a writing operation, an output of a first inverter in a memory device is discharged according to a signal provided by a first word line, and an output of a second inverter in the memory device is charged according to a signal provided by a second word line, wherein the second inverter is cross-coupled with the first inverter. During the writing operation, a power is disconnected from the first inverter and the second inverter according to a signal provided by the first word line.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.