Inventor
Hung-Jen Liao
Inventor
Hsinchu, TW
Overview
Patents· 146 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores45%
H10BElectronic memory devices13%
H01LSemiconductor devices11%
H10DInorganic electric semiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H03KPulse technique5%
G06FElectric digital data processing4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
G01RMeasuring electric variables1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
10,878,890Operation assist circuit, memory device and operation assist method202010,854,282Memory read stability enhancement with short segmented bit line architecture202010,847,214Low voltage bit-cell202010,847,217Pre-charging bit lines through charge-sharing202010,839,894Memory computation circuit and method202010,832,765Variation tolerant read assist circuit for SRAM202010,803,928Low voltage memory device202010,783,955Memory circuit having shared word line202010,778,198Level shifter202010,770,131SRAM cell for interleaved wordline scheme202010,755,768Semiconductor device including distributed write driving arrangement and method of operating same202010,734,066Static random access memory with write assist circuit202010,714,181Memory cell202010,685,704Static random access memory circuit202010,685,686Power switch control for dual power supply202010,672,776Memory circuit having resistive device coupled with supply voltage line202010,651,832Level shifter202010,559,333Memory macro and method of operating the same202010,541,007Memory device with strap cells202010,529,415Write assist for a memory device and methods of forming the same202010,510,401Semiconductor memory device using shared data line for read/write operation201910,510,380Power switch control for dual power supply201910,510,403Memory read stability enhancement with short segmented bit line architecture201910,503,421Configurable memory storage system201910,431,295Static random access memory and method of controlling the same201910,411,019SRAM cell word line structure with reduced RC effects201910,410,715Pre-charging bit lines through charge-sharing201910,373,964Method of writing to memory circuit using resistive device201910,354,952Memory cell having multi-level word line201910,319,421Memory macro and method of operating the same201910,319,435Write assist for a memory device and methods of forming the same201910,304,500Power switch control for dual power supply201910,275,561Method for eliminating false paths of a circuit unit to be implemented using a system201910,276,579Layout design for manufacturing a memory cell201910,276,231SRAM cell for interleaved wordline scheme201910,268,787Hybrid timing analysis method and associated system and non-transitory computer readable medium201910,204,660Memory device with strap cells201910,176,864Static random access memory circuits201910,170,487Device having an inter-layer via (ILV), and method of making same201910,163,491Memory circuit having shared word line201810,153,038Memory read stability enhancement with short segmented bit line architecture201810,083,739Three-dimensional three-port bit cell and method of assembling same201810,062,419Digtial circuit structures201810,024,906Timing skew characterization apparatus and method20189,997,219Memory macro and method of operating the same20189,979,399Level shifter20189,959,916Dual rail memory, memory macro and associated hybrid power supply method20189,922,700'Memory read stability enhancement with short segmented bit line architecture'20189,922,701'Pre-charging bit lines through charge-sharing'20189,886,996'SRAM cell for interleaved wordline scheme'20189,865,605'Memory circuit having resistive device coupled with supply voltage line'20189,853,035Layout scheme and method for forming device cells in semiconductor devices20179,842,627'Memory device with strap cells'20179,837,130Digtial circuit structures to control leakage current20179,824,729'Memory macro and method of operating the same'20179,762,216'Level shifter circuit using boosting circuit'20179,741,429'Memory with write assist circuit'20179,704,565'Method of using a static random access memory'20179,685,224'Memory with bit line control'20179,685,223'Voltage controller'20179,666,253'Dual rail memory, memory macro and associated hybrid power supply method'20179,659,620'Memory device with self-boosted mechanism'20179,640,251'Multi-port memory cell'20179,607,683'Emulator for imulating an operation of a SRAM'20179,601,162'Memory devices with strap cells'20179,589,885'Device having multiple-layer pins in memory MUX1 layout'20179,552,873'Memory device'20179,536,598'Memory arrangement'20179,496,026'Memory device with stable writing and/or reading operation'20169,484,350'Semiconductor device having an inter-layer via (ILV), and method of making same'20169,449,667'Memory circuit having shared word line'20169,425,095'Distributed metal routing'20169,418,729'Multi-port memory cell'20169,412,742'Layout design for manufacturing a memory cell'20169,343,140'Boosted read write word line'20169,336,859'Memory array'20169,318,190'Memory device'20169,281,031'Method and apparatus for read assist to compensate for weak bit'20169,281,056'Static random access memory and method of using the same'20169,257,172'Multi-port memory cell'20169,208,854'Three dimensional dual-port bit cell and method of assembling same'20159,183,341'Pre-colored methodology of multiple patterning'20159,165,623'Memory arrangement'20159,142,275'Wordline tracking for boosted-wordline timing scheme'20159,135,971'Boosted read write word line'20159,129,956'Device having multiple-layer pins in memory MUX1 layout'20159,099,199'Memory cell and memory array'20159,093,176'Power line lowering for write assisted control scheme'20159,075,936'Pre-colored methodology of multiple patterning'20159,064,799'Method of forming edge devices for improved performance'20159,041,069'Distributed metal routing'20158,958,232'Method and apparatus for read assist to compensate for weak bit'20158,942,053'Generating and amplifying differential signals'20158,928,113'Layout scheme and method for forming device cells in semiconductor devices'20158,907,681'Timing skew characterization apparatus and method'20148,792,292'Providing row redundancy to solve vertical twin bit failures'20148,773,930'Built-in test circuit and method'20148,767,493'SRAM differential voltage sensing apparatus'20148,723,265'Semiconductor structure with dummy polysilicon lines'20148,713,491'Pre-colored methodology of multiple patterning'20148,693,265'Data inversion for dual-port memory'20148,675,439'Bit line voltage bias for low power memory design'20148,665,654'Memory edge cell'20148,610,236'Edge devices layout for improved performance'20138,601,411'Pre-colored methodology of multiple patterning'20138,576,655'Semiconductor memories'20138,559,251'Memory circuit and method of writing datum to memory circuit'20138,553,448'SRAM cells, memory circuits, systems, and fabrication methods thereof'20138,488,395'Keepers, integrated circuits, and systems thereof'20138,482,990'Memory edge cell'20138,455,354'Layouts of POLY cut openings overlapping active regions'20138,427,888'Word-line driver using level shifter at local control circuit'20138,406,075'Ultra-low leakage memory architecture'20138,406,028'Word line layout for semiconductor memory'20138,395,950'Memory device having a clock skew generator'20138,363,454'SRAM bit cell'20138,355,277'Biasing circuit and technique for SRAM data retention'20138,289,754'SRAM cells, memory circuits, systems, and fabrication methods thereof'20128,223,571'Generating and amplifying differential signals'20128,218,354'SRAM word-line coupling noise restriction'20128,111,542'8T low leakage SRAM cell'20128,077,517'Distributed VDC for SRAM memory'20117,952,911'SRAM cell array structure'20117,848,174'Memory word-line tracking scheme'20107,826,252'Read-preferred SRAM cell design'20107,808,812'Robust 8T SRAM cell'20107,701,755'Memory having improved power design'20107,639,551'Sense amplifiers operated under hamming distance methodology'20097,613,054'SRAM device with enhanced read/write operations'20097,577,052'Power switching circuit'20097,551,415'Repair circuitry with an enhanced ESD protection device'20097,535,788'Dynamic power control for expanding SRAM write margin'20097,505,345'Circuit and method for an SRAM with two phase word line pulse'20097,502,277'Word-line driver design for pseudo two-port memories'20097,468,903'Circuits for improving read and write margins in multi-port SRAMS'20087,462,894'Electrical fuse device with dummy cells for ESD protection'20087,460,391'Write VCCMIN improvement scheme'20087,436,696'Read-preferred SRAM cell design'20087,394,637'Sense amplifier with leakage compensation for electrical fuses'20087,313,050'Word-line driver for memory devices'20077,271,644'Multi-state electrical fuse'20077,215,587'Tracking circuit for a memory device'20077,190,626'Memory system with bit-line discharging mechanism'20077,137,079'Memory compiler with ultra low power feature and method of use'20065,995,433'Three-transistor type DRAM with a refresh circuit'19995,546,019'CMOS I/O circuit with 3.3 volt output and tolerance of 5 volt input'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (62)· patent assignee history
1996Based in Nun-Tou Hsien, TW· patent location history
1999Based in Tou Liu, TW· patent location history
2006–2020Based in Hsinchu, TW· patent location history
2007–2011Based in Hsin Chu, TW· patent location history
2008Based in Hsichu, TW· patent location history
2011–2015Patents assigned to LIAO HUNG-JEN (32)· patent assignee history
2011–2015Patents assigned to CHEN YEN-HUEI (17)· patent assignee history
2011–2015Patents assigned to CHOU SHAO-YU (9)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (83)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 83 | 2015–2020 |
| TAIWAN SEMICONDUCTOR MFG | 62 | 1996–2016 |
| LIAO HUNG-JENself | 32 | 2011–2015 |
| CHEN YEN-HUEI | 17 | 2011–2015 |
| CHOU SHAO-YU | 9 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 141 | 2006–2020 |
| Hsin Chu, TW | 2 | 2007–2011 |
| Hsichu, TW | 1 | 2008 |
| Tou Liu, TW | 1 | 1999 |
| Nun-Tou Hsien, TW | 1 | 1996 |