Memory cells having a heater electrode formed between a first storage material and a second storage material and methods of forming the same

The present disclosure relates generally to memory cells, and more particularly to memory cells having a heater electrode formed between a first storage material a second storage material, memory arrays, and methods of forming the same.

Memory devices are utilized as non-volatile memory for a wide range of electronic applications in need of high memory densities, high reliability, and data retention without power. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices.

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory, among others. Types of resistance variable memory include phase change random access memory (PCRAM) and resistive random access memory (RRAM), for instance.

Resistance variable memory devices can include a resistance variable material, e.g., a phase change material, for instance, which can be programmed into different resistance states to store data. The particular data stored in a resistance variable material cell can be read by sensing the cell's resistance e.g., by sensing current and/or voltage variations based on the resistance of the resistance variable material.

FIG. 1 illustrates a portion of a memory cell in accordance with a number of embodiments of the present disclosure.

FIG. 2 illustrates a portion of a memory cell in accordance with a number of embodiments of the present disclosure.

FIG. 3 illustrates a portion of a resistive memory array in accordance with a number of embodiments of the present disclosure.

FIG. 4 illustrates a portion of a three dimensional resistive memory array in accordance with a number of embodiments of the present disclosure.

Memory cells having a first storage material, a second storage material, and a heater electrode and methods of manufacturing the same are described herein. As an example, a memory cell can include a first storage material, a second storage material, and a heater electrode, where the heater electrode is formed between the first storage material the second storage material.

Previous memory cells have not utilized a heater electrode formed between a first storage material and a second storage material. Embodiments of the present disclosure can provide benefits such as reducing thermal disturb to adjacent memory cells and/or, providing for utilization of lower programming currents among others, as compared to previous memory cells not having a heater electrode formed between the first storage material and the second storage material.

Because the heater electrodes of memory cells according to the present disclosure are formed between the first storage material and the second storage material, memory cells according to the present disclosure can provide a more directed heating, e.g., heat can be provided more directly to areas associated with programming the storage material, as compared to previous memory cells not having a heater electrode formed between a first storage material and a second storage material. For instance, there may be greater thermal resistances, e.g., greater thermal isolation, associated with areas of the storage materials that phase change for programming the memory cell. For example, the areas associated with programming the storage materials, may be more thermally isolated from conductive lines, such as access lines and data/sense lines, than other elements of the memory cell and/or other portions of the storage materials. Providing the heater electrodes that are formed between the first storage material and the second storage material, as disclosed herein, can provide that lower energy, e.g., lower programming currents, may be utilized for programming memory cells according to the present disclosure, as compared to previous memory cells. Also, the lower programming energy can help to reduce programming disturb, e.g., thermal energy inadvertently provided to neighboring memory cells, among other benefits.

In the detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 108 may reference element “8” in FIG. 1 , and a similar element may be referenced as 208 in FIG. 2 . Also, as used herein, “a number of” a particular element and/or feature can refer to one or more of such elements and/or features.

FIG. 1 illustrates a portion of a memory cell 102 in accordance with a number of embodiments of the present disclosure. As illustrated in FIG. 1 , the memory cell 102 can include: a storage material 104 , e.g., a first storage material; a storage material 106 , e.g., a second material; a heater electrode 108 ; and a select device 109 . As illustrated in FIG. 1 , the select device 109 can include a select device material 110 , e.g., a first portion of the select device 109 , and a select device material 112 , e.g., a second portion of the select device 109 . The select device materials 110 , 112 can be operated, e.g., turned on/off, to select/deselect a memory cell in order to perform operations such as data programming, e.g., writing, and/or data sensing, e.g., reading operations. For instance, responsive to an applied voltage across the memory cell 102 that is less than a threshold voltage, the select device materials 110 , 112 can remain in an “off” state, e.g., an electrically nonconductive state. Alternatively, responsive to an applied voltage across the memory cell 102 that is greater than the threshold voltage, the select device materials 110 , 112 can be in an “on” state. Some embodiments of the present disclosure provide that the select device 109 can be a switch, e.g., a MOS transistor, a BJT, a diode, an ovonic threshold switch (OTS), among other types of switches. Some embodiments of the present disclosure provide that the select 109 can be a three terminal switch. The storage materials 104 , 106 can store a data state of the memory cell 102 . The memory cell 102 can include electrode materials 114 , 116 , 118 , 120 , and lamina materials 122 , 124 , 126 , 128 . As illustrated in FIG. 1 , components of the memory cell 102 , e.g., the first storage material 104 , the second storage material 106 , the heater electrode 108 , the first portion 110 of the select device 109 , and the second portion 112 of the select device 109 can be formed in series.

As illustrated in FIG. 1 , the select device material 110 can be formed on, e.g., subsequent to, an electrode material 114 . In the example illustrated in FIG. 1 , the select device material 110 is formed on, e.g., in contact with, the electrode material 114 . However, examples of the present disclosure are not so limited. For instance, a number of intervening materials, not shown in FIG. 1 , may separate a material formed on another material, such as the select device material 110 and the electrode material 114 , among others. The electrode material 114 may be formed on a conductive line, as discussed further herein.

The electrode material 114 can include materials such as Ti, Ta, W, Al, Cr, Zr, Nb, Mo, Hf, B, C, N, conductive nitrides of the aforementioned materials, e.g., TiN, TaN, WN, CN, etc., and/or combinations thereof. The electrode material 114 can have a thickness 130 in a range from about 8 nanometers (nm) to about 15 nm, for instance.

Embodiments of the present disclosure provide that the select device materials 110 , 112 do not store a data state of the memory cell 102 , e.g., in contrast to the storage materials 104 , 106 the select device materials 110 , 112 do not have different resistance values that are stable over time. For instance, the select device materials 110 , 112 can be in a perpetual amorphous state. The select device materials 110 , 112 can include As, Te, Ge, Si, S, and/or Se. Some specific examples of the select device materials 110 , 112 include AsTeGeSi, As 2 Te 3 Ge, and As 2 Se 3 Ge.

The select device material 110 can have a thickness 132 in a range from about 6 nm to about 20 nm, for instance. Some embodiments of the present disclosure provide that the select device material 104 can have a thickness 132 in a range from about 7.5 nm to about 15 nm.

As illustrated in FIG. 1 , the electrode material 116 can be formed on the select device material 110 . The electrode material 116 can be similar to the electrode material 114 , e.g., the electrode material 116 can include a number of materials as discussed with the electrode material 114 . Additionally, the electrode material 116 can have a thickness 134 in a range from about 8 nm to about 20 nm.

As illustrated in FIG. 1 , the lamina material 122 can be formed on the electrode material 116 . The lamina material 122 may be utilized to improve an electrical contact, e.g., of the storage materials 104 , 106 . The lamina material 122 can include materials such as W, TiN, CN, WsiN, and/or TiSiN, among others. The lamina material 122 can have a thickness 136 in a range from about 4 nm to about 15 nm.

Embodiments of the present disclosure provide that the memory cell 102 includes the storage materials 104 , 106 . Embodiments of the present disclosure provide that the storage materials 104 , 106 are programmable, e.g. the storage materials 104 , 106 may have a variable resistance. Embodiments of the present disclosure provide that the storage materials 104 , 106 can include a resistance variable material that can be programmed into different resistance states to store data. For example, a combined resistance of the storage materials 104 , 106 can determine a data state of the memory cell 102 .

The storage materials 104 , 106 can include, for example, one or more resistance variable materials such as a metal oxide material, such as alkaline metal oxides, e.g., Li 2 O, Na 2 O, K 2 O, Rb 2 O, Cs 2 O, BeO, MgO, CaO, SrO, and BaO, refractive metal oxides, e.g., NbO, NbO 2 , Nb 2 O 5 , MoO 2 , MoO 3 , Ta 2 O 5 , W 2 O 3 , WO 2 , WO 3 , ReO 2 , ReO 3 , and Re 2 O 7 , and binary metal oxides, e.g., Cu x O y , WO x , Nb 2 O 5 , Al 2 O 3 , Ta 2 O 5 , TiO x , ZrO x , Ni x O and Fe x O, among others. Other examples of resistance variable materials associated with the storage materials 104 , 106 of the memory cell 102 can include chalcogenides, binary metal oxides, colossal magnetoresistive materials such as Pr (1-x) Ca x MnO 3 (PCMO), La (1-x) CaxMnO 3 (LCMO), and Ba (1-x) Sr x TiO 3 , among others, and/or perovskite oxides such as doped or undoped SrTiO 3 , SrZrO 3 , and BaTiO 3 , and polymer materials such as Bengala Rose, AlQ 3 Ag, Cu-TCNQ, DDQ, TAPA, and Fluorescine-based polymers, among others. As such, the memory cell 102 can be a RRAM cell, a PCRAM cell, and/or a conductive bridging memory cell, among various other types of resistive memory cells. The storage materials 104 , 106 can include materials such as In, Ge, Sb, Te, Si, 0 , N, and/or combinations thereof. Some specific examples, e.g., chalcogenides, of the storage material 108 include Ge 2 Sb 2 Te 5 , Ge 1 Sb 2 Te 4 , Ge 1 Sb 4 Te 7 , Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, Ge—Te—Sn—Ni, Ge—Te—Sn—Pd, and Ge—Te—Sn—Pt. Embodiments of the present disclosure are not limited to a particular type of resistance variable material.

As illustrated in FIG. 1 , the storage material 104 can be formed on the lamina material 122 . The storage material 104 can have a thickness 138 in a range from 10 nm to 50 nm. Some embodiments of the present disclosure provide that the storage material 104 can have a thickness 138 in a range from 15 nm to 35 nm.

As illustrated in FIG. 1 , a lamina material 124 can be formed on the storage material 104 . The lamina material 124 can be similar to the lamina material 122 , e.g., the lamina material 124 can include a number of materials as discussed with the lamina material 122 . Additionally, the lamina material 124 can have a thickness 140 in a range from 8 nm to 20 nm.

As illustrated in FIG. 1 , a heater electrode 108 can be formed on the lamina material 124 . The heater electrode 108 may be utilized as a heater that can heat-up, e.g., by a Joule effect, to provide energy and/or increased temperature to the adjacent storage materials 104 , 106 . The heater electrode 108 can include materials such as W, Si, N, B, Ta, Sn, Ti, 0 , and C. Some specific examples of the heater electrode material 108 include WSiN, WSiC, TiSiN, and SiC. Embodiments of the present disclosure provide that the heater electrode 108 can have a resistivity from 1 milliohm-centimeter to 500 milliohm-centimeter. The heater electrode 108 can have a thickness 142 in a range from 6 nm to 35 nm.

As illustrated in FIG. 1 , the lamina material 126 can be formed on the heater electrode 108 . The lamina material 126 can be similar to the lamina material 122 , e.g., the lamina material 126 can include a number of materials as discussed with the lamina material 122 . Additionally, the lamina material 126 can have a thickness 144 in a range from 8 nm to 20 nm.

As illustrated in FIG. 1 , the storage material 106 can be formed on the lamina material 126 . The storage material 106 can have a thickness 146 in a range from 10 nm to 50 nm. Some embodiments of the present disclosure provide that the storage material 106 can have a thickness 146 in a range from 15 nm to 35 nm. Embodiments of the present disclosure provide that the heater electrode material 108 is formed between the storage material 104 and the storage material 106 . Forming the heater electrode 108 between the storage material 104 and the storage material 106 can help to increase a local temperature in particular volumes of the storage material 104 and the storage material 106 , e.g., volumes near to the heater electrode 108 .

As illustrated in FIG. 1 , the lamina material 128 can be formed on the storage material 106 . The lamina material 128 can be similar to the lamina material 122 , e.g., the lamina material 128 can include a number of materials as discussed with the lamina material 122 . Additionally, the lamina material 128 can have a thickness 148 in a range from 8 nm to 20 nm.

As illustrated in FIG. 1 , the electrode material 118 can be formed on the lamina material 128 . The electrode material 118 can be similar to the electrode material 114 , e.g., the electrode material 118 can include a number of materials as discussed with the electrode material 114 . Additionally, the electrode material 118 can have a thickness 150 in a range from 8 nm to 20 nm.

As illustrated in FIG. 1 , the select device material 112 can be formed on the electrode material 118 . The select device material 112 can have a thickness 152 in a range from 7.5 nm to 15 nm.

As illustrated in FIG. 1 , the electrode material 120 can be formed on the electrode material 118 . The electrode material 120 can be similar to the electrode material 114 , e.g., the electrode material 120 can include a number of materials as discussed with the electrode material 114 . Additionally, the electrode material 120 can have a thickness 154 in a range from 8 nm to 20 nm.

Some embodiments of the present disclosure provide that the memory cell 102 is symmetric about the heater electrode 108 . For instance, the memory cell 102 can include the electrode material 114 , the select device material 110 , the electrode material 116 , the lamina material 122 , the storage material 104 , and the lamina material 124 and, transverse the heater electrode 108 , the memory cell 102 can include the lamina material 126 , the storage material 106 , the lamina material 128 , the electrode material 118 , the select device material 112 and the electrode material 120 . In some embodiments, at least on pair of symmetrically corresponding components of the memory cell 102 located on opposite sides of the heater electrode 108 have equal thicknesses. For instance, the thickness 132 of the select device material 110 is equal to the thickness 152 of the select device material 112 , and the thickness 138 of the storage material 104 is equal to the thickness 146 of the storage material 106 , and so forth.

Additionally, the same material or materials can be used to form symmetrically corresponding components of the memory cell 102 located on opposite sides of the heater electrode 108 . For instance, the same material or materials can be used to form both the select device material 110 and the select device material 112 , and the same material or materials can be used to form both the storage material 104 and the storage material 106 , and so forth. For example, some embodiments of the present disclosure provide that the select device material 110 comprises a first material and the select device material 112 comprises a second material that is a same material as the first material.

Some embodiments of the present disclosure provide that the memory cell 102 is symmetric about the heater electrode 108 and can have a symmetric thermal profile. For instance, the symmetry can provide that temperature hot spots for a phase change of the storage materials 104 , 106 are substantially equally thermally isolated from an access line and a data/sense line, which are discussed further herein.

Some embodiments of the present disclosure provide that the memory cell 102 is asymmetric about the heater electrode 108 . Being asymmetric about the heater electrode 108 , a number of corresponding components of the memory cell 102 located on opposite sides of the heater electrode 108 may have different thicknesses. For instance, the thickness 132 of the select device material 110 may be different than, e.g., greater than or less than, the thickness 152 of the select device material 112 , and/or the thickness 138 of the storage material 104 may be different than the thickness 146 of the storage material 106 , and so forth.

Additionally, being asymmetric about the heater electrode 108 , a different material or materials can be used to form used to form a number of corresponding components of the memory cell 102 located on opposite sides of the heater electrode 108 . For example, some embodiments of the present disclosure provide that the select device material 110 comprises a first material and the select device material 112 comprises a second material that is a different material as the first material, and so forth.

FIG. 2 illustrates a portion of a memory cell 202 in accordance with a number of embodiments of the present disclosure. As mentioned, some embodiments of the present disclosure provide that the memory cell 202 is asymmetric about the heater electrode 208 . As illustrated in FIG. 2 , the memory cell 202 is asymmetric about the heater electrode material 208 ; the select device 209 includes the select device material 210 and does not include a corresponding select device material located on opposite sides of the heater electrode 208 . For some applications, forming a memory cell 202 that is asymmetric about the heater electrode 208 may reduce a number of processing steps and/or processing complexity, as compared to a memory cell that is symmetric about the heater electrode material, for instance. As illustrated in FIG. 2 , components of the memory cell 202 , e.g., the first storage material 204 , the second storage material 206 , the heater electrode 208 , and the select device 209 can be formed in series.

As mentioned, the select device 209 includes the select device material 210 and does not include a corresponding select device material located on opposite sides of the heater electrode 208 . Some embodiments of the present disclosure provide that the select device 209 can be a switch, e.g., a MOS transistor, a BJT, a diode, an ovonic threshold switch (OTS), among other types of switches. Some embodiments of the present disclosure provide that the select device 209 can be a three terminal switch.

The memory cells according to the present disclosure can be formed using various processing techniques such as atomic material deposition (AMD), e.g., atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), supercritical fluid deposition (SFD), patterning, etching, filling, chemical mechanical planarization (CMP), combinations thereof, and/or other suitable processes. In accordance with a number of embodiments of the present disclosure, materials may be grown in situ.

FIG. 3 illustrates a portion of a memory array 360 in accordance with a number of embodiments of the present disclosure. The array 360 can be a cross-point array, which may also be referred to as a crossbar array.

The array 360 can include a number memory cells 302 , where each memory cell 302 is located at a respective intersection of a first plurality of conductive lines, e.g., access lines, 362 - 1 , 362 - 2 , . . . , 362 -N, which may be referred to herein as word lines, and a second plurality of conductive lines, e.g., data/sense lines, 364 - 1 , 364 - 2 , . . . , 364 -M, which may be referred to herein as bit lines. The designators N and M can have various values. Embodiments are not limited to a particular number of word lines and/or bit lines. As illustrated, the access lines 362 - 1 , 362 - 2 , . . . , 362 -N are substantially parallel to each other and are substantially orthogonal to the data/sense lines 364 - 1 , 364 - 2 , . . . , 364 -M, which are substantially parallel to each other; however, embodiments are not so limited. As illustrated in FIG. 3 , the array 360 can be a two dimensional array. For example, the memory cells 302 of the array 360 can be arranged between the access lines, 362 - 1 , 362 - 2 , . . . , 362 -N and the data/sense lines, 364 - 1 , 364 - 2 , . . . , 364 -M in a single tier.

As used herein, the term “substantially” intends that the modified characteristic needs not be absolute, but is close enough so as to achieve the advantages of the characteristic. For example, “substantially parallel” is not limited to absolute parallelism, and can include orientations that are at least closer to a parallel orientation than a perpendicular orientation. Similarly, “substantially orthogonal” is not limited to absolute orthogonalism, and can include orientations that are at least closer to a perpendicular orientation than a parallel orientation. The conductive lines can include conductive material, e.g., a metal material. Examples of the conductive material include, but are not limited to, tungsten, copper, titanium, aluminum, and/or combinations thereof, among other conductive materials.

In operation, a selected memory cell 302 can be programmed by applying a voltage, e.g., a write voltage, across the selected memory cell 302 via a selected access line 362 - 1 , 362 - 2 , . . . , 362 -N and a selected data/sense line 364 - 1 , 364 - 2 , . . . , 364 -M. The width and/or magnitude of voltage pulses across the selected memory cell 302 can be adjusted, e.g., varied, in order to program the selected memory cell 302 to particular data states, e.g., by adjusting a resistance level of the storage materials discussed herein, e.g., by a phase change to the storage materials 104 / 106 , 204 / 206 . A sensing, e.g., read, operation can be used to determine the data state of a memory cell 302 by a sensing current, for example, on a data/sense line 364 - 1 , 364 - 2 , . . . , 364 -M corresponding to the memory cell 302 responsive to a particular voltage applied to a selected access line to which the memory cell 302 is coupled. Sensing operations can also include biasing unselected access lines 362 - 1 , 362 - 2 , . . . , 362 -N and/or unselected data/sense lines 364 - 1 , 364 - 2 , . . . , 364 -M at particular voltages in order to sense the data state of the selected memory cell 302 .

FIG. 4 illustrates a portion of a three dimensional memory array 470 in accordance with a number of embodiments of the present disclosure. As illustrated in FIG. 4 , the array 470 includes a plurality memory cells 402 - 1 , 402 - 2 , 402 - 3 , 402 - 4 , 402 - 5 , 402 - 6 arranged into multiple tiers, e.g., tier 472 and tier 474 , which may also be referred to as levels. While FIG. 4 illustrates two tiers, embodiments of the present disclosure are not so limited; the array 470 can include varying numbers of tiers for different applications. In one or more embodiments, the processes of forming a memory cell and/or memory cell array can be repeated a number of times to create a number of tiers.

Each tier, e.g., tiers 472 , 474 , of the array 470 the memory cells 402 can be arranged in a cross point architecture where the memory cells 402 of adjacent tiers share a plurality of conductive lines, e.g., word lines or bit lines. For example, as illustrated in FIG. 4 , the memory cells 402 - 1 , 402 - 2 , 402 - 3 of tier 472 share the word line 462 with the memory cells of 402 - 4 , 402 - 5 , 402 - 6 of tier 474 . Similarly, other cells of tier 472 would share other word lines with other cells of tier 474 . Embodiments of the present disclosure are not limited to memory cells 402 of adjacent tiers sharing a plurality of word lines. For instance, some embodiments of the present disclosure provide that memory cells 402 of adjacent tiers share a plurality of bit lines. As mentioned, some embodiments of the present disclosure provide that the cells, e.g., cells 402 - 1 , 402 - 2 , 402 - 3 of tier 472 and cells of 402 - 4 , 402 - 5 , 402 - 6 of tier 474 can be symmetric. This cell symmetry can provide that cells of adjacent tiers, e.g., tiers 472 and 474 , have similar properties, e.g., the cells are indistinguishable from one another. Advantageously, this cell symmetry can provide improved multiple tier arrays, as compared to previous arrays.

While the memory cells 402 - 1 , 402 - 2 , 402 - 3 of tier 472 share the word line 462 with the memory cells of 402 - 4 , 402 - 5 , 402 - 6 of tier 474 , each of the memory cells 402 - 1 , 402 - 2 , 402 - 3 , 402 - 4 , 402 - 5 , 402 - 6 is associated with a respective bit line 464 . As shown in FIG. 4 , memory cells 402 - 1 , 402 - 2 , 402 - 3 , 402 - 4 , 402 - 5 , 402 - 6 are respectively associated with bit lines 464 - 1 , 464 - 2 , 464 - 3 , 464 - 4 , 464 - 5 , 464 - 6 .

As discussed, some examples of the present disclosure provide that the cells, e.g. cells 402 - 1 , 402 - 2 , 402 - 3 , 402 - 4 , 402 - 5 , 402 - 6 , are symmetric about respective heater electrodes 408 . Also, as discussed, some examples of the present disclosure provide that the cells, e.g., cells 402 - 1 , 402 - 2 , 402 - 3 , 402 - 4 , 402 - 5 , 402 - 6 , are asymmetric about respective heater electrodes 408 .

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.