Inventor

Innocenzo Tortorelli

Inventor
Cernusco Sul Naviglio, IT

Overview

85→
Patents
2013–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 85 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores25%
H10NElectric solid-state devices not otherwise provided for23%
H01LSemiconductor devices20%
H10BElectronic memory devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G06FElectric digital data processing2%
H10DInorganic electric semiconductor devices2%
G06NComputing arrangements based on specific computational models1%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
11,120,870Mixed cross point memory202111,114,159Dedicated read voltages for data structures202111,114,613Cross-point memory and methods for forming of the same202111,094,879Structures incorporating and methods of forming metal lines including carbon202111,094,377Multi-level self-selecting memory device202111,074,971Apparatuses and methods including memory and operation of same202111,062,767Techniques for programming neural memory unit using cell conditioning202111,037,613Implementations to store fuse data in memory devices202111,031,553Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references202111,024,372Segregation-based memory202111,018,300Self-aligned memory decks in cross-point memory arrays202110,985,212Multi-component cell architectures for a memory device202110,976,936Sensing operations in memory202110,937,829Three dimensional memory arrays202110,921,989Sensing operations in memory202110,896,932Three dimensional memory array202110,892,406Phase change memory structures and devices202110,884,640Set technique for phase change memory202110,861,539Neural network memory202010,854,674Cross-point memory and methods for fabrication of same202010,854,813Dopant-modulated etching for memory devices202010,803,939Techniques for programming a memory cell202010,803,934Mixed cross point memory202010,777,291Drift mitigation with embedded refresh202010,777,275Reset refresh techniques for self-selecting memory202010,777,266Mixed cross point memory202010,707,271Memory cells having resistors and formation of the same202010,680,170Cross-point memory and methods for forming of the same202010,672,833Semiconductor devices including a passive material between memory cells and conductive access lines, and related electronic devices202010,665,298Techniques to access a self-selecting memory device202010,658,035Apparatuses and methods of reading memory cells202010,658,034Dedicated read voltages for data structures202010,600,481Apparatuses including memory cells and methods of operation of same202010,600,456Program operations in memory202010,580,980Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references202010,559,353Weight storage using memory device202010,546,632Multi-level self-selecting memory device202010,510,957Self-aligned memory decks in cross-point memory arrays201910,497,753Three dimensional memory array201910,497,863Method, system, and device for L-shaped memory component201910,461,125Three dimensional memory arrays201910,446,226Apparatuses including multi-level memory cells and methods of operation of same201910,424,374Programming enhancement in self-selecting memory201910,418,102Apparatuses and methods including memory and operation of same201910,381,077Apparatuses and methods including memory and operation of same201910,283,703Cross-point memory and methods for forming of the same201910,283,198Apparatuses and methods of reading memory cells based on response to a test pulse201910,269,442Drift mitigation with embedded refresh201910,263,039Memory cells having resistors and formation of the same201910,255,975Apparatuses and methods of reading memory cells201910,248,351Set technique for phase change memory201910,186,659Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references201910,163,982Multi-deck memory device with inverted deck201810,163,506Apparatuses including memory cells and methods of operation of same201810,157,650Program operations in memory201810,157,667Mixed cross point memory201810,157,670Apparatuses including memory cells and methods of operation of same201810,153,428Structures incorporating and methods of forming metal lines including carbon201810,134,470Apparatuses and methods including memory and operation of same201810,102,891Double-polarity memory read201810,096,655Three dimensional memory array201810,062,433Apparatuses and methods of reading memory cells20189,876,168Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references20189,806,129'Cross-point memory and methods for fabrication of same'20179,799,381'Double-polarity memory read'20179,768,378'Cross-point memory and methods for fabrication of same'20179,705,080'Forming self-aligned conductive lines for resistive random access memories'20179,698,345'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references'20179,672,908'Apparatuses and methods of reading memory cells based on response to a test pulse'20179,645,102'Material test structure'20179,634,245'Structures incorporating and methods of forming metal lines including carbon'20179,570,167'Apparatuses and methods of reading memory cells'20179,520,555'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact'20169,444,043'Method, system and device for phase change memory with shunt'20169,406,881'Memory cells having a heater electrode formed between a first storage material and a second storage material and methods of forming the same'20169,275,730'Apparatuses and methods of reading memory cells based on response to a test pulse'20169,196,530'Forming self-aligned conductive lines for resistive random access memories'20158,988,926'Method, system and device for phase change memory with shunt'20158,976,570'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact'20158,945,403'Material test structure'20158,837,201'Programming an array of resistance random access memory cells using unipolar pulses'20148,680,499'Memory cells'20148,599,599'Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact'20138,467,226'Programming an array of resistance random access memory cells using unipolar pulses'20138,410,527'Electrical fuse device based on a phase-change memory element and corresponding programming method'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2021Patents assigned to MICRON TECHNOLOGY INC (70)· patent assignee history
2013–2015Patents assigned to TORTORELLI INNOCENZO (6)· patent assignee history
2013–2015Patents assigned to PELLIZZER FABIO (4)· patent assignee history
2013–2021Based in Moncalieri, IT· patent location history
2015–2021Based in Cernusco Sul Naviglio, IT· patent location history
2016–2021Patents assigned to OVONYX MEMORY TECH LLC (6)· patent assignee history
2017–2021Patents assigned to INTEL CORP (7)· patent assignee history
2019–2021Based in Santa Clara, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC702013–2021
INTEL CORP72017–2021
OVONYX MEMORY TECH LLC62016–2021
TORTORELLI INNOCENZOself62013–2015
PELLIZZER FABIO42013–2015
Locations
LocationPatentsSpan
Cernusco Sul Naviglio, IT692015–2021
Moncalieri, IT142013–2021
Santa Clara, California, US22019–2021