Receiving circuit

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-112889, filed on May 30, 2014, the entire contents of which are incorporated herein by reference.

The embodiments discussed herein are related to a receiving circuit.

With improvements in the performances of information processing apparatuses such as devices for communication backbones and servers, the data rates of transmission and reception of signals in and out of the devices are desired to be increased. For a receiving circuit, a so-called clock-and-data recovery (CDR) is desired, which determines transmitted data at an appropriate timing and recovers data and a clock. The clock-and-data recovery is achieved by detecting a phase difference between input data and a clock (sampling clock) that is used for sampling data, and adjusting the phase of the sampling clock based on the phase difference thus detected.

For example, a clock-and-data recovery circuit (CDR circuit) of a voltage controlled oscillator (VCO) type (or a phase locked loop (PLL) type) is known, which adjusts the phase of a sampling clock by adjusting a control voltage of a voltage controlled oscillator. As the voltage controlled oscillator, an LC voltage controlled oscillator is known, which is capable of high-frequency oscillations with a low noise (see, for example, International Publication Pamphlet No. WO2009/096413 and Japanese Laid-open Patent Publication No. 2004-356701). The LC voltage controlled oscillator generates a clock signal having an oscillation frequency according to an inductor and a capacitor. In addition, a communication semiconductor integrated circuit including a plurality of LC voltage controlled oscillators in a PLL circuit has been proposed (see, for example, Japanese Laid-open Patent Publication No. 2010-63054).

FIG. 14 illustrates a configuration example of a receiving circuit configured with two lanes through which to receive data in parallel. The receiving circuit illustrated in FIG. 14 includes: a first CDR circuit (CDR 1 ) 1400 - 1 configured to receive input data DI 1 and output output data DO 1 ; and a second CDR circuit (CDR 2 ) 1400 - 2 configured to receive input data DI 2 and output output data DO 2 . Since the first CDR circuit 1400 - 1 and the second CDR circuit 1400 - 2 are configured and operate in the same manner, the first CDR circuit 1400 - 1 will be described as an example.

The first CDR circuit 1400 - 1 determines whether the input data DI 1 is “0” or “1” by use of a comparator circuit (determination circuit) 1401 , and outputs the result of the determination as output data DO 1 . The comparator circuit (determination circuit) 1401 uses an output clock CK 1 of an LC voltage controlled oscillator (LC VCO) 1405 as a sampling clock, and makes the determination on the input data DI 1 at the timing of the clock CK 1 .

A phase-frequency detector circuit (PFD) 1402 detects a phase difference and a frequency difference between the input data DI 1 and the clock CK 1 , and outputs an up signal UP 1 and a down signal DN 1 in accordance with the result of the detection.

A charge pump circuit (CP) 1403 and a loop filter (LPF) 1404 generate a control voltage VCOC 1 by performing addition or subtraction of a current (injection or extraction of electric charges) in accordance with the up signal UP 1 and the down signal DN 1 outputted from the phase-frequency detector circuit 1402 . The LC voltage controlled oscillator 1405 generates a clock having an oscillation frequency according to the control voltage VCOC 1 , and outputs the clock as an output clock CK 1 . With the above-described operation, the output clock CK 1 of the LC voltage controlled oscillator 1405 is locked to the input data DI 1 , so that the function of the clock-and-data recovery is achieved.

A receiving circuit having a plurality of lanes, which receives a plurality of pieces of data and outputs a plurality of pieces of data in parallel through a plurality of CDR circuits, is generally implemented by arranging circuits of the respective lanes in parallel. If LC voltage controlled oscillators included in the CDR circuits of the respective lanes are arranged adjacent to each other, interference occurs between the LC voltage controlled oscillators due to mutual coupling of inductors of the LC voltage controlled oscillators. This interference causes injection locking, by which the phases of the clocks of the LC voltage controlled oscillators which are oscillating at nearby frequencies are shifted such that the outputs of the LC voltage controlled oscillators have the same phase and frequency.

When interference occurs between the LC voltage controlled oscillators in the loops of the CDR circuits, the phases of the LC voltage controlled oscillators are shifted in directions that make the phase difference between their output clocks smaller as indicated in FIG. 15 , thus causing a phase error. A large interference between the LC voltage controlled oscillators relative to the loop gain of the CDR circuit causes a large phase error, leading to deterioration in the characteristics of the CDR circuit. In FIG. 15 , a clock CK 1 indicates a clock to be locked to input data DI 1 while a clock CK 2 indicates a clock to be locked to input data DI 2 . In addition, regarding the clocks CK 1 , CK 2 , dotted lines indicate an example of a case where there is no interference between the LC voltage controlled oscillators while solid lines indicate an example of a case where the phases are shifted by interference between the LC voltage controlled oscillators.

FIGS. 16A to 16C indicate influences of interference between LC voltage controlled oscillators. Each of the diagrams indicates a relation between an input phase difference θin_d/2π (corresponding to the phase difference between the input data DI 1 and DI 2 in the example illustrated in FIG. 14 ) and a clock phase difference θd/2π (corresponding to the phase difference between the clocks CK 1 and CK 2 in the example illustrated in FIG. 14 ). Each CDR circuit is controlled such that the clock is conformed to the phase of the input data. Accordingly, the input phase difference and the clock phase difference are ideally converged and equalized.

In a case where there is no interference between the LC voltage controlled oscillators included in the CDR circuits, the input phase difference and the clock phase difference are equalized as indicated in FIG. 16A . However, in a case where there is interference, a convergence phase error occurs as indicated in FIGS. 16B and 16C . Moreover, even in the case where there is interference between the LC voltage controlled oscillators included in the CDR circuits, no convergence phase error occurs when the input phase difference takes 0 or π, while a convergence phase error occurs when the input phase difference takes another value, as indicated in FIGS. 16B and 16C . In other words, this phase error varies depending on the magnitude of the input phase difference (the phase difference between input data) and on the magnitude of the interference between LC voltage controlled oscillators.

Increasing the loop gains of the CDR circuits allows for reducing the influence of interference between the LC voltage controlled oscillators, but changes the characteristics of the CDR circuits. In addition, since the loop gain of a CDR circuit is generally defined in its standards and has an optimum magnitude fixed in view of its performance, it is difficult to simply increase the loop gains of the CDR circuits.

For these reason, the LC voltage controlled oscillators (CDR circuits) are desirably implemented at a sufficient distance to reduce the influence of the interference, and are thus difficult to implement at a high density.

According to an aspect of the invention, a receiving circuit includes: clock-and-data-recovery-circuits arranged in parallel, each of the clock-and-data-recovery-circuits including an LC-voltage-controlled-oscillator configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, each clock-and-data-recovery-circuit being configured to sample a piece of input data with an output clock of the LC-voltage-controlled-oscillator and adjust the oscillation frequency of the LC-voltage-controlled-oscillator in accordance with a phase difference and a frequency difference between the piece of input data and the output clock of the LC-voltage-controlled-oscillator, thereby recovering data and a clock based on the piece of input data; and a gain-adjustment-circuit configured to adjust ratios of gains of up and down of the oscillation frequency of the LC-voltage-controlled-oscillator in a loop in each of the clock-and-data-recovery-circuits arranged adjacent to each other, in accordance with a phase difference between the pieces of input data and a phase difference between the output clocks of the respective clock-and-data-recovery-circuits.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

FIGS. 1A and 1B are diagrams for explaining a receiving circuit in a first embodiment.

FIG. 2 is a diagram illustrating a configuration example of the receiving circuit in the first embodiment.

FIGS. 3A and 3B are diagrams illustrating an example of a phase detector circuit in the first embodiment.

FIG. 4 is a diagram illustrating a configuration example of a charge pump circuit in the first embodiment.

FIG. 5 is a diagram illustrating a configuration example of a loop filter in the first embodiment.

FIG. 6 is a diagram illustrating a configuration example of an LC voltage controlled oscillator in the first embodiment.

FIGS. 7A and 7B are diagrams illustrating a configuration example of a phase difference calculation circuit in the first embodiment.

FIGS. 8A and 8B are diagrams illustrating another configuration example of the phase difference calculation circuit in the first embodiment.

FIG. 9 is a diagram illustrating a configuration example of a receiving circuit in a second embodiment.

FIG. 10 is a diagram illustrating a configuration example of a phase interpolation circuit in the second embodiment.

FIG. 11 is a diagram illustrating a configuration example of a receiving circuit in a third embodiment.

FIG. 12 is a diagram illustrating a configuration example of a receiving circuit in a fourth embodiment.

FIG. 13 is a diagram illustrating a configuration example of a digital filter in the fourth embodiment.

FIG. 14 is a diagram illustrating a receiving circuit having a plurality of CDR circuits arranged in parallel.

FIG. 15 is a diagram for explaining interference between LC voltage controlled oscillators.

FIGS. 16A to 16C are diagrams indicating influences of interference between LC voltage controlled oscillators.

Hereinafter, embodiments will be described with reference to the drawings.

In a receiving circuit having a plurality of lanes in which clock-and-data recovery circuits (CDR circuits) each having an LC voltage controlled oscillator are respectively arranged, a convergence phase error in the CDR circuits varies, depending on a phase difference between input data and a phase difference between clocks in adjacent lanes, due to interference between the LC voltage controlled oscillators. In view of this, in the embodiments described below, a phase difference between input data and a phase difference between clocks in adjacent lanes are detected, and ratios of the gains of up (UP) and down (DN) in the loop of each CDR circuit, which increase and decrease the oscillation frequency of the LC voltage controlled oscillator, are adjusted in accordance with the detected phase differences. In this way, the convergence phase error is corrected without changing the loop gain of the CDR circuit.

First Embodiment

A first embodiment will be described.

FIG. 1A is a diagram illustrating a configuration example of a receiving circuit in the first embodiment. FIG. 1A illustrates, as an example, a receiving circuit configured with two lanes through which two CDR circuits receive data and output data in parallel. The receiving circuit illustrated in FIG. 1A includes: a first CDR circuit (CDR 1 ) 100 - 1 configured to receive input data DI 1 and output output data DO 1 ; a second CDR circuit (CDR 2 ) 100 - 2 configured to receive input data DI 2 and output output data DO 2 ; phase detector circuits (PDs) 111 , 112 ; and a phase difference calculation circuit 113 . The phase detector circuits 111 , 112 and the phase difference calculation circuit 113 constitute an example of a gain adjustment circuit.

Each of the CDR circuits 100 includes an LC voltage controlled oscillator. The CDR circuit 100 samples the input data by use of an output clock of the LC voltage controlled oscillator, and adjusts the oscillation frequency of the LC voltage controlled oscillator in accordance with a phase difference and a frequency difference between the input data and the output clock of the LC voltage controlled oscillator, thereby recovering data and a clock based on the input data.

Each of the CDR circuits 100 - i (i is an index and is 1 or 2 in the example illustrated in FIG. 1A ) includes a comparator circuit (determination circuit) 101 , a phase-frequency detector circuit (PFD) 102 , a charge pump circuit (CP) 103 , a loop filter (LPF) 104 , and an LC voltage controlled oscillator (LC VCO) 105 . The comparator circuit 101 uses an output clock CKi of the LC voltage controlled oscillator 105 as a sampling clock, determines whether the input data DIi is “0” or “1” at the timing of the clock CKi, and outputs the result of the determination as output data DOi.

The phase-frequency detector circuit 102 detects the phase difference and the frequency difference between the input data DIi and the clock CKi, and outputs an up signal UPi or a down signal DNi, which provides instruction to increase or decrease a control voltage VCOCi, in accordance with the result of the detection. The charge pump circuit 103 and the loop filter 104 generate the control voltage VCOCi by performing addition or subtraction of a current (injection or extraction of electric charges) in accordance with the up signal UPi and the down signal DNi, which are outputted from the phase-frequency detector circuit 102 , and an output CPADi of the phase difference calculation circuit 113 .

The LC voltage controlled oscillator 105 generates a clock having an oscillation frequency according to an inductor (L) and a capacitor (C). The LC voltage controlled oscillator 105 includes a variable capacitor, for example. The oscillation frequency of the LC voltage controlled oscillator 105 is controlled by adjusting the capacitance value of the variable capacitor with the control voltage VCOCi, so that the LC voltage controlled oscillator 105 outputs, as the output clock CKi, a clock having a frequency according to the supplied control voltage VCOCi.

The phase detector circuit 111 detects the phase difference between the input data DI 1 , which is inputted to the CDR circuit 100 - 1 , and the input data DI 2 , which is inputted to the CDR circuit 100 - 2 , and outputs an up signal UPD or a down signal DND in accordance with the result of the detection. In short, the phase detector circuit 111 outputs the up signal UPD or the down signal DND in accordance with the phase difference between the input data DI 1 , DI 2 in the adjacent lanes.

The phase detector circuit 112 detects the phase difference between the clock CK 1 , which is outputted from the LC voltage controlled oscillator 105 of the CDR circuit 100 - 1 , and the clock CK 2 , which is outputted from the LC voltage controlled oscillator 105 of the CDR circuit 100 - 2 , and outputs an up signal UPCK and a down signal DNCK in accordance with the result of the detection. In short, the phase detector circuit 112 outputs the up signal UPCK or the down signal DNCK in accordance with the phase difference between the clocks CK 1 , CK 2 in the adjacent lanes.

The phase difference calculation circuit 113 generates outputs CPAD 1 , CPAD 2 according to the difference between the phase difference between the input data DI 1 , DI 2 and the phase difference between the clocks CK 1 , CK 2 , based on the up signal UPD and the down signal DND, which are outputted from the phase detector circuit 111 , as well as the up signal UPCK and the down signal DNCK, which are outputted from the phase detector circuit 112 . The output CPAD 1 of the phase difference calculation circuit 113 is supplied to the charge pump circuit 103 of the CDR circuit 100 - 1 , and the ratios of the gains of up (UP) and down (DN) in the loop of the CDR circuit 100 - 1 are adjusted based on the output CPAD 1 . On the other hand, the output CPAD 2 of the phase difference calculation circuit 113 is supplied to the charge pump circuit 103 of the CDR circuit 100 - 2 , and the ratios of the gains of up (UP) and down (DN) in the loop of the CDR circuit 100 - 2 are adjusted based on the output CPAD 2 .

FIG. 1B is a diagram indicating a gain relative to an input phase difference in the loop of the CDR circuit. In FIG. 1B , the horizontal axis indicates the phase difference between the input data and the clock, and the vertical axis indicates the normalized gain. When there is no interference between the LC voltage controlled oscillators, the characteristic of the gain is as indicated by a long dashed dotted line 121 in FIG. 1B , and is converged (the gain becomes zero) at a portion where there is no phase difference between the input data and the clock.

However, if there is interference between the LC voltage controlled oscillators, the influence of the interference increases the gain in a direction that makes the clock phase difference between the adjacent lanes smaller. As a result, the characteristic of the gain is changed (shifted) as indicated by a solid line 122 in FIG. 1B , for example. Without gain adjustment or the like, the characteristic is converged at a point where the gain becomes zero. For this reason, if the characteristic of the gain is changed as indicated by the solid line 122 , a convergence phase error occurs.

In view of this, in the receiving circuit according to the first embodiment, the gains of the up signal (UP) and the down signal (DN) in the charge pump circuit 103 of the CDR circuit 100 are adjusted by use of the outputs CPAD 1 , CPAD 2 of the phase difference calculation circuit 113 to adjust the ratios of the gains of up and down in the loop of the CDR circuit 100 . In this way, the ratios of the gains of up and down in the loop of the CDR circuit are adjusted to be converged with the gain indicated by a dashed line in FIG. 1B , for example, to cancel the influence of the interference between the LC voltage controlled oscillators 105 . In this way, the convergence phase error can be reduced.

FIG. 2 is a diagram illustrating, in more detail, a configuration example of the receiving circuit in the first embodiment illustrated in FIG. 1A . The receiving circuit illustrated in FIG. 2 includes: two CDR circuits 100 - i each configured to receive input data DIi and output output data DOi; phase detector circuits 201 - 1 , 201 - 2 , 203 - 1 , 203 - 2 ; frequency divider circuits (DIVs) 202 - 1 , 202 - 2 , 204 - 1 , 204 - 2 ; and a phase difference calculation circuit 205 .

Each of the CDR circuits 100 - i includes the comparator circuit 101 , the phase-frequency detector circuit 102 , the charge pump circuit 103 , the loop filter 104 , and the LC voltage controlled oscillator 105 . The comparator circuit 101 uses the output clock CKi of the LC voltage controlled oscillator 105 as a sampling clock, determines whether the input data DIi is “0” or “1” at the timing of the clock CKi, and outputs the result of the determination as the output data DOi.

The phase-frequency detector circuit 102 detects the phase difference and the frequency difference between the input data DIi and the clock CKi outputted from the LC voltage controlled oscillator 105 , and outputs the up signal UPi or the down signal DNi, which provides instruction to increase or decrease the control voltage VCOCi, in accordance with the result of the detection. FIG. 3A is a diagram illustrating a configuration example of the phase-frequency detector circuit in the first embodiment. FIG. 3A illustrates, as an example, a Hogge-type phase detector circuit including flip-flops 301 , 302 and exclusive OR logic circuits (XOR circuits) 303 , 304 .

The flip-flop 301 holds and outputs an input IN at the rising edges of the clock CK. The flip-flop 302 holds and outputs the output of the flip-flop 301 at the falling edges of the clock CK. The XOR circuit 303 receives and performs a logical operation on the input IN and the output of the flip-flop 301 , and outputs the result of the logical operation as an up signal UP. The XOR circuit 304 receives and performs a logical operation on the outputs of the flip-flops 301 , 302 , and outputs the result of the logical operation as a down signal DN.

According to the phase detector circuit illustrated in FIG. 3A , when the phase of the clock CK lags behind the phase of the input IN, the up signal UP is asserted (a high level in this example) for a longer period of time than that of the down signal DN. On the other hand, when the phase of the clock CK is ahead of the phase of the input IN, the up signal UP is asserted for a shorter period of time than that of the down signal DN.

FIG. 3B is a diagram illustrating an example of an output characteristic of the phase detector circuit illustrated in FIG. 3A . In FIG. 3B , the horizontal axis indicates the phase difference between the input IN and the clock CK, and the vertical axis indicates the normalized output characteristic (UP-DN). The gain of this phase detector circuit has a linear characteristic with respect to the phase difference between the input IN and the clock CK. The gain of the phase detector circuit is expressed by TD/π, where TD represents a transition density of the input IN.

The charge pump circuit 103 performs addition or subtraction of a current (injection or extraction of electric charges) on a supply node of the control voltage VCOCi in accordance with the up signal UPi and the down signal DNi, which are outputted from the phase-frequency detector circuit 102 , and the output CPADi of the phase difference calculation circuit 113 . FIG. 4 is a diagram illustrating a configuration example of the charge pump circuit 103 in the first embodiment. The charge pump circuit 103 includes: a P-channel transistor 401 , which functions as a switch; an inverter 402 ; a N-channel transistor 403 , which functions as a switch; and a current sources 404 , 405 . Each of the P-channel transistor 401 and the N-channel transistor 403 is a MOS transistor, for example. The current source 404 is a current source connected to a power supply potential node and configured to supply a current ICP. The current source 405 is a current source connected to a reference potential node (for example, a ground potential node) and configured to supply a current ICP. The current sources 404 , 405 have transistors connected in a current mirror configuration, for example.

The P-channel transistor 401 has a gate to which an up signal UP is inputted through the inverter 402 and a source which is connected to the current source 404 . The N-channel transistor 403 has a gate to which a down signal DN is supplied and a source which is connected to the current source 405 . A drain of the P-channel transistor 401 and a drain of the N-channel transistor 403 are connected at a connection point that is connected to the output node OUT. In addition, an output CPAD of the corresponding phase difference calculation circuit 113 is supplied to the output node OUT.

In the charge pump circuit illustrated in FIG. 4 , during a period of time when the up signal UP is asserted (a high level in this example), the P-channel transistor 401 goes into an on state (energized state), so that the current ICP (a corresponding amount of charges) is injected into the output node OUT. On the other hand, during a period of time when the down signal DN is asserted (a high level in this example), the N-channel transistor 403 goes into an on state (energized state), so that the current ICP (a corresponding amount of charges) is extracted from the output node OUT.

In this way, in the charge pump circuit, a voltage level of the output node OUT changes in accordance with the periods of time when the inputted up signal UP and the inputted down signal DN are respectively asserted. Moreover, addition and subtraction of a current (injection and extraction of electric charges) on the output node OUT is performed in accordance with the output CPAD from the corresponding phase difference calculation circuit 113 , so that the voltage level of the output node OUT of the charge pump circuit is changed. In short, the charge pump circuit in the first embodiment is such that the voltage level of the output node OUT is changed in accordance with the periods of time when the inputted up signal UP and the inputted down signal DN are respectively asserted and the output CPAD from the corresponding phase difference calculation circuit 113 . The output node OUT is connected to a loop filter, for example, and charges and discharges the capacitor included in the loop filter.

The loop filter 104 filters and removes a high-frequency component of the output of the charge pump circuit 103 , and allows a low-frequency component to pass therethrough to generate the control voltage VCCi. The loop filter 104 includes: a capacitor 501 and a resistor 502 connected in series between an input node IN (output node OUT) and the reference potential node; and a capacitor 503 connected between the input node IN (output node OUT) and the reference potential node, for example as illustrated in FIG. 5 .

The LC voltage controlled oscillator 105 generates a clock having an oscillation frequency according to the inductor (L) and the capacitor (C). The oscillation frequency of the LC voltage controlled oscillator 105 is controlled by adjusting the capacitance value of the variable capacitor with the control voltage VCOCi, so that the LC voltage controlled oscillator 105 outputs, as the output clock CKi, a clock having a frequency according to the supplied control voltage VCOCi.

FIG. 6 is a diagram illustrating a configuration example of the LC voltage controlled oscillator 105 in the first embodiment. The LC voltage controlled oscillator 105 includes: P-channel transistors 601 , 602 ; N-channel transistors 603 , 604 ; a current source 605 ; variable capacitors 606 , 607 ; and an inductor 608 . Each of the P-channel transistors 601 , 602 and the N-channel transistors 603 , 604 is a MOS transistor, for example. The current source 605 is a current source configured to supply a current IVCO.

The P-channel transistor 601 has a gate connected to a positive-side output node OUT, a source connected to a power supply potential node, and a drain connected to a negative-side output node OUTX. The P-channel transistor 602 has a gate connected to the negative-side output node OUTX, a source connected to the power supply potential node, and a drain connected to the positive-side output node OUT. The N-channel transistor 603 has a gate connected to the positive-side output node OUT, a drain connected to the negative-side output node OUTX, and a source connected to the current source 605 . The N-channel transistor 604 has a gate connected to the negative-side output node OUTX, a drain connected to the positive-side output node OUT, and a source connected to the current source 605 . Each of the variable capacitors 606 , 607 is connected between the positive-side output node OUT and the negative-side output node OUTX, and has a capacitance value controlled with the control voltage VCOC. The inductor 608 is connected between the positive-side output node OUT and the negative-side output node OUTX.

The LC voltage controlled oscillator 105 illustrated in FIG. 6 includes: the P-channel transistors 601 , 602 cross-coupled to each other; and the N-channel transistors 603 , 604 cross-coupled to each other, and the current supplied by the current source 605 is adjusted. The oscillation frequency of the LC voltage controlled oscillator 105 depends on the inductance value of the inductor 608 and the capacitance values of the variable capacitors 606 , 607 . The oscillation frequency is controlled by adjusting the capacitance values of the variable capacitors 606 , 607 with the control voltage VCOC. Note that the LC voltage controlled oscillator 105 may be configured such that a plurality of capacitors are connected in parallel as the variable capacitor, and the capacitance value is adjusted by controlling electrical connection and disconnection of each capacitor with the control voltage VCOC.

The phase detector circuit 201 - 1 detects the phase difference between a reference clock CKREF and input data DI 1 frequency-divided by the frequency divider circuit 202 - 1 , and outputs an up signal UPD 1 and a down signal DND 1 in accordance with the result of the detection. The phase detector circuit 201 - 2 detects the phase difference between the reference clock CKREF and input data DI 2 frequency-divided by the frequency divider circuit 202 - 2 , and outputs an up signal UPD 2 and a down signal DND 2 in accordance with the result of the detection.

The phase detector circuit 203 - 1 detects the phase difference between the reference clock CKREF and a clock CK 1 frequency-divided by the frequency divider circuit 204 - 1 , and outputs an up signal UPCK 1 and a down signal DNCK 1 in accordance with the result of the detection. The phase detector circuit 203 - 2 detects the phase difference between the reference clock CKREF and a clock CK 2 frequency-divided by the frequency divider circuit 204 - 2 , and outputs an up signal UPCK 2 and a down signal DNCK 2 in accordance with the result of the detection.

The configuration of each of the phase detector circuits 201 - 1 , 201 - 2 and the phase detector circuits 203 - 1 , 203 - 2 is the same as that of the phase detector circuit illustrated in FIG. 3A , for example. In addition, the frequency division by the frequency divider circuits 202 - 1 , 202 - 2 and the frequency divider circuits 204 - 1 , 204 - 2 is performed to alleviate operation speed requirements for the circuits on the subsequent stages, and may take various frequency division ratios depending on the configuration. Note that when the circuits on the subsequent stages are capable of processing, the frequency divider circuit 202 - 1 , 202 - 2 or the frequency divider circuit 204 - 1 , 204 - 2 may not be provided in the configuration.

The phase difference calculation circuit 205 generates outputs CPAD 1 , CPAD 2 according to the phase difference between the input data DI 1 , DI 2 of the CDR circuits 100 - 1 , 100 - 2 and the phase difference between the output clocks CK 1 , CK 2 of the LC voltage controlled oscillator 105 based on signals outputted from the phase detector circuits 201 - 1 , 201 - 2 and the phase detector circuits 203 - 1 , 203 - 2 .

The phase difference calculation circuit 205 obtains the phase difference between the input data DI 1 , DI 2 in the adjacent lanes based on the up signal UPD 1 and the down signal DND 1 , which indicate the phase difference between the frequency-divided input data DI 1 and the reference clock CKREF, as well as the up signal UPD 2 and the down signal DND 2 , which indicate the phase difference between the frequency-divided input data DI 2 and the reference clock CKREF. Similarly, the phase difference calculation circuit 205 obtains the phase difference between the clocks CK 1 , CK 2 in the adjacent lanes based on the up signal UPCK 1 and the down signal DNCK 1 , which indicate the phase difference between the frequency-divided clock CK 1 and the reference clock CKREF as well as the up signal UPCK 2 and the down signal DNCK 2 , which indicate the phase difference between the frequency-divided clock CK 2 and the reference clock CKREF. The phase difference calculation circuit 205 then generates outputs CPAD 1 , CPAD 2 for adjusting the gains of up and down in the loops of the CDR circuits 100 - 1 , 100 - 2 in accordance with the difference between the obtained phase difference between the input data DI 1 , DI 2 and the obtained phase difference between the clocks CK 1 , CK 2 .

Here, the transition density TD of the input data DI 1 , DI 2 may be set to 0.5 on the assumption of random data. On the other hand, the transition density TD of the clocks CK 1 , CK 2 is 1 because the clocks CK 1 , CK 2 have signal transition in every cycle. In view of this, the first embodiment, adjustment is performed to match the gain of the phase detector circuits 201 - 1 , 201 - 2 for the input data DI 1 , DI 2 and the gain of the phase detector circuits 203 - 1 , 203 - 2 for the clocks CK 1 , CK 2 . For example, gain adjustment is performed in accordance with the transition density TD such that (a detection rate×a current value) is matched between the input data DI 1 , DI 2 and the clocks CK 1 , CK 2 .

As one method of matching the gain of the phase detector circuits 201 - 1 , 201 - 2 for the input data DI 1 , DI 2 and the gain of the phase detector circuits 203 - 1 , 203 - 2 for the clocks CK 1 , CK 2 , the frequency division ratios of the frequency divider circuits 202 - 1 , 202 - 2 and the frequency divider circuits 204 - 1 , 204 - 2 may be controlled to match the numbers of times of transition per unit time. For example, the frequency division ratios may be set such that the frequency of the frequency-divided clocks CK 1 , CK 2 to be inputted to the phase detector circuit 203 - 1 , 203 - 2 becomes one-half of the frequency component of the frequency-divided input data DI 1 , DI 2 to be inputted to the phase detector circuit 201 - 1 , 201 - 2 . A configuration example of the phase difference calculation circuit 205 in this case is illustrated in FIGS. 7A and 7B .

FIG. 7A is a diagram illustrating a configuration example of a circuit configured to generate the output CPAD 1 in the phase difference calculation circuit 205 . The circuit includes: P-channel transistors 701 , 705 , 709 , 713 ; N-channel transistors 702 , 706 , 710 , 714 ; inverters 717 to 720 ; and current sources 703 , 704 , 707 , 708 , 711 A, 712 A, 715 A, 716 A. Each of the current sources 703 , 707 , 711 A, 715 A is a current source connected to the power supply potential node and configured to supply a current IADJ. Each of the current sources 704 , 708 , 712 A, 716 A is a current source connected to the reference potential node (for example, the ground potential node) and configured to supply the current IADJ.

The P-channel transistor 701 has a gate to which an up signal UPCK 1 is inputted through the inverter 717 , a source connected to the current source 703 , and a drain connected to the output node of the output CPAD 1 . The N-channel transistor 702 has a gate to which a down signal DNCK 1 is inputted, a source connected to the current source 704 , and a drain connected to the output node of the output CPAD 1 . The P-channel transistor 705 has a gate to which a down signal DNCK 2 is inputted through the inverter 718 , a source connected to the current source 707 , and a drain connected to the output node of the output CPAD 1 . The N-channel transistor 706 has a gate to which an up signal UPCK 2 is inputted, a source connected to the current source 708 , and a drain connected to the output node of the output CPAD 1 .

The P-channel transistor 709 has a gate to which a down signal DND 1 is inputted through the inverter 719 , a source connected to the current source 711 A, and a drain connected to the output node of the output CPAD 1 . The N-channel transistor 710 has a gate to which an up signal UPD 1 is inputted, a source connected to the current source 712 A, and a drain connected to the output node of the output CPAD 1 . The P-channel transistor 713 has a gate to which an up signal UPD 2 is inputted through the inverter 720 , a source connected to the current source 715 A, and a drain connected to the output node of the output CPAD 1 . The N-channel transistor 714 has a gate to which a down signal DND 2 is inputted, a source connected to the current source 716 A, and a drain connected to the output node of the output CPAD 1 .

FIG. 7B is a diagram illustrating a configuration example of a circuit configured to generate the output CPAD 2 in the phase difference calculation circuit 205 . The circuit includes: P-channel transistors 721 , 725 , 729 , 733 ; N-channel transistors 722 , 726 , 730 , 734 ; inverters 737 to 740 ; and current sources 723 A, 724 A, 727 A, 728 A, 731 , 732 , 735 , 736 . Each of the current sources 723 A, 727 A, 731 , 735 is a current source connected to the power supply potential node and configured to supply a current IADJ. Each of the current sources 724 A, 728 A, 732 , 736 is a current source connected to the reference potential node (for example, the ground potential node) and configured to supply a current IADJ.

The P-channel transistor 721 has a gate to which an up signal UPD 1 is inputted through the inverter 737 , a source connected to the current source 723 A, and a drain connected to the output node of the output CPAD 2 . The N-channel transistor 722 has a gate to which a down signal DND 1 is inputted, a source connected to the current source 724 A, and a drain connected to the output node of the output CPAD 2 . The P-channel transistor 725 has a gate to which a down signal DND 2 is inputted through the inverter 738 , a source connected to the current source 727 A, and a drain connected to the output node of the output CPAD 2 . The N-channel transistor 726 has a gate to which an up signal UPD 2 is inputted, a source connected to the current source 728 A, and a drain connected to the output node of the output CPAD 2 .

The P-channel transistor 729 has a gate to which a down signal DNCK 1 is inputted through the inverter 739 , a source connected to the current source 731 , and a drain connected to the output node of the output CPAD 2 . The N-channel transistor 730 has a gate to which an up signal UPCK 1 is inputted, a source connected to the current source 732 , and a drain connected to the output node of the output CPAD 2 . The P-channel transistor 733 has a gate to which an up signal UPCK 2 is inputted through the inverter 740 , a source connected to the current source 735 , and a drain connected to the output node of the output CPAD 2 . The N-channel transistor 734 has a gate to which a down signal DNCK 2 is inputted, a source connected to the current source 736 , and a drain connected to the output node of the output CPAD 2 .

Note that it is desirable to adjust the current IADJ supplied by each of the current sources 703 , 704 , 707 , 708 , 711 A, 712 A, 715 A, 716 A, 723 A, 724 A, 727 A, 728 A, 731 , 732 , 735 , 736 illustrated in FIGS. 7A and 7B , depending on the magnitude of interference between the LC voltage controlled oscillators.

Here, the phases of the waveforms of the input data DI 1 , DI 2 and the clocks CK 1 , CK 2 relative to the phase of the reference clock CKREF are represented by φDI 1 , φDI 2 , φCK 1 , φCK 2 , respectively. The circuit illustrated in FIG. 7A performs an operation of (φCK 1 −φCK 2 )−(φDI 1 −φDI 2 ), and outputs the output CPAD 1 according to the difference between the phase difference (φDI 1 −φDI 2 ) between the input data DI 1 , DI 2 and the phase difference (φCK 1 −φCK 2 ) between the clocks CK 1 , CK 2 . On the other hand, the circuit illustrated in FIG. 7B performs an operation of (φDI 1 −φDI 2 )−(φCK 1 −φCK 2 ), and outputs the output CPAD 2 according to the difference between the phase difference (φDI 1 −φDI 2 ) between the input data DI 1 , DI 2 and the phase difference (φCK 1 −φCK 2 ) between the clocks CK 1 , CK 2 . As is clear from the above description, one of the output CPAD 1 and the output CPAD 2 is a plus (positive) output, and the other is a minus (negative) output, and the output CPAD 1 and the output CPAD 2 have the same magnitude.

Alternatively, as another method of matching the gain of the phase detector circuits 201 - 1 , 201 - 2 for the input data DI 1 , DI 2 and the gain of the phase detector circuits 203 - 1 , 203 - 2 for the clocks CK 1 , CK 2 , the gain of the phase detector circuits 201 - 1 , 201 - 2 for the input data DI 1 , DI 2 may be set to twice the gain of the phase detector circuits 203 - 1 , 203 - 2 for the clocks CK 1 , CK 2 while the frequency divider circuits 202 - 1 , 202 - 2 and the frequency divider circuits 204 - 1 , 204 - 2 are set to have the same frequency division ratio. In other words, the weight on the phase difference between the input data DI 1 , DI 2 and the weight on the phase difference between the clocks CK 1 , CK 2 may be made different from each other, or more specifically, the weight on the phase difference between the input data DI 1 , DI 2 may be set to twice the weight on the phase difference between the clocks CK 1 , CK 2 . For example, in the phase difference calculation circuit 205 , the current value of the current sources corresponding to the input data DI 1 , DI 2 may be set to twice the current value of the current sources corresponding to the clock CK 1 , CK 2 . A configuration example of the phase difference calculation circuit 205 in this case is illustrated in FIGS. 8A and 8B .

FIG. 8A is a diagram illustrating a configuration example of a circuit configured to generate the output CPAD 1 in the phase difference calculation circuit 205 . FIG. 8B is a diagram illustrating a configuration example of a circuit configured to generate the output CPAD 2 in the phase difference calculation circuit 205 . The circuit illustrated in FIG. 8A is different from the circuit illustrated in FIG. 7A in that the current sources connected to the transistors 709 , 710 , 713 , 714 controlled with the up signals UPD 1 , UPD 2 and the down signals DND 1 , DND 2 for the input data DI 1 , DI 2 are current sources 711 B, 712 B, 715 B, 716 B configured to supply a current 2 IADJ. The circuit illustrated in FIG. 8A is the same as the circuit illustrated in FIG. 7A in the other points.

The circuit illustrated in FIG. 8B is different from the circuit illustrated in FIG. 7B in that the current sources connected to the transistors 721 , 722 , 725 , 726 controlled with the up signals UPD 1 , UPD 2 and the down signals DND 1 , DND 2 for the input data DI 1 , DI 2 are current sources 723 B, 724 B, 727 B, 728 B configured to supply the current 2 IADJ. The circuit illustrated in FIG. 8B is the same as the circuit illustrated in FIG. 7B in the other points.

According to the first embodiment, it is possible to cancel the influence of interference between LC voltage controlled oscillators by adjusting the gains in the loops in CDR circuits in accordance with the phase differences between the input data and the phase differences between the output clocks of the CDR circuits, and to thus suppress deterioration in the characteristics of the CDR circuits due to the interference. In addition, the first embodiment makes it possible to arrange the LC voltage controlled oscillators (CDR circuits) adjacent to each other, thus reducing the area for implementation, so that the area efficiency can be improved.

Note that, in the first embodiment described above, the phase difference between the reference clock CKREF and each of the input data DI 1 , DI 2 and the clocks CK 1 , CK 2 is detected. However, since the clocks CK 1 , CK 2 have a signal transition in every cycle, the clocks CK 1 , CK 2 may be directly compared to detect the phase difference without using the reference clock CKREF.

Second Embodiment

Next, a second embodiment will be described.

FIG. 9 is a diagram illustrating a configuration example of a receiving circuit in the second embodiment. FIG. 9 illustrates, as an example, a receiving circuit configured with two lanes through which two CDR circuits receive data and output data in parallel. In FIG. 9 , constituent elements having the same functions as those of the constituent elements illustrated in FIG. 2 are denoted by the same signs, and redundant description is omitted.

In the receiving circuit in the first embodiment illustrated in FIG. 2 , each of the phase detector circuits 201 - 1 , 201 - 2 and the phase detector circuits 203 - 1 , 203 - 2 detects the phase difference between its target signal and the reference clock CKREF. In contrast, in the second embodiment, a phase interpolation circuit 901 generates a clock with an intermediate phase from clocks CK 1 , CK 2 through interpolation. In the example illustrated in FIG. 9 , the phase interpolation circuit 901 interpolates the phase from the frequency-divided clocks CK 1 , CK 2 frequency-divided by frequency divider circuits 204 - 1 , 204 - 2 to generate a clock CKI. Then, each of phase detector circuits 201 - 1 , 201 - 2 and phase detector circuits 203 - 1 , 203 - 2 uses the output (clock) CKI of the phase interpolation circuit 901 as a reference clock, and detects a phase difference.

FIG. 10 is a diagram illustrating a configuration example of the phase interpolation circuit 901 illustrated in FIG. 9 . The phase interpolation circuit 901 includes: N-channel transistors 1001 , 1002 , 1006 , 1007 ; resistors 1003 , 1004 ; and current sources 1005 , 1008 . Each of the N-channel transistors 1001 , 1002 , 1006 , 1007 is a MOS transistor, for example. The current source 1005 is a current source connected to the reference potential node and configured to supply a current IPI 1 . The current source 1006 is a current source connected to the reference potential node and configured to supply a current IPI 2 .

The N-channel transistor 1001 has a gate connected to a first positive-side input node IN 1 , a source connected to the current source 1005 , and a drain connected to a negative-side output node OUTX. The N-channel transistor 1002 has a gate connected to a first negative-side input node INX 1 , a source connected to the current source 1005 , and a drain connected to a positive-side output node OUT.

The N-channel transistor 1006 has a gate connected to a second negative-side input node INX 2 , a source connected to the current source 1008 , and a drain connected to the positive-side output node OUT. The N-channel transistor 1007 has a gate connected to a second positive-side input node IN 2 , a source connected to the current source 1008 , and a drain connected to the negative-side output node OUTX. The resistor 1003 has one end connected to the negative-side output node OUTX and the other end connected to the power supply potential node.

The resistor 1004 has one end connected to the positive-side output node OUT and the other end connected to the power supply potential node. For example, a signal on the positive side of a clock CK 1 is inputted to the first positive-side input node IN 1 , a signal on the negative side of the clock CK 1 (a inverted phase signal of the signal on the positive side) is inputted to the first negative-side input node INX 1 , a signal on the positive side of a clock CK 2 is inputted to the second positive-side input node IN 2 , and a signal on the negative side of the clock CK 2 (an inverted phase signal of the signal on the positive side) is inputted to the second negative-side input node INX 2 .

In the phase interpolation circuit 901 illustrated in FIG. 10 , an output part of a differential pair in which one of the clocks CK 1 and CK 2 is inputted to the input nodes IN 1 , INX 1 and an output part of a differential pair in which the other clock is inputted to the input nodes IN 2 , INX 2 are connected, so that a ratio of interpolation can be changed by changing a ratio between the current values of the currents IPI 1 , IPI 2 supplied to the respective differential pair. In the second embodiment, since it is suffices that clocks of specific phases are generated by interpolation, the ratio between the current values of the currents IPI 1 , IPI 2 may be 1:1 (the ratio of interpolation is 1:1), for example.

According to the second embodiment, it is possible to cancel the influence of interference between LC voltage controlled oscillators included in CDR circuits, and to thus suppress deterioration in the characteristics of the CDR circuits due to the interference, and it is possible to arrange the LC voltage controlled oscillators (CDR circuits) adjacent to each other, thus reducing the area for implementation, so that the area efficiency can be improved, like the first embodiment. Moreover, the second embodiment makes it possible to generate the reference clock inside and to detect the phase difference between the input data and the phase difference between the output clocks without supplying the reference clock from outside.

Third Embodiment

Next, a third embodiment will be described.

The above-described first and second embodiments have been described by giving the receiving circuits configured with two lanes through which two CDR circuits receive data and output data in parallel as examples. These receiving circuits, however, are not limiting, and a receiving circuit having three lanes or more may be used. FIG. 11 is a diagram illustrating a configuration example of a receiving circuit in the third embodiment. In FIG. 11 , constituent elements having the same functions as those of the constituent elements illustrated in FIG. 1A are denoted by the same signs, and redundant description is omitted.

The interference between LC voltage controlled oscillators included in CDR circuits varies depending on their distance. For this reason, the larger their distance, the smaller the influence of the interference. Accordingly, when LC voltage controlled oscillators are distant from each other by two lanes or more, the influence of the interference therebetween may be ignored. In view of this, in the receiving circuit having three lanes or more, as illustrated in FIG. 11 , each pair of adjacent two lanes are provided with: a phase detector circuit 111 configured to detect a phase difference between input data in the adjacent lanes; a phase detector circuit 112 configured to detect a phase difference between clocks in the adjacent lanes; and a phase difference calculation circuit 113 configured to generate an output for gain adjustment in accordance with the phase difference between the input data and the phase difference between the clocks, based on outputs of the phase detector circuits 111 , 112 .

For example, phase detector circuits 111 - 1 , 112 - 1 and a phase difference calculation circuit 113 - 1 are provided for the lane of a CDR circuit 100 - 1 and the lane of a CDR circuit 100 - 2 , which are adjacent to each other. The phase detector circuit 111 - 1 outputs an up signal and a down signal in accordance with the phase difference between input data DI 1 , DI 2 in the adjacent lanes, and the phase detector circuit 112 - 1 outputs an up signal and a down signal in accordance with the phase difference between clocks CK 1 , CK 2 in the adjacent lanes. The phase difference calculation circuit 113 - 1 generates outputs CPAD 1 , CPADA 2 according to the difference between the phase difference between the input data DI 1 , DI 2 and the phase difference between the clocks CK 1 , CK 2 , based on the up signals and the down signals outputted from the phase detector circuits 111 - 1 , 112 - 1 , and output the outputs CPAD 1 , CPADA 2 to charge pump circuits 103 of the CDR circuits 100 - 1 , 100 - 2 .

In addition, for example, phase detector circuits 111 - 2 , 112 - 2 and phase difference calculation circuit 113 - 2 are provided for the lane of the CDR circuit 100 - 2 and the lane of a CDR circuit 100 - 3 , which are adjacent to each other. The phase detector circuit 111 - 2 outputs an up signal and a down signal in accordance with the phase difference between input data DI 2 , DI 3 in the adjacent lanes, and the phase detector circuit 112 - 2 outputs an up signal and a down signal in accordance with the phase difference between clocks CK 2 , CK 2 in the adjacent lanes. The phase difference calculation circuit 113 - 2 generates outputs CPADB 2 , CPADA 3 according to the difference between the phase difference between the input data DI 2 , DI 3 and the phase difference between the clocks CK 2 , CK 3 , based on the up signals and the down signals outputted from the phase detector circuits 111 - 2 , 112 - 2 , and output the outputs CPADB 2 , CPADA 3 to the charge pump circuits 103 of the CDR circuits 100 - 2 , 100 - 3 .

Then, the charge pump circuit 103 and a loop filter 104 of the CDR circuit 100 - 1 generate a control voltage VCOC 1 by performing addition or subtraction of a current (injection or extraction of electric charges) in accordance with the up signal UP 1 and the down signal DN 1 , which are outputted from a phase-frequency detector circuit 102 , and the output CPAD 1 of the phase difference calculation circuit 113 - 1 . The charge pump circuit 103 and a loop filter 104 of the CDR circuit 100 - 2 generate a control voltage VCOC 2 by performing addition or subtraction of a current (injection or extraction of electric charges) in accordance with the up signal UP 2 and the down signal DN 2 , which are outputted from the phase-frequency detector circuit 102 , the output CPADA 2 of the phase difference calculation circuit 113 - 1 , and the output CPADB 2 of the phase difference calculation circuit 113 - 2 . In this way, in the lane sandwiched by two lanes (the lane on both sides of which other CDR circuits are arranged), the gains of up (UP) and down (DN) in the loop of the CDR circuit are adjusted in accordance with the phase difference between the input data and the phase difference between the clocks relative to each of the adjacent lanes.

According to the third embodiment, it is possible to cancel the influence of interference between LC voltage controlled oscillators included in CDR circuits, and to thus suppress deterioration in the characteristics of the CDR circuits due to the interference, even in the case of a receiving circuit having three lanes or more.

Fourth Embodiment

Next, a fourth embodiment will be described.

FIG. 12 is a diagram illustrating a configuration example of a receiving circuit in the fourth embodiment. In FIG. 12 , constituent elements having the same functions as those of the constituent elements illustrated in FIG. 1A are denoted by the same signs, and redundant description is omitted. The receiving circuit in the fourth embodiment is what is obtained by digitizing the charge pump circuit and the loop filter in the CDR circuit 100 , and a digital filter 1201 achieves functions corresponding to the above-described charge pump circuit and loop filter.

A phase difference calculation circuit 1202 generates gain adjustment codes GCP, GCN according to the difference between a phase difference between input data DI 1 , DI 2 and a phase difference between clocks CK 1 , CK 2 , based on an up signal UPD and a down signal DND, which are outputted from a phase detector circuit 111 , and an up signal UPCK and a down signal DNCK, which are outputted from a phase detector circuit 112 . Note that the up signals UPD, UPCK and the down signals DND, DNCK, which are outputted from the phase detector circuits 111 , 112 are not necessary to be digital signals, and it is suffices that at least the gain adjustment codes GCP, GCN, which are outputted from the phase difference calculation circuit 1202 , are digital signals. The gain adjustment code GCP, which is outputted from the phase difference calculation circuit 1202 , is supplied to the digital filter 1201 of the CDR circuit 100 - 1 , and the gain adjustment code GCN, which is outputted from the phase difference calculation circuit 1202 , is supplied to the digital filter 1201 of the CDR circuit 100 - 2 .

The digital filter 1201 generates a control code VCOC for an LC voltage controlled oscillator 105 by performing digital signal processing based on the up signal UP and the down signal DN, which are digital signals, outputted from the phase-frequency detector circuit 102 , and the gain adjustment code GC, which is outputted from the phase difference calculation circuit 1202 . The oscillation frequency of the LC voltage controlled oscillator 105 is controlled by adjusting the capacitance value of a variable capacitor with the control code VCOC, so that the LC voltage controlled oscillator 105 outputs, as an output clock CK, a clock having a frequency according to the control code VCOC. Here, the variable capacitor included in the LC voltage controlled oscillator 105 suffices as long as its capacitance value is adjustable by digital control. For example, the LC voltage controlled oscillator 105 may be configured such that a plurality of capacitors are connected in parallel as the variable capacitor, and the capacitance value is adjusted by controlling electrical connection and disconnection of each capacitor with the control code VCOC.

FIG. 13 is a diagram illustrating a configuration example of the digital filter 1201 in the fourth embodiment. The digital filter 1201 includes: multipliers 1301 , 1302 , 1306 , 1309 ; adders 1303 , 1304 , 1307 , 1310 ; and flip-flops 1308 , 1311 . Note that in FIG. 13 , bit operation processing on digital signals and clocks for driving the flip-flops 1308 , 1311 and the like are omitted.

The multiplier 1301 multiplies the inputted up signal UP by (1+GC) and outputs the result of the operation, where the value (1+GC) is obtained by the adder 1303 adding the inputted gain adjustment code GC to 1. The multiplier 1302 multiplies the inputted down signal DN by (1−GC) and outputs the result of the operation, where the value (1−GC) is obtained by the adder 1304 subtracting the inputted gain adjustment code GC from 1. The adder 1305 subtracts the output value of the multiplier 1302 from the output value of the multiplier 1301 and outputs the result of the operation. In this way, the inputted up signal UP and down signal DN are multiplied by (1+GC) and (1−GC), respectively, in accordance with the gain adjustment code GC, so that the ratios of the gains of up (UP) and down (DN) in the loop of the CDR circuit 100 are adjusted.

The multiplier 1306 multiplies the output value of the adder 1305 and a filter coefficient G 2 . The adder 1307 adds an output value of the multiplier 1306 and an output value of the flip-flop 1308 . The flip-flop 1308 holds and outputs an output value of the adder 1307 . In other words, the multiplier 1306 , the adder 1307 , and the flip-flop 1308 achieves an integrating circuit configured to feed back and add the output of the flip-flop 1308 .

In addition, the multiplier 1309 multiplies the output value of the flip-flop 1308 and a filter coefficient G 1 . The adder 1310 adds an output value of the multiplier 1309 and an output value of the flip-flop 1311 . The flip-flop 1311 holds and outputs an output value of the adder 1310 . In other words, the multiplier 1309 , the adder 1310 , and the flip-flop 1311 achieves an integrating circuit configured to feedback and add the output of the flip-flop 1311 . An output of the flip-flop 1311 is outputted as the control code VCOC.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.