Bump structures for semiconductor package

This application claims the benefit of and is a divisional of U.S. patent application Ser. No. 13/624,356, filed Sep. 21, 2012, and entitled, “Bump Structures for Semiconductor Package,” which application claims the benefit of U.S. Provisional Patent Application No. 61/695,560, filed Aug. 31, 2012 entitled, “Bump Structures for Semiconductor Package” both of which applications are hereby incorporated herein by reference.

Semiconductor packaging utilizes bumps to establish electrical contact between a chip's Input/Output (I/O) pads and a substrate. Structurally, a bump structure contains a bump and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. The bumps themselves, based on the material and shape, are classified as solder balls, pillar bumps and metal bumps with mixed metals. Recently, instead of using solder balls, pillar bumps are used in the electronic component to achieve finer pitch with minimum probability of bump bridging, reduce capacitance load for the circuits and allow the electronic component to perform at higher frequencies. A solder alloy is still necessary for capping the bump structure and joining electronic components as well. Properly applied, pillar bumps can be placed in virtually any position on a chip, given the pitch considerations. In addition, redundant bumps can be added for symmetry, mechanical stability, additional thermal arrangement, or to optimize interconnect to reduce inductance and enhance speed.

FIG. 1 is a plan view of a semiconductor chip having a plurality of bump structures in accordance with some embodiments;

FIG. 2 is a cross-sectional view of the bump structures on the semiconductor chip taken along the line I-I of FIG. 1 in accordance with some embodiments;

FIGS. 3A through 3D are cross-sectional views of intermediate stages in the manufacturing of bump structures in accordance with an embodiment;

FIG. 4 is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 3D in accordance with some embodiments;

FIG. 5A is a cross-sectional view of bump structures on a semiconductor chip in accordance with some embodiments;

FIG. 5B is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 5A in accordance with some embodiments;

FIG. 6A is a cross-sectional view of bump structures on a semiconductor chip in accordance with some embodiments;

FIG. 6B is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 6A in accordance with some embodiments;

FIGS. 7A through 7C are cross-sectional views of intermediate stages in the manufacturing of bump structures in accordance with an embodiment;

FIG. 8 is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 7C in accordance with some embodiments;

FIG. 9A is a cross-sectional view of bump structures on a semiconductor chip in accordance with some embodiments;

FIG. 9B is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 9A in accordance with some embodiments;

FIG. 10A is a cross-sectional view of bump structures on a semiconductor chip in accordance with some embodiments;

FIG. 10B is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 10A in accordance with some embodiments;

FIGS. 11A through 11B are cross-sectional views of intermediate stages in the manufacturing of bump structures in accordance with an embodiment;

FIG. 12 is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 11B in accordance with some embodiments;

FIG. 13A is a cross-sectional view of bump structures on a semiconductor chip in accordance with some embodiments;

FIG. 13B is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 13A in accordance with some embodiments;

FIG. 14A is a cross-sectional view of bump structures on a semiconductor chip in accordance with some embodiments; and

FIG. 14B is a cross-sectional view of a package structure with the semiconductor chip shown in FIG. 14A in accordance with some embodiments.

It is to be understood that the following disclosure provides many different embodiments or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this description will be thorough and complete, and will fully convey the present disclosure to those of ordinary skill in the art. It will be apparent, however, that one or more embodiments may be practiced without these specific details.

In the drawings, the thickness and width of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements. The elements and regions illustrated in the figures are schematic in nature, and thus relative sizes or intervals illustrated in the figures are not intended to limit the scope of the present disclosure.

FIG. 1 is a plan view of a semiconductor chip having a plurality of bump structures in accordance with some embodiments.

As depicted in FIG. 1 , a semiconductor chip 100 includes at least a first region 110 and a second region 120 , wherein a plurality of first bump structures 28 A are formed on the first region 110 , and a plurality of second bump structures 28 D are formed on the second region 120 . In an embodiment, the first region 110 is in the central region of the chip 100 , and the second region 120 is along the peripheral region of the chip 100 . In some embodiments, the first bump structures 28 A and the second bump structures 28 D are pillar bump structures. In an embodiment, the plan-view profile of the bump structures 28 A or 28 D is square, and the plan-view profile of the bump structure 28 A or 28 D can be circular, rectangular, oval, octagonal, or the like according to some embodiments. The first bump structures 28 A with first lateral dimensions W 1 (also referring to diameter or width of the first bump structures) present a first bump density in the first region 110 , and the second bump structures 28 D with second lateral dimensions W 2 (also referring to diameter or width of the second bump structures) present a second bump density in the second region 120 . In an embodiment, the first bump density is different than the second bump density, while the first bump density can be the same as the second bump density in some embodiments. In an embodiment, the first lateral dimensions W 1 of the first bump structures 28 A is uniform throughout the first region 110 , and the second lateral dimensions W 2 of the second bump structures 28 D is uniform throughout the second region 120 . In an embodiment, the first lateral dimension W 1 is different than the second lateral dimension W 2 , while the first lateral dimension W 1 can be the same as the second lateral dimension W 2 in some embodiments. As examples of the semiconductor chip 100 , a logic chip or a memory chip is employed. In an embodiment, the first bump structures 28 A function as active bumps, for example signal bumps, and the second bump structures 28 D represent as dummy bumps without serving electrical connection between the chip 100 and any other substrate. In some embodiments, as depicted in FIG. 1 , the first region 110 is smaller than the second region 120 , the first bump density is greater than the second bump density, and the first lateral dimension W 1 is smaller than the second lateral dimension W 2 . For example, the difference between W 1 and W 2 is about 1˜10 μm.

FIG. 2 is a cross-sectional view of the bump structures on the semiconductor chip taken along the line I-I of FIG. 1 in accordance with some embodiments. The semiconductor chip 100 includes a first substrate 10 , a metal pad 16 on the first substrate 10 , and a passivation layer 18 overlying the metal pad 16 . The first bump structures 28 A are electrically connecting to the metal pad 16 through openings in the passivation layer 18 , and the second bump structures 28 D are positioned on the passivation layer 18 without electrical connecting to the metal pad 16 . In some embodiments, the first substrate 10 includes a semiconductor substrate 11 , an integrated circuit device 12 in and/or on the semiconductor substrate 11 , and an interconnect structure 14 overlying the device 12 and the semiconductor substrate 11 .

The first substrate 10 is employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or thereupon. The semiconductor substrate 11 is defined to mean any construction comprising semiconductor materials including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used.

The integrated circuit device 12 formed in and/or on the semiconductor substrate 11 may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), resistors, diodes, capacitors, inductors, fuses, and other suitable elements. The microelectronic elements are interconnected to form the integrated circuit device, such as a logic device, memory device (e.g., static random access memory or SRAM), radio frequency (RF) device, input/output (I/O) device, system-on-chip (SoC) device, combinations thereof, and other suitable types of devices.

The interconnect structure 14 includes inter-layer dielectric layers (not shown) and metallization layers (not shown) overlying the integrated circuit device 12 . The inter-layer dielectric layers include low-k dielectric materials, un-doped silicate glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials. The dielectric constants (k value) of the low-k dielectric materials may be less than about 3.9, or less than about 2.8. The metallization layers may be formed of, for example copper (Cu), aluminum (Al), AlCu, copper alloy, or other mobile conductive materials.

The metal pad 16 is a metallization layer formed on a top-level inter-layer dielectric layer of the interconnect structure 14 . In an embodiment, the metal pad 16 is formed in the first region 110 of the semiconductor chip 100 . In some embodiments, the metal pad 16 is formed on the first region 110 and the second region 120 as well. Suitable materials for the metal pad 16 may include, but are not limited to, for example Cu, Al, AlCu, copper alloy, or other mobile conductive materials. The metal pad 16 provides an electrical connection upon which the first bump structures 28 A are formed for external connections in subsequent processing steps.

The passivation layer 18 is formed on the interconnect structure 14 and covers some portions of the metal pad 16 , while some portions of the metal pad 16 within the first region 110 are exposed by openings 19 (see FIGS. 3A and 3B ) in the passivation layer 18 . In some embodiments, the passivation layer 18 includes a dielectric layer, a polymer layer, or combinations thereof. The passivation layer 18 may be a single layer or a laminated layer. In FIG. 2 , a single layer of the passivation layer 18 is shown for illustrative purposes only. As such, other embodiments may include any number of passivation layers. The passivation layer 18 may have a single opening or a plurality of openings 19 on one metal pad 16 . In FIG. 2 , the passivation layer 18 having two openings 19 is shown for illustrative purposes only. As such, other embodiments may include any number of openings 19 in the passivation layer 18 over one metal pad 16 .

The bump structures 28 A and 28 D are formed after the formation of the patterned passivation layer 18 with openings 19 . In some embodiments, the first bump structures 28 A are formed on the exposed portions of the metal pad 16 within the first region 110 , and the second bump structures 28 D are formed on the passivation layer 18 within the second region 120 . In at least one embodiment, the bump structures 28 A and 28 D are formed of pillar bumps. The pillar bumps are formed of conductive materials. In some embodiments, the pillar bump includes an under-bump metallization (UBM) layer, a metal pillar and at least one capping layer. The metal pillar may include Cu, Cu alloy, gold (Au), Au alloy or the like. The capping layer may include nickel (Ni), solder, Au, palladium (Pd), or any other noble metals.

On the first region 110 , the first bump structure 28 A has a first bump height H A that is measured from the bottom side 28 A B of the first bump structure 28 A to the top side 28 A T of the first bump structure 28 A. On the second region 120 , the second bump structure 28 D has a second bump height H D that is measured from the bottom side 28 D B of the second bump structure 28 D to the top side 28 D T of the second bump structure 28 D. The second bump structures 28 D are positioned on the passivation layer 18 with a thickness T 18 . In some embodiments, the thickness T 18 is greater than about 3 μm. For example the thickness T 18 is between about 1 μm and about 20 μm.

For reducing or eliminating the gap between the top sides of the two bump structures, the second bump height H D is well controlled to make the top side 28 A t of the first bump structure 28 A being substantially leveled with the top side 28 D t of the second bump structure 28 D according to some embodiments. For example, the gap between the top side 28 A T and the top side 28 D T can be controlled at a range of about 0 to about 5 μm, at a range of about 0 to about 3 μm or at a range of about 0 to about 1 μm. In some embodiments, the first bump height H A is greater than the second bump height H D . For example, the difference between the first bump height H A and the second bump height H D is at the range between about 1 nm and about 20 nm. The minimized gap between the top side 28 A T and the top side 28 D T makes control of standoff possible for a package structure with the chip 100 bonded to another substrate. The exemplary package structure involves the chip on a package substrate with bump structures, the chip on a wafer with bump structures, or the chip on another chip with bump structures. By controlling the bump within the chip 100 , variation of standoffs between the chip 100 and the other substrate can be minimized, such that the standoffs become more uniform and quality of dispensing underfill in the package structure is improved. In some embodiments, the mechanisms for providing coplanar bump structures can be applied to the manufacture of bump structures with different critical dimension on different regions within the chip.

FIGS. 3A through 3D are cross-sectional views of intermediate stages in the manufacturing of bump structures in accordance with an embodiment. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 1 ˜ 2 .

Referring to FIG. 3A , the first substrate 10 , for example a wafer-level form including a plurality of chip regions is provided with the integrated circuit device 12 (see FIG. 2 ) formed in or on the semiconductor substrate 11 , the interconnect structure 14 formed on the semiconductor substrate 11 , and the metal pad 16 formed on the interconnect structure 14 . In an embodiment, each chip region includes the first region 110 and the second region 120 , and the metal pad 16 is formed over the interconnect structure 14 in the first region 110 . The passivation layer 18 is formed on the interconnect structure 14 and covering portions of the metal pad 16 . In some embodiments, the formation of the passivation layer 18 includes successfully forming a dielectric layer 18 A and a first polymer layer 18 B over the first substrate 10 and then forming an opening 19 a in the stack of the layers 18 A and 18 B such that a portion of the metal pad 16 is exposed. In some embodiments, the dielectric layer 18 A includes undoped silicate glass (USG), silicon nitride, silicon oxide, silicon oxynitride or a non-porous material by any suitable method, such as CVD, PVD, or the like. The dielectric layer 18 A may be a single layer or a laminated layer. In some embodiments, the first polymer layer 18 B is formed of epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used. In an embodiment, the opening 19 a is formed to pass through the dielectric layer 18 A and the first polymer layer 18 B and expose a central portion of the metal pad 16 .

Referring to FIG. 3B , the formation of the passivation layer 18 further includes forming a second polymer layer 18 C on the resulted structure as depicted in FIG. 3A . In some embodiments, the second polymer layer 18 C is formed of epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively soft, often organic, dielectric materials can also be used. Then another openings 19 b and opening 19 c are formed in the second polymer layer 18 C. The openings 19 b are formed in the second polymer layer 18 C within the first region 110 to expose connection portions 16 P of the metal pad 16 . In an embodiment, the second polymer layer 18 C remaining on the metal pad 16 forms at least one polymer buffer 18 D which separates the two adjacent openings 19 b . The opening 19 c is formed in the second polymer layer 18 C within the second region 120 to expose a landing portion 18 P of the first polymer layer 18 B.

Referring to FIG. 3C , an under-bump metallization (UBM) layer 20 is formed on the resulted structure shown in FIG. 3B . The UBM layer 20 covers the second polymer layer 18 C, the connection portions 16 P of the metal pad 16 , and the landing portion 18 P of the first polymer layer 18 B. In at least one embodiment, the UBM layer 20 includes a diffusion barrier layer (not shown), which is formed of titanium, tantalum, titanium nitride, tantalum nitride, or the like. In some embodiments, the UBM layer 20 further includes a seed layer (not shown) formed on the diffusion barrier layer. The seed layer may be formed of copper, copper alloys that include silver, chromium, nickel, tin, gold, and combinations thereof.

Next, first metal stacks M 1 are formed on the UBM layer 20 over the connection portions 16 P. In an embodiment, the first metal stack M 1 including a first metal pillar 22 A, a first metal capping layer 24 A and a first solder capping layer 26 A is formed on the UBM layer 20 positioned directly over each connection portion 16 P within the first region 110 . The formation of the first metal stack M 1 is, for example through photoresist masking, photolithography, plating, and dry/wet etching processes. In at least one embodiment, the first metal pillar 22 A is intended to include a layer including substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, cobalt or zirconium. In at least one exemplary embodiment, the first metal pillar 22 A has a thickness T 22A of less than about 20 μm. In another exemplary embodiment, the thickness T 22A is of about 1 to about 20 μm, although the thickness may be greater or smaller.

The first metal capping layer 24 A is formed on top of the first metal pillar 22 A. The first metal capping layer 24 A can act as a barrier layer to prevent copper in the first metal pillar 22 A from diffusing into a bonding material, such as solder alloy, that is used to connect first substrate 10 to external features. The prevention of copper diffusion increases the reliability and bonding strength of the electronics package. In some embodiments, the first metal capping layer 24 A is a metallization layer which may include nickel, tin, tin-lead (SnPb), gold (Au), silver (Ag), palladium (Pd), Indium (In), platinum (Pt), nickel-palladium-gold (NiPdAu), nickel-gold (NiAu), other similar materials, or alloys. The first metal capping layer 24 A may be a multi-layered structure or a single-layered structure. In an embodiment, the first metal capping layer 24 A has a thickness T 24A of less than about 5 μm. In other embodiments, the thickness T 24A is between about 0.5 μm to about 3 μm.

The first solder capping layer 26 A is formed on top of the first metal capping layer 24 A. In some embodiments, the first solder capping layer 26 A is made of a lead-free solder material, such as Sn, SnAg, Sn—Pb, SnAgCu (with Cu weight percentage less than or equal to about 0.5%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, SnAgSb, and other similarly appropriate material by plating methods. In at least one embodiment, the first solder capping layer 26 A is formed with a controlled volume. In an embodiment, the first solder capping layer 26 A is formed of a controlled thickness T 26A less than about 10 μm. In another embodiment, the thickness T 26A is less than or equal to about 7 μm. In at least another embodiment, the thickness T 26A is controlled at a range between about 2 μm and about 7 μm.

Referring to FIG. 3D , a second metal stack M 2 is formed on the UBM layer 20 and positioned directly over the landing portions 18 P within the second region 120 . In an embodiment, the second metal stack M 2 includes a second metal pillar 22 D, a second metal capping layer 24 D and a second solder capping layer 26 D. The formation of the second metal stack M 2 is, for example through photoresist masking, photolithography, plating, and dry/wet etching processes. In at least one embodiment, the second metal pillar 22 D includes a layer including substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. In an embodiment, the second metal pillar 22 D has a thickness T 22D , which is less than the thickness T 22A of the first metal pillar 22 A. For example, the thickness T 22D , is less than 5 μm, although the thickness may be greater or smaller. In some embodiments, the ratio of T 22A to T 22D is about 1 to about 4 μm.

The second metal capping layer 24 D is formed on top of the second metal pillar 22 D. In some embodiments, the second metal capping layer 24 D is a metallization layer which may include nickel, tin, tin-lead (SnPb), gold (Au), silver (Ag), palladium (Pd), Indium (In), platinum (Pt), nickel-palladium-gold (NiPdAu), nickel-gold (NiAu), other similar materials, or alloys. The second metal capping layer 24 D may be a multi-layered structure or a single-layered structure. In an embodiment, the second metal capping layer 24 D has a thickness T 24D substantially equal to the thickness T 24A of the first metal capping layer 24 A. In an embodiment, the thickness T 24D is less than about 5 μm. For example, the thickness T 24D is between about 0.5 μm to about 3 μm.

The second solder capping layer 26 D is formed on top of the second metal capping layer 24 D. In some embodiments, the second solder capping layer 26 D is made of a lead-free solder material, such as Sn, SnAg, Sn—Pb, SnAgCu (with Cu weight percentage less than 0.3%), SnAgZn, SnZn, SnBi—In, Sn—In, Sn—Au, SnPb, SnCu, SnZnIn, SnAgSb, and other similarly appropriate material by plating methods. In an embodiment, the second solder capping layer 26 D is formed of a thickness T 26D greater than the thickness T 26A of the first solder capping layer 26 A. In some embodiments, the thickness T 26D is less than about 10 μm. In another embodiment, the thickness T 26D is less than or equal to about 7 μm. In at least another embodiment, the thickness T 26D is controlled at a range between about 2 μm and about 7 μm.

After the formation of the first metal stack M 1 and the second metal stack M 2 , exposed portions of the UBM layer 20 are removed. In some embodiments, the remaining portion of the UBM layer 20 underlying the first metal pillar 22 A is referred to as a first UBM layer 20 A, and the remaining portion of the UBM layer 20 underlying the second metal pillar 22 D is referred to as a second UBM layer 20 D. Accordingly, the first bump structure 28 A is the stack including the first UBM layer 20 A, the first metal pillar 22 A, the first metal capping layer 24 A and the first solder capping layer 26 A. The second bump structure 28 D is the stack including the second UBM layer 20 D, the second metal pillar 22 D, the second metal capping layer 24 D and the second solder capping layer 26 D. In an embodiment, the top surface 26 A T of the first solder capping layer 26 A is substantially leveled with the top surface 26 D T of the second solder capping layer 26 D by controlling the thickness T 22D of the second metal pillar 22 D and the thickness T 26D of the second solder capping layer 26 D. For example, the gap between the top surface 26 A T and the top surface 26 D T can be controlled at ranges of about 0 to about 5 μm, about 0 to about 3 μm or about 0 to about 1 μm. As depicted in FIG. 3D , the first bump structure 28 A has a first bump height H 1 that is measured from the bottom surface 20 A B of the first UBM layer 20 A to the top surface 26 A T of the first solder capping layer 26 A. The second bump structure 28 D has a second bump height H 2 that is measured from the bottom surface 20 D B of the second UBM layer 20 D to the top surface 26 D T of the second solder capping layer 26 D. Since the second bump structure 28 D is positioned on the layers 18 A and 18 B, the first bump height H 1 is greater than the second bump height H 2 according to an embodiment. For example, the difference between the first bump height H 1 and the second bump height H 2 is at the range between about 1 nm and about 20 nm. By controlling the thickness of the metal pillars 22 A and 22 D in different regions 110 and 120 , the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is substantially leveled with the top surface 24 D T of the second metal capping layer 24 D.

In some embodiments, the first substrate 10 includes a number of chip regions that are sawed and separated from each other to form individual chips 100 A in accordance with some embodiments. FIG. 4 depicts in a cross-sectional view of a package structure 300 A with the chip 100 A bonded on a second substrate 200 in accordance with some embodiments. The second substrate 200 may be a semiconductor wafer, a portion of a semiconductor wafer, a semiconductor chip, a package substrate, or a circuit board. In some embodiments, the second substrate 200 includes silicon, gallium arsenide, silicon on insulator, glass, ceramic, plastic, organic materials, tape film, or other supporting materials. In some embodiments, the second substrate 200 also includes passive devices such as resistors, capacitors, inductors and the like, or active devices such as transistors. In some embodiments, the second substrate 200 includes through vias 202 as shown in FIG. 4 . The through vias 202 can be formed of copper, copper alloy or other conductive materials according to some embodiments. In an embodiment, the second substrate 200 functions as an interposer for interconnecting at least one integrated circuit chip to another chip, wafer or substrate. In some embodiments, the second substrate 200 includes a plurality of first contact pads 204 on a first side 200 S 1 , a first dielectric layer 206 on the first side 200 S 1 and covering portions of the contact pads 204 , and a plurality of connectors 208 A and 208 B landing on the exposed portions of the first contact pads 204 respectively. The connectors 208 A and 208 B can be formed of metal stacks with the same materials, and a uniform lateral dimension according to some embodiments. In an embodiment, the connector 208 A or 208 B includes a metal pillar formed of copper or copper alloy. In some embodiments, the connector 208 A or 208 B also includes at least one metal capping layer formed of nickel, gold, or solder on the metal pillar. In some embodiments, the second substrate 200 also includes a plurality of second contact pads 210 on a second side 200 S 2 opposite to the first side 200 S 1 , a second dielectric layer 212 on the second side 200 S 2 and covering portions of the second contact pads 210 , and a plurality of connectors 214 placed on the exposed portions of the second contact pads 210 respectively. In some embodiments, the connectors 214 are solder balls to form a connection between the second substrate and the underlying substrate (not shown).

The package structure 300 A in FIG. 4 shows the chip 100 bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B on the second substrate 200 . By solder reflowing process, a first solder joint region 302 is formed between the first bump structure 28 A and the first connector 208 A, and a second solder joint region 304 is formed between the second bump structure 28 D and the second connector 208 B. The thickness T 302 of the first solder joint region 302 may be varied depending on the volume of the first solder capping layer 26 A and the volume of solder material on the first connector 208 A, and the thickness T 304 of the second solder joint region 304 may be varied depending on the volume of the second solder capping layer 26 D and the volume of solder material on the second connector 208 B. In an embodiment, the thickness T 304 of the second solder joint region 304 is greater than the thickness T 302 of the first solder joint region 302 . The distance between first substrate 10 and the second substrate 200 , is called the “standoff”. In some embodiments, an underfill material is applied to fill the space between the chip 100 and the second substrate 200 for preventing cracks in the solder joint regions. By controlling the heights of the bump structures 28 A and 28 D within the chip 100 A, variation of standoffs between the chip 100 A and the substrate 200 can be minimized, such that the standoffs become more uniform and the underfill formation process is controllable and repeatable. The exemplary chip packages described above involve chips on substrates with bump structures. However, in some embodiments, the application of bump structures is applied to chip packages involving chips on substrates without bump structures.

FIG. 5A is a cross-sectional view of bump structures on a semiconductor chip 100 B in accordance with some embodiments, and FIG. 5B is a cross-sectional view of a package structure 300 B with the semiconductor chip 100 B bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 1 ˜ 4 .

Referring to FIG. 5A , by controlling the thickness of the metal pillars 22 A and 22 D in different regions 110 and 120 on the chip 100 B, the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. Accordingly, the top surface 26 A T of the first solder capping layer 26 A is substantially leveled with the top surface 26 D T of the second solder capping layer 26 D. Since the first bump structure 28 A is positioned on the metal pad 16 and the second bump structure 28 D is positioned on the layers 18 A and 18 B, the first bump height H 1 is greater than the second bump height H 2 . In some embodiments, the thicknesses of layers in the bump structures 28 A and 28 D satisfy the following criteria. T 22A is greater than T 22D , T 24A is substantially equal to T 24D , and T 26A is substantially equal to T 26D . For example, the difference between T 22A and T 22D , is about 1 to about 20 μm. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is substantially leveled with the top surface 22 D T of the second metal pillar 22 D. Referring to FIG. 5B , the package structure 300 B shows the chip 100 B bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the first connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 304 of the second solder joint region 304 is substantially equal to the thickness T 302 of the first solder joint region 302 .

FIG. 6A is a cross-sectional view of bump structures on a semiconductor chip 100 C in accordance with some embodiments, and FIG. 6B is a cross-sectional view of a package structure 300 C with the semiconductor chip 100 C bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 1 ˜ 4 .

Referring to FIG. 6A , by controlling the thickness of the solder capping layers 26 A and 26 D in different regions 110 and 120 on the chip 100 C, the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. Accordingly, the top surface 26 A T of the first solder capping layer 26 A is substantially leveled with the top surface 26 D T of the second solder capping layer 26 D. In some embodiments, the bump heights and the thicknesses of layers in the bump structures 28 A and 28 D satisfy the following criteria. H 1 is greater than H 2 , T 22A is substantially equal to T 22D , T 24A is substantially equal to T 24D , and T 26A is greater than T 26D . For example, the ratio of T 26A to T 26D is at the range from about 1.5 to about 3. For another example, the difference between T 26A to T 26D is about 1 to about 10 μm. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is lower than the top surface 22 D T of the second metal pillar 22 D, and the top surface 24 A T of the first metal capping layer 24 A is lower than the top surface 24 D T of the second metal capping layer 24 D. Referring to FIG. 6B , the package structure 300 C shows the chip 100 C bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 302 of the first solder joint region 302 is greater than the thickness T 304 of the second solder joint region 304 . For example, the ratio of T 304 to T 302 is at the range from about 1.5 to about 3.

FIGS. 7A through 7C are cross-sectional views of intermediate stages in the manufacturing of bump structures in accordance with an embodiment. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 3A ˜ 3 D.

Referring to FIG. 7A , the formation of the passivation layer 18 includes forming the dielectric layer 18 A and then forming an opening in the dielectric layer 18 A such that a portion of the metal pad 16 is exposed. Next, the first polymer layer 18 B is formed on the dielectric layer 18 A and the exposed portion of the metal pad 16 followed by forming at least two openings 19 d in the first polymer layer 18 B. The second openings 19 d are formed in the first region 110 to expose portions of the metal pad 16 . In an embodiment, the first polymer layer 18 B remaining on the metal pad 16 forms at least one polymer buffer 18 D 1 which separating the two adjacent openings 19 d.

Referring to FIG. 7B , the second polymer layer 18 C is formed on the resulted structure shown in FIG. 7A , and then another openings 19 e and 19 c are formed in the second polymer layer 18 C in the first region 110 and the second region 120 . In some embodiments, at least two openings 19 e are formed within the two openings 19 d respectively to expose at least two connection portions 16 P of the metal pad 16 within the first region 110 . In an embodiment as depicted in FIG. 7B , the second polymer layer 18 C includes a portion 18 D 2 remaining on the polymer buffer 18 D 1 , which separates the two adjacent openings 19 e . In some embodiments, at least one opening 19 c is formed in the first region 110 to expose a landing portion 18 P of the first polymer layer 18 B.

Next, shown in FIG. 7C , the bump structures 28 A and 28 D are formed on the connection portions 16 P and the landing portion 18 P respectively. The first bump structures 28 A are formed on the connection portions 16 P and a second bump structure 28 D is formed on the landing portion 18 P of the second polymer layer 18 C. In an embodiment, the first bump structure 28 A includes the first UBM layer 20 A, the first metal pillar 22 A, the first metal capping layer 24 A and the first solder capping layer 26 A. In an embodiment, the second bump structure 28 D includes the second UBM layer 20 D, the second metal pillar 22 D, the second metal capping layer 24 D and the second solder capping layer 26 D. By controlling the thickness of the metal pillars 22 A and 22 D in different regions 110 and 120 , the top surface of the first bump structure 28 A is substantially leveled with the top surface of the second bump structures 28 D. Since the first bump structure 28 A is positioned on the metal pad 16 and the second bump structure 28 D is positioned over the layers 18 A and 18 B, the first bump height H 1 is greater than the second bump height H 2 . In some embodiments, the thicknesses of layers in the bump structures 28 A and 28 D satisfy the followings. T 22A is greater than T 22D , T 24D is substantially equal to T 24D , and T 26A is less than T 26D . For example, the difference between T 22A and T 22D , is about 1 to about 20 μm. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is substantially leveled with the top surface 24 D T of the second metal capping layer 24 D.

In some embodiments, the first substrate 10 includes a number of chip regions that are sawed and separated from each other to form individual chips 100 D in accordance with some embodiments. FIG. 8 depicts in a cross-sectional view a package structure 300 D with the chip 100 D bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIG. 4 . The package structure 300 D shows the chip 100 D bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 304 of the second solder joint region 304 is greater than the thickness T 302 of the first solder joint region 302 .

FIG. 9A is a cross-sectional view of bump structures on a semiconductor chip 100 E in accordance with some embodiments, and FIG. 9B is a cross-sectional view of a package structure 300 E with the semiconductor chip 100 E bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 7 ˜ 8 .

Referring to FIG. 9A , the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. In an embodiment, the top surface 26 A T of the first solder capping layer 26 A is substantially leveled with the top surface 26 D T of the second solder capping layer 26 D. In some embodiments, the bump heights and thicknesses of layers in the bump structures 28 A and 28 D satisfy the following criteria. H 1 is greater than H 2 , T 22A is greater than T 22D , T 24A is substantially equal to T 24D , and T 26A is substantially equal to T 26D . For example, the difference between T 22A and T 22D , is about 1 to about 20 μm. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is substantially leveled with the top surface 22 D T of the second metal pillar 22 D. Referring to FIG. 9B , in the package structure 300 E, the chip 100 E is bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 304 of the second solder joint region 304 is substantially equal to the thickness T 302 of the first solder joint region 302 .

FIG. 10A is a cross-sectional view of bump structures on a semiconductor chip 100 F in accordance with some embodiments, and FIG. 10B is a cross-sectional view of a package structure 300 F with the semiconductor chip 100 F bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 7 ˜ 8 .

Referring to FIG. 10A , the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. In an embodiment, the top surface 26 A T of the first solder capping layer 26 A is substantially leveled with the top surface 26 D T of the second solder capping layer 26 D. In some embodiments, the bump heights and thicknesses of layers in the bump structures 28 A and 28 D satisfy the following criteria. H 1 is greater than H 2 , T 22A is substantially equal to T 22D , T 24A is substantially equal to T 24D , and T 26A is greater than T 26D . For example, the ratio of T 26A to T 26D is at the range from about 1.5 to about 3. For another example, the difference between T 26A to T 26D is about 1 to about 10 μm. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is lower than the top surface 22 D T of the second metal pillar 22 D, and the top surface 24 A T of the first metal capping layer 24 A is lower than the top surface 24 D T of the second metal capping layer 24 D. Referring to FIG. 10B , in the package structure 300 F, the chip 100 F is bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 302 of the first solder joint region 302 is greater than the thickness T 304 of the second solder joint region 304 . For example, the ratio of T 304 to T 302 is at the range from about 1.5 to about 3.

FIGS. 11A through 11B are cross-sectional views of intermediate stages in the manufacturing of bump structures in accordance with an embodiment. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 3A ˜ 3 D.

Referring to FIG. 11A , the formation of the passivation layer 18 includes forming the dielectric layer 18 A and the first polymer layer 18 B and then forming an opening 19 a passing through the layers 18 A and 18 B such that a connection portions 16 P of the metal pad 16 are exposed. Next, as shown in FIG. 11B , the first bump structures 28 A are formed on the connection portions 16 P and the second bump structure 28 D is formed on a predetermined portion 18 P of the first polymer layer 18 B. By controlling the thickness of the metal pillars 22 A and 22 D in different regions 110 and 120 , the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. In some embodiments, the bump heights and thicknesses of layers in the bump structures 28 A and 28 D satisfy the following criteria. H 1 is greater than H 2 , T 22A is greater than T 22D , T 24A is substantially equal to T 24D , and T 26A is less than T 26D . In some embodiments, the top surface 22 A T of the first metal pillar 22 A is substantially leveled with the top surface 24 D T of the second metal capping layer 24 D.

The first substrate 10 includes a number of chip regions that are sawed and separated from each other to form individual chips 100 G in accordance with some embodiments. FIG. 12 depicts in a cross-sectional view of a package structure 300 G with the chip 100 G bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIG. 4 . In the package structure 300 G, the chip 100 G is bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 304 of the second solder joint region 304 is greater than the thickness T 302 of the first solder joint region 302 .

FIG. 13A is a cross-sectional view of bump structures on a semiconductor chip 100 H in accordance with some embodiments, and FIG. 13B is a cross-sectional view of a package structure 300 H with the semiconductor chip 100 H bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 11 ˜ 12 .

Referring to FIG. 13A , the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. In an embodiment, the top surface 26 A T of the first solder capping layer 26 A is substantially leveled with the top surface 26 D T of the second solder capping layer 26 D. In some embodiments, the bump heights and thicknesses of layers in the bump structures 28 A and 28 D satisfy the following criteria. H 1 is greater than H 2 , T 22A is greater than T 22D , T 24A is substantially equal to T 24D , and T 26A is substantially equal to T 26D . For example, the difference between T 22A and T 22D , is about 1˜20 μm. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is substantially leveled with the top surface 22 D T of the second metal pillar 22 D. Referring to FIG. 13B , the package structure 300 H shows the chip 100 E bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 304 of the second solder joint region 304 is substantially equal to the thickness T 302 of the first solder joint region 302 .

FIG. 14A is a cross-sectional view of bump structures on a semiconductor chip 100 I in accordance with some embodiments, and FIG. 14B is a cross-sectional view of a package structure 300 I with the semiconductor chip 100 I bonded to the second substrate 200 in accordance with some embodiments. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 11 ˜ 12 .

Referring to FIG. 14A , the top of the first bump structure 28 A is substantially leveled with the top of the second bump structures 28 D. In an embodiment, the top surface 26 A T of the first solder capping layer 26 A is substantially leveled with the top surface 26 D T of the second solder capping layer 26 D. In some embodiments, the bump heights and thicknesses of layers in the bump structures 28 A and 28 D satisfy the following criteria. H 1 is greater than H 2 T 22A is substantially equal to T 22D , T 24A is substantially equal to T 24D , and T 26A is greater than T 26D . For example, the ratio of T 26A to T 26D is at the range from about 1.5 to about 3. For another example, the difference between T 26A to T 26D is about 1 to about 10 μm. In some embodiments, the top surface 22 A T of the first metal pillar 22 A is lower than the top surface 22 D T of the second metal pillar 22 D, and the top surface 24 A T of the first metal capping layer 24 A is lower than the top surface 24 D T of the second metal capping layer 24 D. Referring to FIG. 14B , the package structure 300 I shows the chip 100 I bonded to the second substrate 200 by connecting the bumps structures 28 A and 28 D on the first substrate 10 to the connectors 208 A and 208 B, respectively, on the second substrate 200 . In an embodiment, the thickness T 302 of the first solder joint region 302 is greater than the thickness T 304 of the second solder joint region 304 . For example, the ratio of T 304 to T 302 is at the range from about 1.5 to about 3.

According to some embodiments, a package structure includes a first substrate bonded to a second substrate. The first substrate has a first region and a second region and includes a metal pad overlying the first substrate in the first region, a first metal pillar overlying the metal pad, a passivation layer overlying the first substrate in the second region, and a second metal pillar overlying the passivation layer in the second region. The second substrate includes a first connector and a second connector. The first substrate is bonded to the second substrate, in which a first solder joint region is formed between the first metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.

According to some embodiments, a package structure includes a first substrate bonded to a second substrate. The first substrate has a first region and a second region and includes a metal pad overlying the first substrate in the first region, a first metal pillar overlying and electrically connected to the metal pad, a passivation layer overlying the first substrate in the second region, and a second metal pillar overlying the passivation layer in the second region. The second substrate includes a first connector and a second connector. The first substrate is bonded to the second substrate, in which a first solder joint region is formed between the first metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first solder joint region is greater than the thickness of the second solder joint region.

According to some embodiments, a method of forming bump structures on a first region and a second region of a semiconductor substrate, including: forming a metal pad overlying the first region of semiconductor substrate; forming a passivation layer overlying the metal pad and the semiconductor substrate; patterning the passivation layer to expose a portion of the metal pad; forming an under-bump metallization (UBM) layer on the passivation layer and the exposed portion of the metal pad; forming a first metal pillar on the UBM layer over the exposed portion of the metal pad; and forming a second metal pillar on the UBM layer over the passivation layer within the second region. The thickness of the first metal pillar is greater than or equal to the thickness of the second metal pillar.

In some embodiments, a method is provided for forming bump structures on a first region and a second region of a semiconductor substrate. The method includes forming a metal pad overlying the first region of semiconductor substrate;

forming a passivation layer overlying the metal pad and the semiconductor substrate in the first region and the second region, and patterning the passivation layer to expose a portion of the metal pad. The method further includes forming an under-bump metallization (UBM) layer on the passivation layer and the exposed portion of the metal pad, and forming a first metal pillar on the UBM layer over the exposed portion of the metal pad. In addition, the method includes forming a second metal pillar on the UBM layer over the passivation layer in the second region. wherein the thickness of the first metal pillar is greater than or equal to the thickness of the second metal pillar.

In yet another embodiment, provided is a method for forming bump structures on a first region and a second region of a semiconductor substrate, including forming a metal pad overlying the first region of semiconductor substrate. The method further includes forming a passivation layer overlying the metal pad and the semiconductor substrate in the first region and the second region, and patterning the passivation layer to expose a portion of the metal pad. Further method steps include forming a first metal pillar having a first thickness and extending through the passivation layer and contacting the exposed portion of the metal pad, and forming a second metal pillar having a second thickness less than or equal to the first thickness and having a bottommost surface forming an interface with a topmost surface of the passivation layer in the second region.

Another method embodiment includes forming a metal pad overlying a first region of a semiconductor substrate, and forming a passivation layer overlying the metal pad and the semiconductor substrate in the first region and a second region. The method further includes patterning the passivation layer to expose a portion of the metal pad, and forming a first metal pillar having a first thickness and extending through the passivation layer and contacting the exposed portion of the metal pad. A second metal pillar having a second thickness less than or equal to the first thickness and having a bottommost substantially coplanar with a topmost surface of the passivation layer in the second region is also formed and the method includes bonding a first connector of a second substrate to the first metal pillar and bonding a second connector of the second substrate to the second metal pillar.

While the present disclosure has been particularly shown and described with reference to example embodiments thereof, a skilled person in the art will appreciate that there can be many embodiment variations of this disclosure. Although the embodiments and their features have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments.

The above method embodiments show exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiment of the disclosure. Embodiments that combine different claims and/or different embodiments are within scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure.