Inventor

Po-Hao Tsai

Inventor

Zhongli City, TW

Overview

2004–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 137 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%

H01LSemiconductor devices35%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%

H10DInorganic electric semiconductor devices3%

B23KSoldering or unsoldering1%

H01QAntennas, i.e. radio aerials1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

B29CShaping or joining of plastics0%

B29LIndexing scheme associated with subclass b29c, relating to particular articles0%

B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems0%

PatentTitleYear

11,114,313Wafer level mold chase2021 11,114,311Chip package structure and method for forming the same2021 11,114,405Semiconductor package structure with twinned copper2021 11,107,798Semiconductor packages and methods of forming the same2021 11,101,214Package structure with dam structure and method for forming the same2021 11,094,625Semiconductor package with improved interposer structure2021 11,094,639Semiconductor package2021 11,075,168InFO-POP structures with TIVs having cavities2021 11,075,151Fan-out package with controllable standoff2021 11,069,673Semiconductor package and manufacturing method thereof2021 11,062,997Method for forming chip package structure2021 11,062,987Semiconductor device2021 11,063,007Semiconductor device and method of manufacture2021 11,056,471Semiconductor device and method of manufacture2021 10,985,100Chip package with recessed interposer substrate2021 10,971,461Semiconductor device and method of manufacture2021 10,937,742Package and manufacturing method thereof2021 10,879,194Semiconductor device package and method of manufacturing the same2020 10,872,850Package structure and method of forming thereof2020 10,854,563Device, semiconductor package and method of manufacturing semiconductor package2020 10,840,218Semiconductor device and method of manufacture2020 10,818,607Semiconductor device and method of manufacture2020 10,818,583Semiconductor devices, methods of manufacture thereof, and semiconductor device packages2020 10,804,247Chip package structure with conductive shielding film2020 10,804,254Fan-out package with cavity substrate2020 10,790,162Integrated circuit package and method2020 10,784,123Integrated circuit packages and methods of forming same2020 10,763,132Release film as isolation film in package2020 10,741,520Method of controlling bump height variation2020 10,720,403Integrated fan-out package structures with recesses in molding compound2020 10,672,752Semiconductor package and manufacturing method thereof2020 10,665,559Device, semiconductor package and method of manufacturing semiconductor package2020 10,658,347Semiconductor packages and methods of forming the same2020 10,636,775Package structure and manufacturing method thereof2020 10,622,297Semiconductor device and method2020 10,553,569Multi-die structure and method for forming same2020 10,541,213Backside redistribution layer (RDL) structure2020 10,535,614Package and manufacturing method thereof2020 10,535,591Semiconductor device and method of manufacturing the same2020 10,535,627Printing module, printing method and system of forming a printed structure2020 10,529,673Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices2020 10,522,476Package structure, integrated fan-out package and method of fabricating the same2019 10,522,496Method for a stacked and bonded semiconductor device2019 10,515,827Method for forming chip package with recessed interposer substrate2019 10,515,923Method for forming semiconductor package structure with twinned copper layer2019 10,515,904Method for forming chip package structure2019 10,515,901InFO-POP structures with TIVs having cavities2019 10,515,937Semiconductor device and method of manufacture2019 10,515,875Interconnect structure for package-on-package devices2019 10,468,339Heterogeneous fan-out structure and method of manufacture2019 10,361,161Semiconductor device and method of manufacture2019 10,354,982Integrated fan-out structure with guiding trenches in buffer layer2019 10,290,610PoP device and method of forming the same2019 10,276,511Package and manufacturing method thereof2019 10,269,587Integrated circuit packages and methods of forming same2019 10,269,778Package on package (PoP) bonding structures2019 10,269,685Interconnect structure for package-on-package devices2019 10,204,889Package structure and method of forming thereof2019 10,170,341Release film as isolation film in package2019 10,170,451Semiconductor device method of manufacture2019 10,163,875Method for forming chip package structure with adhesive layer2018 10,163,872Semiconductor packages and methods of forming the same2018 10,163,848Semiconductor package2018 10,163,813Chip package structure including redistribution structure and conductive shielding film2018 10,157,888Integrated fan-out packages and methods of forming the same2018 10,141,253Semiconductor device and method2018 10,134,719Semiconductor package and manufacturing method thereof2018 10,128,226Mechanisms for forming package structure2018 10,115,675Packaged semiconductor device and method of fabricating a packaged semiconductor device2018 10,109,573Packaged semiconductor devices and packaging devices and methods2018 10,103,125Chip package structure and method for forming the same2018 10,103,132Semiconductor device and method of manufactures2018 10,090,253Semiconductor package2018 10,083,946Integrated fan-out structure with guiding trenches in buffer layer2018 10,062,662Integrated fan-out package structures with recesses in molding compound2018 10,049,989Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices2018 10,008,485Semiconductor device and method of manufacture2018 9,953,949Through package via (TPV)2018 9,953,948Pillar design for conductive bump2018 9,953,955Integrated fan-out package structures with recesses in molding compound2018 9,929,128'Chip package structure with adhesive layer'2018 9,929,108'Backside redistribution layer (RDL) structure'2018 9,922,903'Interconnect structure for package-on-package devices and a method of fabricating'2018 9,842,826'Semiconductor device and method of manufacture'2017 9,818,697'Semiconductor package manufacturing method'2017 9,799,581'Integrated fan-out structure with openings in buffer layer'2017 9,773,724'Semiconductor devices, methods of manufacture thereof, and semiconductor device packages'2017 9,761,566'Multi-die structure and method of forming same'2017 9,728,496'Packaged semiconductor devices and packaging devices and methods'2017 9,728,508'Semiconductor device and method of manufacture'2017 9,698,135'Mechanisms for forming package structure'2017 9,673,181'Package on package (PoP) bonding structures'2017 9,646,918'Semiconductor device and method'2017 9,646,942'Mechanisms for controlling bump height variation'2017 9,633,934'Semicondutor device and method of manufacture'2017 9,633,895'Integrated fan-out structure with guiding trenches in buffer layer'2017 9,583,420'Semiconductor device and method of manufactures'2017 9,570,401'Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices'2017 9,553,059'Backside redistribution layer (RDL) structure'2017 9,543,170'Semiconductor packages and methods of forming the same'2017 9,508,666'Packaging structures and methods with a metal pillar'2016 9,496,235'Pillar design for conductive bump'2016 9,478,498'Through package via (TPV)'2016 9,460,987'Interconnect structure for package-on-package devices and a method of fabricating'2016 9,455,211'Integrated fan-out structure with openings in buffer layer'2016 9,425,121'Integrated fan-out structure with guiding trenches in buffer layer'2016 9,406,588'Semiconductor package and manufacturing method thereof'2016 9,368,438'Package on package (PoP) bonding structures'2016 9,355,977'Bump structures for semiconductor package'2016 9,355,973'Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices'2016 9,349,701'Self-aligning conductive bump structure and method of fabrication'2016 9,318,455'Method of forming a plurality of bumps on a substrate and method of forming a chip package'2016 9,252,065'Mechanisms for forming package structure'2016 9,219,016'Structure design for 3DIC testing'2015 9,159,678'Semiconductor device and manufacturing method thereof'2015 9,142,432'Integrated fan-out package structures with recesses in molding compound'2015 9,111,821'Packaged semiconductor devices and packaging devices and methods'2015 9,111,914'Fan out package, semiconductor device and manufacturing method thereof'2015 9,093,314'Copper bump structures having sidewall protection layers'2015 9,048,222'Method of fabricating interconnect structure for package-on-package devices'2015 9,024,438'Self-aligning conductive bump structure and method of making the same'2015 8,970,035'Bump structures for semiconductor package'2015 8,953,336'Surface metal wiring structure for an IC substrate'2015 8,952,544'Semiconductor device and manufacturing method thereof'2015 8,941,244'Semiconductor device and manufacturing method thereof'2015 8,922,004'Copper bump structures having sidewall protection layers'2014 8,901,735'Connector design for packaging integrated circuits'2014 8,877,554'Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices'2014 8,816,498'Pillar design for conductive bump'2014 8,778,738'Packaged semiconductor devices and packaging devices and methods'2014 8,664,760'Connector design for packaging integrated circuits'2014 8,653,658'Planarized bumps for underfill control'2014 8,610,285'3D IC packaging structures and methods with a metal pillar'2013 8,455,995'TSVs with different sizes in interposers for bonding dies'2013 7,125,795'Fabrication method for microstructures with high aspect ratios'2006 6,804,443'Test structure and method of step coverage for optical waveguide production'2004 6,737,307'Method for forming amorphous silicon film on single crystal silicon and structure formed'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2006Based in Hsinchu, TW· patent location history

2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (24)· patent assignee history

2013–2017Patents assigned to LIN JING-CHENG (10)· patent assignee history

2013–2017Patents assigned to TSAI PO-HAO (10)· patent assignee history

2013–2015Patents assigned to HUANG CHENG-LIN (5)· patent assignee history

2013–2021Based in Zhongli City, TW· patent location history

2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (109)· patent assignee history

2015–2021Based in Taoyuan County, TW· patent location history

2015Based in Yaoyuan, TW· patent location history

2018–2021Based in Taoyuan, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	109	2015–2021
TAIWAN SEMICONDUCTOR MFG	24	2013–2016
LIN JING-CHENG	10	2013–2017
TSAI PO-HAOself	10	2013–2017
HUANG CHENG-LIN	5	2013–2015

Locations

Location	Patents	Span
Zhongli City, TW	89	2013–2021
Taoyuan, TW	23	2018–2021
Taoyuan County, TW	13	2015–2021
Hsinchu, TW	2	2004–2006
Yaoyuan, TW	1	2015