Fishbone structure enhancing spacing with adjacent conductive line in power network

Typically, a power network of an integrated circuit (IC) chip includes a plurality of layers of conductive lines which are arranged as, for example, a mesh network, and a plurality of interlayer vias that interconnect different layers of conductive lines. In the mesh network, conductive lines in an upper layer such as a metal layer M 7 cross over conductive lines in a lower layer such as a metal layer M 2 . Corresponding to where the conductive lines in the upper layer overlap with the conductive lines in the lower layer, interlayer vias and conductive segments in intermediate metal layers are disposed.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a schematic top-view diagram of a power network in accordance with some embodiments.

FIG. 1B is a schematic cross-sectional view diagram of the power network along line A-A′ in FIG. 1A .

FIG. 2A is a schematic perspective-view diagram of a fishbone structure in FIG. 1B in accordance with some embodiments.

FIG. 2B is a schematic top-view diagram of a structure which includes the fishbone structure in FIG. 2A and adjacent conductive lines for which a wide metal spacing rule does not apply in accordance with some embodiments.

FIG. 3 is a schematic top-view diagram of a structure for which the wide metal spacing rule is applied.

FIG. 4A is a schematic perspective-view diagram of a fishbone structure in FIG. 1B in accordance with some embodiments.

FIG. 4B is a schematic top-view diagram of a structure which includes the fishbone structure in FIG. 4A and adjacent conductive lines for which the wide metal spacing rule triggered by non-prefer direction routing does not apply in accordance with some embodiments.

FIG. 5 is a schematic top-view diagram of a structure for which the wide metal spacing rule is triggered by non-prefer direction routing.

FIG. 6 is a schematic top-view diagram of a staggered fishbone structure in accordance with some embodiments.

FIG. 7 is a schematic top-view diagram of a fishbone structure with a thickened spine in accordance with some embodiments.

FIG. 8 is a schematic top-view diagram of a fishbone structure with a thickened spine in accordance with other embodiments.

FIG. 9 is a schematic top-view diagram of a fishbone structure with multi-rows of spine in accordance with some embodiments.

FIG. 10 is a schematic top-view diagram of a fishbone structure that has a rotated orientation in accordance with some embodiments.

FIG. 11 is a schematic top-view diagram of a fishbone structure that has a wider spacing between conductive segments in the metal layer M 3 in accordance with some embodiments.

FIG. 12 is a flow diagram of a method for generating a structure in FIG. 2B that includes the fishbone structure in FIG. 2A in accordance with some embodiments.

FIGS. 13A to 13F are schematic top-view diagrams of layouts illustrating operations for generating the structure in FIG. 2B that includes the fishbone structure in FIG. 2A in accordance with some embodiments.

FIG. 14 is a block diagram of a hardware system for implementing method embodiments described with reference to FIGS. 12 and 13A-13F in accordance with some embodiments.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “top”, “bottom”, “front”, “back”, “left”, “right”, “horizontal”, “vertical” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

FIG. 1A is a schematic top-view diagram of a power network 100 in accordance with some embodiments. FIG. 1B is a schematic cross-sectional view diagram of the power network 100 along line A-A′ in FIG. 1A . Referring to both FIGS. 1A and 1B , in some embodiments, the power network 100 includes a plurality of conductive lines (not shown) in a metal layer M 1 , a plurality of conductive lines 122 in a metal layer M 2 , a plurality of conductive segments 118 in a metal layer M 3 , a plurality of conductive segments 114 in a metal layer M 4 , a plurality of conductive segments 110 in a metal layer M 5 , a plurality of conductive lines 106 in a metal layer M 6 and a plurality of conductive lines 102 in a metal layer M 7 . The power network 100 further includes a plurality of interlayer vias 124 (not shown) between the metal layers M 1 and M 2 , a plurality of interlayer vias 120 between the metal layers M 2 and M 3 , a plurality of interlayer vias 116 between the metal layers M 3 and M 4 , a plurality of interlayer vias 112 between the metal layers M 4 and M 5 , a plurality of interlayer vias 108 between the metal layers M 5 and M 6 , and a plurality of interlayer vias 104 between the metal layers M 6 and M 7 . Each layer M 1 , M 2 . . . or M 7 of the power network 100 includes alternatively arranged VDD lines and VSS lines. The interlayer vias 124 , 120 , 116 , 112 , 108 and 104 couple corresponding VDD lines in the layers M 1 , M 2 . . . and M 7 , and couple corresponding VSS lines in the layers M 1 , M 2 . . . and M 7 .

Referring to FIG. 1A , in some embodiments, the conductive lines 102 in the metal layer M 7 are running in a Y direction. The conductive lines 122 in the metal layer M 2 are running in an X direction. The X direction is substantially vertical to the Y direction. The conductive lines 102 cross over the conductive lines 122 .

Referring to FIG. 1B , suppose a designer decides that the power network 100 is sufficiently dense without the complete network in the metal layers M 3 , M 4 and M 5 . The conductive lines 106 in the metal layer M 6 running in the X direction are formed, and interlayer vias 104 between the metal layers M 7 and M 6 are formed at where the conductive lines 102 in the metal layer M 7 overlap with the conductive lines 106 in the metal layer M 6 . Further, in order to connect the conductive lines 106 in the metal layer M 6 to the conductive lines 122 in the metal layer M 2 , the conductive segments 110 , 114 and 118 in the metal layers M 5 , M 4 and M 3 , respectively, and the interlayer vias 108 , 112 , 116 and 120 between the metal layers M 6 and M 5 , M 5 and M 4 , M 4 and M 3 , and M 3 and M 2 , respectively, are formed at locations corresponding to where the conductive lines 102 in the metal layer M 7 overlap with the conductive lines 122 in the metal layer M 2 . The conductive segments 110 in the metal layer M 5 are running in the Y direction. The conductive segments 114 in the metal layer M 4 are running in the X direction. The conductive segments 118 in the metal layer M 3 are running in the Y direction. In FIG. 1B , corresponding to some places where the conductive lines 102 overlap with the conductive lines 122 , a fishbone structure 200 is formed by a portion of conductive segments 118 , the conductive line 122 and a portion of the interlayer vias 120 , and a fishbone structure 400 is formed by a portion of conductive segments 110 , one of the conductive segments 114 and a portion of the interlayer vias 112 .

FIG. 2A is a schematic perspective-view diagram of the fishbone structure 200 in FIG. 1B in accordance with some embodiments. The fishbone structure 200 includes the conductive line 122 (only a portion is shown) in the metal layer M 2 running in the X direction, the conductive segments 118 A, 118 B and 118 C in the metal layer M 3 running in the Y direction, and the interlayer vias 120 A, 120 B and 120 C disposed at where the conductive segments 118 A, 118 B and 118 C overlap with the conductive line 122 . The conductive line 122 serves as a spine of the fishbone structure 200 and the conductive segments 118 A, 118 B and 118 C serve as ribs of the fishbone structure 200 .

FIG. 2B is a schematic top-view diagram of a structure 210 which includes the fishbone structure 200 in FIG. 2A and adjacent conductive lines 126 and 128 for which a wide metal spacing rule does not apply in accordance with some embodiments. For advanced technology nodes such as 16 nm and beyond, the wide metal spacing rule requires routing tracks adjacent to a conductive line in a lower metal layer to be blocked when a conductive line or conductive segment in an upper metal layer that overlaps with the conductive line in the lower metal layer has a wide width, such as the width greater than or equal to the minimum width of the upper metal layer. For example, when a traditional powerplan structure is employed in advanced technology nodes such as 16 nm and beyond to form the connection at where the metal line 102 in the metal layer M 7 is overlapped with the metal line 122 in the metal layer M 2 as shown in FIG. 1B , routing tracks at where the conductive lines 126 and 128 reside are blocked. In present embodiments, each of the conductive segments 118 A, 118 B and 118 C in the metal layer M 3 has a width W 1 such that the conductive line 122 has a unit spacing S 1 with adjacent conductive lines 126 and 128 in the metal layer M 2 . In other words, the width W 1 of the conductive segments 118 A, 118 B and 118 C does not cause the wide metal spacing rule to be triggered during routing, and therefore, the conductive lines 126 and 128 that has the unit spacing S 1 with the conductive line 122 can be formed. In some embodiments, the width W 1 is the minimum dimension of the layers with VIA layouts. The interlayer vias 120 A, 120 B and 120 C are formed at where the conductive segments 118 A, 118 B and 118 C overlap with the conductive line 122 , respectively.

In comparison to FIG. 2B , FIG. 3 is a schematic top-view diagram of a structure 300 for which the wide metal spacing rule is applied. The structure 300 includes a conductive line 326 in the metal layer M 1 , conductive lines 322 and 328 in a metal layer M 2 , a conductive line 318 in the metal layer M 3 , and interlayer vias 320 A and 320 B between the metal layers M 1 and M 3 , and M 2 and M 3 , respectively. In the advanced technology nodes, the conductive line 326 in the metal layer M 1 and the conductive line 322 in the metal layer M 2 are in parallel to form double rails that increase a current flowing therethrough. As shown in FIG. 3 , the conductive line 326 in the metal layer M 1 has a wider width than the conductive line 322 in the metal layer M 2 . The widths of the conductive lines increase as the layers progress from a lower metal layer such as the metal layer M 2 to an upper metal layer such as the metal layer M 7 . When a connection between the metal layer M 7 and the metal layer M 1 is generated during routing, the conductive line in the metal layer M 7 is projected to the conductive line 326 in the metal layer M 1 and the conductive line 322 in the metal layer M 2 to determine a width of conductive segment in an intermediate layer and an area in the intermediate layer where interlayer vias will be disposed. For example, as the conductive line M 7 is projected to the conductive line 326 in the meta layer M 1 and the conductive line 322 in the metal layer M 2 , the conductive segment 318 in the metal layer M 3 is determined to have a wide width W 2 , and the interlayer vias 320 A and 320 B will be disposed within an area 330 where the conductive segment 318 in the metal layer M 3 overlap with the conductive line 326 in the metal layer M 1 . During routing, because of the wide width W 2 of the conductive segment 318 in the metal layer M 3 , routing tracks adjacent to the conductive line 322 in the metal layer M 2 are blocked for being subjected to the wide metal spacing rule. As a result, in the metal layer M 2 , the adjacent conductive line 328 is separated from the conductive line 322 by two unit spacings S 1 .

Referring to FIG. 2B , because the routing resources adjacent to the conductive line 122 in the metal layer M 2 are available for use, fewer routing detours due to insufficient routing resources will happen during generation of the signal lines. Therefore, performance and area of the chip on which the power network 100 (shown in FIG. 1A ) is configured will be improved.

FIG. 4A is a schematic perspective-view diagram of the fishbone structure 400 in FIG. 1B in accordance with some embodiments. The fishbone structure 400 includes the conductive segment 114 in the metal layer M 4 running in the X direction, the conductive segments 110 A, 110 B and 110 C in the metal layer M 5 running in the Y direction, and the interlayer vias 112 A, 112 B and 112 C disposed at where the conductive segments 110 A, 110 B and 110 C overlap with the conductive segment 114 . The conductive segment 114 serves as a spine of the fishbone structure 400 and the conductive segments 110 A, 110 B and 110 C serve as ribs of the fishbone structure 400 .

FIG. 4B is a schematic top-view diagram of a structure 410 which includes the fishbone structure 400 in FIG. 4A and adjacent conductive lines 426 , 428 , 430 and 432 for which the wide metal spacing rule triggered by non-prefer direction routing does not apply in accordance with some embodiments. For advanced technology node, the wide metal spacing rule further requires several routing tracks adjacent to a conductive line or segment in a metal layer to be blocked when the conductive line or segment in the metal layer has a wide width. The wide metal lines on non-prefer direction induces larger spacing than the metal lines on prefer direction. Also, in advanced technology nodes, a width of the conductive line or segment is defined to be a dimension of the conductive line or segment along a non-preferred direction of routing. In the present embodiments, each of the conductive segments 110 A, 110 B and 110 C in the metal layer M 5 are running in the Y direction, which is the preferred direction of the metal layer M 5 . A width W 3 of each of the conductive segments 110 A, 110 B and 110 C is along a non-preferred direction of the metal layer M 5 , which is the X direction. Because the conductive segment 110 A, 110 B or 110 C are routed in the prefer direction, the width W 3 is along the shorter side of the conductive segment 110 A, 110 B, or 110 C. In this way, the wide metal spacing rule does not apply. As a result, the two conductive lines 426 and 428 that have two unit spacings S 2 and one unit spacing S 2 with the conductive segment 110 A, respectively, and two conductive lines 430 and 432 that has one unit spacing S 2 and two unit spacings S 2 with the conductive segment 110 C, respectively, can be formed. The interlayer vias 112 A, 112 B and 112 C are formed at where the conductive segments 110 A, 110 B and 110 C overlap with the conductive segment 114 , respectively.

In comparison to FIG. 4B , FIG. 5 is a schematic top-view diagram of a structure 500 for which the wide metal spacing rule is triggered by non-prefer direction routing. The structure 500 includes a conductive segment 514 in the metal layer M 4 , a conductive segment 510 in the metal layer M 5 and interlayer vias 512 A, 512 B and 512 C between the metal layers M 4 and M 5 . When a connection between the metal layer M 7 and the metal layer M 2 is generated during routing, the conductive line in the metal layer M 7 is projected to the conductive line in the metal layer M 1 and the conductive line in the metal layer M 2 . Because of the wider width of the metal layer M 7 , projection of the metal layer M 7 can cause a conductive segment in a lower metal layer such as the metal layer M 5 to be routed in the non-prefer direction. In FIG. 5 , the prefer direction and the non-prefer direction of the metal layer M 5 is the Y direction and the X direction, respectively. The conductive segment 510 in the metal layer M 5 is routed in the non-prefer direction. A width W 4 of the conductive segment 510 is along the non-prefer direction of the metal layer M 5 and is therefore a longer side of the conductive segment 510 . Therefore, due to the wide metal spacing rule, the interlayer via 512 A has four unit spacings S 2 with an adjacent conductive line 526 , and the interlayer via 512 C has four unit spacings S 2 with an adjacent conductive line 528 . In other words, on both sides of the conductive line 510 , two routing tracks are blocked.

Referring to FIG. 4B , because the routing resources adjacent to the conductive segments 110 A and 110 C in the metal layer M 5 are available for use, fewer routing detours due to insufficient routing resources will happen during generation of signal line. Therefore, performance and area of the chip on which the power network 100 (shown in FIG. 1A ) will be improved.

FIG. 6 is a schematic top-view diagram of a staggered fishbone structure 600 in accordance with some embodiments. Compared to the fishbone structure 200 which has aligned conductive segments 118 A, 118 B and 118 C shown in FIG. 2A and elements of which also shown in FIG. 2B , the staggered fishbone structure 600 has conductive segments 618 A, 618 B and 618 C which are arranged in a staggered manner with respect to a conductive line 622 A. Interlayer vias 620 A, 620 B and 620 C are disposed between the conductive segments 618 A, 618 B and 618 C in the metal layer M 3 and the conductive line 622 A in the metal layer M 2 , respectively. Compared to the interlayer vias 120 A, 120 B and 120 C which are located at centers of the conductive segments 118 A, 118 B and 118 C, the interlayer via 620 A is located at a right portion of the conductive segment 618 A, the interlayer via 620 B is located at a left portion of the conductive segment 618 B and the interlayer via 620 C is located at a right portion of the conductive segment 618 C when viewing along the X direction.

FIG. 7 is a schematic top-view diagram of a fishbone structure 700 with a thickened spine in accordance with some embodiments. The fishbone structure 700 includes the conductive line 722 in the metal layer M 2 which serves as a spine of the fishbone structure 700 and the conductive segments 718 in the metal layer M 3 which serve as ribs of the fishbone structure 700 . The fishbone structure 700 further includes interlayer vias 720 and 728 for connecting the conductive line 722 to the conductive segments 718 . Compared to the spine of the fishbone structure 200 , the conductive line 122 , shown in FIGS. 2A and 2B , the spine of the fishbone structure 700 , the conductive line 722 , is thickened. Therefore, areas 726 where the conductive segments 718 overlap with the conductive line 722 are enlarged and the number of interlayer vias 720 and 728 disposed at each area 726 is increased. In some embodiments, each of the interlayer vias 720 and 728 has a square shape.

FIG. 8 is a schematic top-view diagram of a fishbone structure 800 with a thickened spine in accordance with other embodiments. Compared to the fishbone structure 700 in FIG. 7 , the fishbone structure 800 has interlayer vias 820 each of which are of a rectangular shape. The fishbone structure 800 includes the conductive line 822 in the metal layer M 2 which serves as a spine of the fishbone structure 800 and the conductive segments 818 in the metal layer M 3 which serve as ribs of the fishbone structure 800 . The fishbone structure 800 further includes interlayer vias 820 for connecting the conductive line 822 to the conductive segments 818 .

FIG. 9 is a schematic top-view diagram of a fishbone structure 900 with multi-rows of spine in accordance with some embodiments. Compared to the fishbone structure 200 which has one row of spine, the conductive line 122 , shown in FIG. 2A , and elements of which also shown in FIG. 2B , the fishbone structure 900 has two rows of spine, the conductive lines 922 A and 922 B. The fishbone structure 900 includes the conductive lines 922 A and 922 B in the metal layer M 2 which serve as a first spine and a second spine of the fishbone structure 900 , respectively, and the conductive segments 918 A, 918 B and 918 C in the metal layer M 3 which serves as ribs of the fishbone structure 900 . The fishbone structure 900 further includes interlayer vias 920 A, 920 B and 920 C for connecting the conductive line 922 A to the conductive segments 918 A, 918 B and 918 C, and interlayer vias 926 A, 926 B and 926 C for connecting the conductive line 922 B to the conductive segments 918 A, 918 B and 918 C.

FIG. 10 is a schematic top-view diagram of a fishbone structure 1000 that has a rotated orientation in accordance with some embodiments. Compared to the fishbone structure 200 that has the conductive line 122 running in the X direction and the conductive segments 118 A, 118 B and 118 C running in the Y direction shown in FIG. 2A and elements of which also shown in FIG. 2B , the fishbone structure 1000 has a conductive line 1022 running in the Y direction and conductive segments 1018 A, 1018 B and 1018 C running in the X direction. Therefore, the fishbone structure 1000 has the orientation which is rotated by 90° from the orientation of the fishbone structure 200 .

FIG. 11 is a schematic top-view diagram of a fishbone structure 1100 that has a wider spacing S 3 between conductive segments 1118 A and 1118 B in the metal layer M 3 in accordance with some embodiments. Compared to the conductive segments 118 A, 118 B and 118 C of the fishbone structure 200 (labeled in FIG. 2A ) that are separated by the spacing S 2 as shown in FIG. 2B , an adjacent pair of conductive segments 1118 A and 1118 B in the fish bone structure 1100 are separated by the spacing S 3 which is larger than the spacing S 2 .

FIG. 12 is a flow diagram of a method 1200 for generating a structure 210 in FIG. 2B that includes the fishbone structure 200 in FIG. 2A in accordance with some embodiments. In operation 1202 , a first conductive line in a first conductive layer running in a first direction is generated. In operation 1204 , a plurality of second conductive lines in a second conductive layer running in a second direction are generated. In operation 1206 , a plurality of interlayer vias interposed between the first conductive layer and the second conductive layer are generated at where the plurality of second conductive lines overlap with the first conductive line. In operation 1208 , for each of the plurality of second conductive lines, a portion of the second conductive line is removed to obtain a plurality of second conductive segments. In operation 1210 , a first adjacent conductive line is generated such that the first conductive line has a first unit spacing with the first adjacent conductive line in the first conductive layer.

FIGS. 13A to 13F are schematic top-view diagrams of layouts 1300 , 1310 , . . . and 1350 illustrating operations for generating the structure 210 in FIG. 2B that includes the fishbone structure 200 in FIG. 2A in accordance with some embodiments. Referring to FIG. 12 and FIG. 13A , in operation 1202 , a first conductive line 1322 in the first conductive layer M 2 running in a first direction, the X direction, is generated. During a routing process for the power network 100 in FIG. 1A , conductive lines such as a conductive line 1326 in the metal layer M 1 running in the X direction is first generated. A routing track 1332 in the metal layer M 2 is in parallel and aligned to the conductive line 1326 in the metal layer M 1 . Then, the conductive line 1322 in the metal layer M 2 running in the X direction is routed along the routing track 1334 . A width of the conductive line 1322 in the metal layer M 2 is smaller than that of the conductive line 1324 in the metal layer M 1 . The conductive line 1326 and the conductive line 1322 form double rails.

Referring to FIG. 12 and FIG. 13B , in operation 1204 , a plurality of conductive lines 1338 A, 1338 B and 1338 C in the second conductive layer M 3 running in a second direction, the Y direction, are generated. Suppose the designer decides that the power network is sufficiently dense without the metal layer M 3 . Compared to some approaches illustratively shown in FIG. 3 that generates the conductive segment 318 in the metal layer M 3 when the conductive line in the metal layer M 7 is projected to the conductive line 326 in the metal layer M 1 and the conductive line 322 in the metal layer M 2 , the conductive lines 1338 A, 1338 B and 1338 C are generated before layers such as M 4 , M 5 . . . and M 7 upper than the metal layer M 3 are generated. In this way, a width W 1 of each of the conductive lines 1338 A, 1338 B and 1338 C is not determined by the shape of the conductive line in the metal layer M 7 projected to the conductive line 1326 in the metal layer M 1 and the conductive line 1322 in the metal layer M 2 , and can be decreased to, for example, the minimum width.

Referring to FIG. 12 and FIG. 13C , in operation 1206 , a plurality of interlayer vias 1320 A, 1320 B and 1320 C interposed between the first conductive layer M 2 and the second conductive layer M 3 are generated at where the plurality of second conductive lines 1338 A, 1338 B and 1338 C overlap with the first conductive line 1322 . Compared to some approaches illustratively shown in FIG. 3 that generate the interlayer vias 320 A and 320 B when the conductive line in the metal layer M 7 is projected to the conductive line 326 in the metal layer M 1 and the conductive line 322 in the metal layer M 2 , the interlayer vias 1320 A, 1320 B and 1320 C are generated when the conductive lines 1338 A, 1338 B and 1338 C in the metal layer M 3 are projected to conductive line 1322 in the metal layer M 2 . In this way, each area where the interlayer via 1320 A, 1320 B or 1320 C is disposed is determined by a shape of the conductive line 1338 A, 1338 B or 1338 C in the metal layer M 3 projected to the conductive line 1322 in the metal layer M 2 . As described with reference to FIG. 13B , the width W 1 of the conductive line 1338 A, 1338 b or 1338 C is reduced for the width is not determined by the shape of the conductive line in the metal layer M 7 projected to the conductive line 1326 in the metal layer M 1 and the conductive line 1322 in the metal layer M 2 . Therefore, the area where the interlayer via 1320 A, 1320 B or 1320 C is disposed has a dimension corresponding to the reduced width.

Referring to FIG. 12 and FIGS. 13D and 13E , in operation 1208 , for each of the plurality of second conductive lines 1338 A, 1338 B and 1338 C (shown in FIG. 13C ), a portion of the second conductive line 1338 A, 1338 B or 1338 C is removed to obtain a plurality of second conductive segments 1318 A, 1318 B and 1318 C (shown in FIG. 13E ). The operation 1208 includes a first operation shown in FIG. 13D and a second operation shown in FIG. 13E . Suppose the designer decides that the power network is sufficiently dense without the complete network in the metal layer M 3 . In the first operation, for each of the plurality of conductive lines 1338 A, 1338 B and 1338 C, portions of the conductive line 1338 A, 1338 B or 1338 C on two sides of the interlayer via 1320 A, 1320 B or 1320 C are removed to obtain a conductive segment 1340 A, 1340 B or 1340 C. However, the remaining conductive segment 1340 A, 1340 B or 1340 C has an area that does not meet the minimum area design rule. Therefore, in the second operation, the area of each of the conductive segment 1340 A, 1340 B or 1340 C is supplemented so that the resulting conductive segment 1318 A, 1318 B or 1318 C meets the minimum area design rule.

Referring to FIG. 12 and FIG. 13F , in operation 1210 , a first adjacent conductive line 1328 or 1330 is generated such that the first conductive line 1322 has a first unit spacing S 1 with the first adjacent conductive line 1328 or 1330 in the first conductive layer M 2 . Because each of the conductive segments 1318 A, 1318 B and 1318 C has the reduced width W 1 , and each of the interlayer via 1320 A, 1320 B and 1320 C has a shape that conform to the area where the conductive segment 1318 A, 1318 B or 1318 C overlap with the conductive line 1322 , the wide metal spacing rule does not apply. Therefore, routing tracks 1332 and 1336 adjacent to the routing track 1334 along which the conductive line 1322 is routed are not blocked and are free to be used during routing of, for example, signal lines. The adjacent conductive lines 1328 or 1330 of the conductive line 1322 can be generated on the routing track 1332 or 1336 , respectively, and has the unit spacing S 1 with the conductive line 1322 . Because the routing resources adjacent to the conductive line 1322 in the metal layer M 2 are available for use, fewer routing detours due to insufficient routing resources will happen during generation of signal lines. Therefore, performance and area of the chip on which the method 1200 in FIG. 12 is performed will be improved.

Although FIG. 12 and FIGS. 13A to 13F are directed to the method 1200 for generating the layout for the structure 210 in FIG. 2B , the operations 1202 , 1204 to 1208 can also be used to generate the layout for the structure 410 in FIG. 4B . Referring to FIG. 4B , the method for generating the layout for the structure 410 further includes an operation of removing a portion of the first conductive line to obtain a first conductive segment 114 . Instead of the operation 1210 , the method for generating the layout for the structure 410 includes an operation of generating a second adjacent conductive line 428 such that one of the plurality of second conductive segments, such as the second conductive segment 110 A on one side of the plurality of second conductive segments 110 A, 110 B and 110 C, has a second unit spacing S 2 with the second adjacent conductive line 428 in the second conductive layer.

FIG. 14 is a block diagram of a hardware system 1400 for implementing method embodiments described with reference to FIGS. 12 and 13A-13F in accordance with some embodiments. The system 1400 includes at least one processor 1402 , a network interface 1404 , an input and output (I/O) device 1406 , a storage 1408 , a memory 1412 , and a bus 1410 . The bus 1410 couples the network interface 1404 , the I/O device 1406 , the storage 1408 and the memory 1412 to the processor 1402 .

In some embodiments, the memory 1412 comprises a random access memory (RAM) and/or other volatile storage device and/or read only memory (ROM) and/or other non-volatile storage device. The memory 1412 includes a kernel 1414 and user space 1416 , configured to store program instructions to be executed by the processor 1402 and data accessed by the program instructions.

In some embodiments, the network interface 1404 is configured to access program instructions and data accessed by the program instructions stored remotely through a network. The I/O device 1406 includes an input device and an output device configured for enabling user interaction with the system 1400 . The input device comprises, for example, a keyboard, a mouse, etc. The output device comprises, for example, a display, a printer, etc. The storage device 1408 is configured for storing program instructions and data accessed by the program instructions. The storage device 1408 comprises, for example, a magnetic disk and an optical disk.

In some embodiments, when executing the program instructions, the processor 1402 is configured to perform method embodiments described with reference to FIGS. 12 and 13A to 13F .

In some embodiments, the program instructions are stored in a non-transitory computer readable recording medium such as one or more optical disks, hard disks and non-volatile memory devices.

Some embodiments have one or a combination of the following features and/or advantages. In some embodiments, a fishbone structure in a power network includes substantially orthogonally arranged first conductive line or segment and a plurality of second conductive segments in different conductive layers connected by interlayer vias. In some embodiments, because a shape of the second conductive segment is not determined by projecting a conductive line in a metal layer upper than the second conductive layer to the first conductive line or segment in the first conductive layer or a conductive line in a layer lower than the first conductive layer, each of the plurality of second conductive segments are routed in a preferred direction and has a width such that the wide metal spacing rule does not apply. Therefore, during routing, routing tracks adjacent to the first conductive line or segment in the first conductive layer is available for use. Several routing tracks adjacent to the first or the last second conductive segments in the plurality of second conductive segments are also not blocked from being used. Because the routing resources adjacent to the first conductive line or segment in the first conductive layer and the routing resources adjacent to the first or the last second conductive segments in the plurality of second conductive segments are available for use, fewer routing detours due to insufficient routing resources will happen during generation of signal lines. Therefore, performance and area of the chip will be improved.

In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer, a plurality of second conductive segments in a second conductive layer and a first plurality of interlayer vias between the first conductive layer and the second conductive layer. The first conductive segment is running in a first direction. The plurality of second conductive segments are running in a second direction. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The first plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line in the first conductive layer or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line in the second conductive layer.

In some embodiments, a fishbone structure in a power network includes a first conductive line in a first conductive layer, a plurality of second conductive segments in a second conductive layer and a first plurality of interlayer vias between the first conductive layer and the second conductive layer. The first conductive line is running in a first direction. The plurality of second conductive segments are running in a second direction. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The first plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive line. Each of the plurality of second conductive segments has a width such that the first conductive line has a first unit spacing with a first adjacent conductive line in the first conductive layer or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line in the second conductive layer.

In some embodiments, in a method, a first conductive line in a first conductive layer running in a first direction is generated by at least one processor. A plurality of second conductive lines in a second conductive layer running in a second direction are generated by the at least one processor. The second direction is substantially vertical to the first direction. A first plurality of interlayer vias interposed between the first conductive layer and the second conductive layer are generated at where the plurality of second conductive lines overlap with the first conductive line. Each of the second conductive lines has a width such that a first routing track adjacent to the first conductive line is available for routing or a second routing track adjacent to one of the plurality of second conductive lines is available for routing. For each of the plurality of second conductive lines, a portion of the second conductive line is removed so as to obtain a plurality of second conductive segments

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.